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8
Multiplexers and Demultiplexers
In the previous chapter, we described at length those combinational logic circuits that can be used
to perform arithmetic and related operations
...
Particular emphasis is given to the operational basics and use of these devices to design more
complex combinational circuits
...
The text has been adequately illustrated with the help of a large number of
solved examples
...
1 Multiplexer
A multiplexer or MUX, also called a data selector, is a combinational circuit with more than one
input line, one output line and more than one selection line
...
Also, multiplexers in IC form almost invariably have an ENABLE
or STROBE input, which needs to be active for the multiplexer to be able to perform its intended
function
...
If there are n selection lines,
then the number of maximum possible input lines is 2n and the multiplexer is referred to as a 2n -to-1
multiplexer or 2n × 1 multiplexer
...
1(a) and (b) respectively show the circuit representation
and truth table of a basic 4-to-1 multiplexer
...
2 and 8
...
The
8-to-1 multiplexer of Fig
...
2 is IC type number 74151 of the TTL family
...
Figure 8
...
It is a 16-to-1 multiplexer with active LOW ENABLE input and active LOW output
...
Maini
© 2007 John Wiley & Sons, Ltd
...
1

(a) 4-to-1 multiplexer circuit representation and (b) 4-to-1 multiplexer truth table
...
2

Output

Inputs

G
A
B
C

(b)

(a) 8-to-1 multiplexer circuit representation and (b) 8-to-1 multiplexer truth table
...
3

Enable

W

C

B

A

G

X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

Output
W

H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

(b)

(a) 16-to-1 multiplexer circuit representation and (b) 16-to-1 multiplexer truth table
...
1
...
8
...

8
...
Figure 8
...
The circuit functions as
follows:
• For S = 0, the Boolean expression for the output becomes Y = I0
...

Thus, inputs I0 and I1 are respectively switched to the output for S = 0 and S = 1
...
8
...
The input combinations 00,
01, 10 and 11 on the select lines respectively switch I0 , I1 , I2 and I3 to the output
...
1)
...
2):
Y = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0

(8
...
2)

Digital Electronics

272

I0
2-to-1
MUX
I1

Y

S

(a)

S

Y

0
1

I0
I1
(b)

I1
Y
I0

S
(c)
Figure 8
...


As outlined earlier, multiplexers usually have an ENABLE input that can be used to control the
multiplexing function
...
The multiplexer functions normally
...
Figure 8
...
8
...
The functional table of this modified multiplexer is also
shown in Fig
...
6
...
Some IC packages have more than
one multiplexer
...
Figure 8
...


Multiplexers and Demultiplexers

273

I0

I1
Y
I2

I3
S0

S1
S0
Figure 8
...


I1
Y
I0

S

Y

X
0
1
S

EN
0
1
1

0
I0
I1

EN
Figure 8
...


8
...
2 Implementing Boolean Functions with Multiplexers
One of the most common applications of a multiplexer is its use for implementation of combinational
logic Boolean functions
...
The input lines corresponding to each of the minterms present in the
Boolean function are made equal to logic ‘1’ state
...
As an
example, Fig
...
8(a) shows the use of an 8-to-1 MUX for implementing the Boolean function given
by the equation
fA B C =

2 4 7

(8
...
7

4-to-1 multiplexer with an ENABLE input
...
3) can be written as follows:
f A B C = A B C +A B C +A B C

(8
...
8
...
The remaining five possible minterms absent in the Boolean function are
tied to logic ‘0’
...
In this, a 2n -to-1 MUX can be
used to implement a Boolean function with n + 1 variables
...
Out of n +
1 variables, n are connected to the n selection lines of the 2n -to-1 multiplexer
...
Various input lines are tied to one of the following: ‘0’, ‘1’, the left-over
variable and the complement of the left-over variable
...
The complete procedure is illustrated for the
Boolean function given by equation (8
...

It is a three-variable Boolean function
...
We will now see how this can be implemented with a 4-to-1 multiplexer
...
The first step here is to determine the truth table of
the given Boolean function, which is shown in Table 8
...

In the next step, two of the three variables are connected to the two selection lines, with the higherorder variable connected to the higher-order selection line
...
In the third step, a table of the type shown in Table 8
...
Under the inputs
to the multiplexer, minterms are listed in two rows, as shown
...

This is easily done with the help of the truth table
...
In the given
table, these entries have been highlighted
...
If neither minterm
of a certain column is highlighted, a ‘0’ is written below that
...
8

Hardware implementation of the Boolean function given by equation (8
...

Table 8
...


Minterm

A

B

C

f(A,B,C)

0
1
2
3
4
5
6
7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
0
1
0
0
1

written
...
The input lines are then given appropriate logic status
...
Figure 8
...


Digital Electronics

276

Table 8
...

I0

I2

I3

0
4

1
5

2
6

3
7

A

A
A

I1

0

A

A

Implementation table for multiplexers
...
3

I0

I2

I3

0
1

2
3

4
5

6
7

0

C
C

I1

C

C

C

It is not necessary to choose only the leftmost variable in the sequence to be used as input to
the multiplexer
...
In the problem illustrated above, A was chosen as the variable for the input lines,
and accordingly the first row of the implementation table contained those entries where ‘A’ was
complemented and the second row contained those entries where A was uncomplemented
...
3
...
9 shows the hardware implementation
...
4 and the hardware implementation is shown in Fig
...
10
...
9

S0

A

C

F

B

Hardware implementation using a 4-to-1 multiplexer
...
4

Implementation table for multiplexers
...
10 Hardware implementation using a 4-to-1 multiplexer
...
11 Multiplexer for parallel-to-serial conversion
...
1
...
The parallel
arrangement in this case is highly undesirable as it would require a large number of transmission
lines
...
Figure 8
...
A three-bit counter controls the selection inputs
...
The conversion process takes a total of eight clock cycles
...

A variety of counter circuits of various types and complexities are, however, available in IC form
...


Example 8
...


Digital Electronics

278

Solution

• Let the Boolean function be f A B C = 1 2 5
...


The truth table for the given Boolean function is given in Table 8
...
The given function can be
implemented with a 4-to-1 multiplexer with two selection lines
...
The implementation table as drawn with the help of the truth table is given in Table 8
...

Figure 8
...


Table 8
...


C

B

A

f(A,B,C)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
0
1
1
0
1
1

Table 8
...

I0

I2

I3

0
4
1

C
C

I1
1
5
0

2
6
C

3
7
1

'1’

'0’
C

I0
I1
4-to-1
I2 MUX
I3
S1

Y

S0

B
A
Figure 8
...
1
...
13 Example 8
...


Example 8
...
13 shows the use of an 8-to-1 multiplexer to implement a certain four-variable Boolean
function
...


Solution
This problem can be solved by simply working backwards in the procedure outlined earlier for designing
the multiplexer-based logic circuit for a given Boolean function
...

From the given logic circuit, we can draw the implementation table as given in Table 8
...
The
entries in the first row (0, 1, 2, 3, 4, 5, 6, 7) and the second row (8, 9, 10, 11, 12, 13, 14, 15) are
so because the selection variable chosen for application to the inputs is the MSB variable D
...
After writing the entries in the first two rows, the entries in the third
row can be filled in by examining the logic status of different input lines in the given logic circuit
diagram
...

The Boolean expression can now be written as follows:
Y=

2 4 9 10 = D C B A + D C B A + D C B A + D C B A
= C B A D+D +D C B A+D C B A
= C B A+D C B A+D C B A
Table 8
...


I0
D
D

I1

I2

I3

I4

I5

I6

I7

0
8

1
9

2
10

3
11

4
12

5
13

6
14

7
15

0

D

1

0

D

0

0

0

280

Digital Electronics

8
...
4 Cascading Multiplexer Circuits
There can possibly be a situation where the desired number of input channels is not available in IC
multiplexers
...
For instance, 8-to-1 multiplexers can be used to construct
16-to-1 or 32-to-1 or even larger multiplexer circuits
...
If 2n is the number of input lines in the available multiplexer and 2N is the number of input lines in
the desired multiplexer, then the number of individual multiplexers required to construct the desired
multiplexer circuit would be 2N −n
...
From the knowledge of the number of selection inputs of the available multiplexer and that of the
desired multiplexer, connect the less significant bits of the selection inputs of the desired multiplexer
to the selection inputs of the available multiplexer
...
The left-over bits of the selection inputs of the desired multiplexer circuit are used to enable or
disable the individual multiplexers so that their outputs when ORed produce the final output
...
3
...
3
Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having an active LOW ENABLE input
...
The ENABLE input is taken as the fourth selection variable occupying the MSB position
...
14 shows the complete logic circuit diagram
...

The circuit functions as follows
...
If we recall the truth table of a four-variable Boolean function, S3
would be ‘0’ for the first eight entries and ‘1’ for the remaining eight entries
...
Similarly, when S3 = 1 the final output will be any of the inputs from D8 to D15 , again depending
upon the logic status of S2 , S1 and S0
...


8
...
It is a combinational logic function that has
2n (or fewer) input lines and n output lines, which correspond to n selection lines in a multiplexer
...
Let us take the case of an
octal-to-binary encoder
...
The truth table of such an encoder
is given in Table 8
...
In the truth table, D0 to D7 represent octal digits 0 to 7
...


Multiplexers and Demultiplexers

281

D0
D1
D2
D3
D4
D5
D6
D7

I0
I1
8-to-1
MUX
Y

S3

I7
E

S2
S1
S0

S2
S1
S0
F
D8
D9
D10
D11
D12
D13
D14
D15

I0
I1
8-to-1
MUX
Y
I7
E
S2
S1
S0
Figure 8
...
3
...
However, in the case of an
octal-to-binary encoder, only eight of these 256 combinations would have any meaning
...
Also, only one of the input lines
at a time is in logic ‘1’ state
...
15 shows the hardware implementation of the octal-to-binary
encoder described by the truth table in Table 8
...
This circuit has the shortcoming that it produces an
all 0s output sequence when all input lines are in logic ‘0’ state
...


8
...
1 Priority Encoder
A priority encoder is a practical form of an encoder
...
In this type of encoder, a priority is assigned to each input so that, when more
than one input is simultaneously active, the input with the highest priority is encoded
...
Let us assume that the octalto-binary encoder described in the previous paragraph has an input priority for higher-order digits
...
In
that case, only D7 will be encoded and the output will be 111
...
15 Octal-to-binary encoder
...
8

Truth table of an encoder
...
9
...
As another example, Fig
...
16 shows the logic symbol and truth
table of a 10-line decimal to four-line BCD encoder providing priority encoding for higher-order
digits, with digit 9 having the highest priority
...


Multiplexers and Demultiplexers

Table 8
...


D0

D1

D2

D3

D4

D5

D6

D7

A

B

C

1
X
X
X
X
X
X
X

0
1
X
X
X
X
X
X

0
0
1
X
X
X
X
X

0
0
0
1
X
X
X
X

0
0
0
0
1
X
X
X

0
0
0
0
0
1
X
X

0
0
0
0
0
0
1
X

0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Figure 8
...


Some of the encoders available in IC form provide additional inputs and outputs to allow expansion
...
ENABLE-IN (EI) and
ENABLE-OUT (EO) terminals on this IC allow expansion
...


Digital Electronics

284

Example 8
...
the output bits are A (MSB), B and C (LSB)
...
If the data inputs and outputs are active
when LOW, determine the logic status of output bits for the following logic status of data inputs:
(a) All inputs are in logic ‘0’ state
...

(c) D7 is in logic ‘0’ state
...


Solution
(a) Since all inputs are in logic ‘0’ state, it implies that all inputs are active
...

(b) Inputs D5 to D7 are the ones that are active
...
Therefore,
the output bits are A = 0, B = 0 and C = 0
...
Since D7 has the highest priority, it will be encoded irrespective of the logic status
of other inputs
...


Example 8
...


Solution
The truth table for such a priority encoder is given in Table 8
...

The Boolean expressions for the two output lines X and Y are given by the equations
X = D2 D3 + D3 = D2 + D3

(8
...
6)

Figure 8
...
5)
and (8
...

Table 8
...
5
...
17 Example 8
...


8
...
It
routes the information present on the input line to any of the output lines
...
A decoder is a
special case of a demultiplexer without the input line
...
18(a) shows the circuit representation
of a 1-to-4 demultiplexer
...
18(b) shows the truth table of the demultiplexer when the input
line is held HIGH
...
Figure 8
...
If there are some unused or ‘don’t care’ combinations in the n-bit
code, then there will be fewer than 2n output lines
...
18 1-to-4 demultiplexer
...
19 Circuit representation of 2-to-4, 3-to-8 and 4-to-16 line decoders
...
If, in the three-bit input code, the only used three-bit
combinations are 000, 001, 010, 100, 110 and 111 (011 and 101 being either unused or don’t care
combinations), then this decoder will have only six output lines
...

A decoder can generate a maximum of 2n possible minterms with an n-bit binary code
...
8
...
This
logic circuit, as we will see, implements a 3-to-8 line decoder function
...
From
the truth table given along with the logic diagram it is clear that, for any given input combination,
only one of the eight outputs is in logic ‘1’ state
...
In the present case, D0 , D1 , D2 , D3 ,
D4 , D5 , D6 and D7 respectively represent the following minterms:
D0 → A B C D1 → A B C D2 → A B C D3 → A B C
D4 → A B C D5 → A B C D6 → A B C D7 → A B C

8
...
1 Implementing Boolean Functions with Decoders
A decoder can be conveniently used to implement a given Boolean function
...
Figure 8
...
7)

In general, an n-to-2n decoder and m external OR gates can be used to implement any combinational
circuit with n inputs and m outputs
...
Let us consider the case of implementing a four-variable
Boolean function with 12 minterms using a 4-to-16 line decoder and an external OR gate
...
In all such cases, where the number of minterms in a given
Boolean function with n variables is greater than 2n /2 (or 2n−1 , the complement Boolean function will
have fewer minterms
...
The output will be nothing but the given Boolean function
...
20 Logic diagram of a 3-to-8 line decoder
...
21 Implementing Boolean functions with decoders
...
3
...
More than one of these devices of a given size may be used to construct a decoder
that can handle a larger number of input and output lines
...
The basic steps to be followed to
carry out the design are as follows:
1
...

2
...

3
...

4
...
The concept is further illustrated in
solved example 8
...


Example 8
...


Solution
A decoder with an OR gate at the output can be used to implement the given Boolean function
...
The truth table of the full adder is given in Table 8
...
8
...

From the truth table, Boolean functions for SUM and CARRY outputs are given by the following
equations:
Sum output S =

1 2 4 7

(8
...
9)

Multiplexers and Demultiplexers

289

Example 8
...


Table 8
...
22 Example 8
...


Example 8
...
Hardware implement the Boolean function F
with a suitable decoder and an external OR/NOR gate having the minimum number of inputs
...
This implies that the function can be
implemented with a 3-to-8 line decoder and a five-input OR gate
...
The second
option uses a NOR gate with fewer inputs and therefore is used instead
...
Therefore,
F = 1, 3, 4
...
23 shows the hardware implementation of Boolean function F
...
23 Example 8
...


Example 8
...


Solution
Let us assume that A (LSB), B, C and D (MSB) are the input variables for the 4-to-16 line decoder
...
If we recall the 16 possible input combinations from 0000 to 1111 in the
case of a 4-to-16 line decoder, we find that the first eight combinations have D = 0, with CBA going
through 000 to 111
...
If we use the D-bit as the ENABLE input for the less significant 3-to-8 line decoder and the
D-bit as the ENABLE input for the more significant 3-to-8 line decoder, the less significant 3-to-8
line decoder will be enabled for the less significant eight of the 16 input combinations, and the more
significant 3-to-8 line decoder will be enabled for the more significant of the 16 input combinations
...
24 shows the hardware implementation
...


Example 8
...
25 shows the logic symbol of IC 74154, which is a 4-to-16 line decoder/demultiplexer
...
Determine the logic status of all 16 output lines for the following
conditions:
(a) D = HIGH, C = HIGH, B = LOW, A = HIGH, G1 = LOW and G2 = LOW
...

(c) D = HIGH, C = HIGH, B = LOW, A = HIGH, G1 = HIGH and G2 = HIGH
...
Also, both ENABLE inputs need to be active for the decoder
to function owing to the indicated ANDing of the two ENABLE inputs
...
24 Example 8
...


74154
1(A)
2(B)
4(C)
8(D)

G1
G2

&

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Figure 8
...
9
...
For the given logic status of the input lines, decoder output line
13 will be active and therefore LOW
...

(b) Since neither ENABLE input is active, all decoder outputs will be inactive and in the logic HIGH
state
...


Example 8
...
9 is to be used as a 1-of-16 demultiplexer
...
Draw the logic diagram indicating the logic status of
ENABLE inputs and DCBA inputs and the point of application of the pulsed waveform
...
26 shows the logic diagram
...
This means that output line 9 is activated
...
This means that output line 15 is activated
...
8
...
This means
that either both ENABLE inputs are active (when the input waveform is in the logic LOW state) or
inactive (when the input waveform is in the logic HIGH state)
...
If the external

74154

'1’

1(A)
2(B)

External
Control

4(C)
8(D)

G1
G2

&

Figure 8
...
10
...

In essence, the logic status of the input waveform is reproduced at either line 9 or line 15, depending
on whether the external control signal is LOW or HIGH
...
4 Application-Relevant Information
Table 8
...
Application-relevant information such as the pin connection diagram, truth table, etc
...

Table 8
...

IC Type
number

Function

Logic
family

7442
74138
74139
74145
74147
74148
74150
74151
74152
74153
74154
74155
74156
74157
74158
74247
74248
74251
74253
74256
74257
74258
74259
74298
74348
74353
74398
74399
4019
4028
40147
4511
4512
4514

1-of-10 decoder
1-of-8 decoder/demultiplexer
Dual 1-of-4 decoder/demultiplexer
1-of-10 decoder/driver (open collector)
10-line to four-line priority encoder
Eight-line to three-line priority encoder
16-input multiplexer
Eight-input multiplexer
Eight-input multiplexer
Dual four-input multiplexer
4-of-16 decoder/demultiplexer
Dual 1-of-4 decoder/demultiplexer
Dual 1-of-4 decoder/demultiplexer (open collector)
Quad two-input noninverting multiplexer
Quad two-input inverting multiplexer
BCD to seven-segment decoder/driver (open collector)
BCD to seven-segment decoder/driver with Pull-ups
Eight-input three-state multiplexer
Dual four-input three-state multiplexer
Dual four-bit addressable latch
Quad two-input non-inverting three-state multiplexer
Quad two-input inverting three-state multiplexer
Eight-bit addressable latch
Dual two-input multiplexer with output latches
Eight-line to three-line priority encoder (three-state)
Dual four-input multiplexer
Quad two-input multiplexer with output register
Quad two-input multiplexer with output register
Quad two-input multiplexer
1-of-10 decoder
10-line to four-line BCD priority encoder
BCD to seven-segment latch/decoder/driver
Eight-input three-state multiplexer
1-of-16 decoder/demultiplexer with input latch

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

(continued overleaf )

Digital Electronics

294

Table 8
...


IC Type
number

Function

Logic
family

4515
4532
4539
4543

1-of-16 decoder/demultiplexer with input latch
Eight-line to three-line priority encoder
Dual four-input multiplexer
BCD to seven-segment latch/decoder/driver for LCD
displays
Dual 1-of-4 decoder/demultiplexers
Dual 1-of-4 decoder/demultiplexers
Dual four-bit addressable latch
Eight-bit addressable latch
Dual two-input multiplexer with latch and common
reset
Dual multiplexer with latch
Quad two-input multiplexer (non-inverting)
Quad two-input multiplexer (inverting)
3-to-8 line decoder (LOW)
3-to-8 line decoder (HIGH)
Eight-line multiplexer
Eight-input priority encoder
Dual 2-to-4 line decoder (LOW)
Dual 2-to-4 line decoder (HIGH)
Quad two-input multiplexer/latch
Dual 4-to-1 multiplexer

CMOS
CMOS
CMOS
CMOS

4555
4556
4723
4724
10132
10134
10158
10159
10161
10162
10164
10165
10171
10172
10173
10174

CMOS
CMOS
CMOS
CMOS
ECL
ECL
ECL
ECL
ECL
ECL
ECL
ECL
ECL
ECL
ECL
ECL

Review Questions
1
...
Is it possible to enhance the capability of an available multiplexer in terms of the number of input
lines it can handle by using more than one device? If yes, briefly describe the procedure to do so,
with the help of an example
...
What is an encoder? How does a priority encoder differ from a conventional encoder? With the
help of a truth table, briefly describe the functioning of a 10-line to four-line priority encoder with
active LOW inputs and outputs and priority assigned to the higher-order inputs
...
What is a demultiplexer and how does it differ from a decoder? Can a decoder be used as a
demultiplexer? If yes, from where do we get the required input line?
5
...

6
...


Multiplexers and Demultiplexers

295

Problems
1
...

(i) Fig
...
27(a); (ii) Fig
...
27(b)

'0’ '1’

I0
I1
I2
I3
I4
I5
I6
I7

8-to-1
MUX

F

S2 S1 S0

A B C
(a)

'0’

I0

'1’

I1

A

I2
I3

4-to-1
MUX

S1

S0

B

F

C
(b)

Figure 8
...


2
...

Fig
...
28

Digital Electronics

296

D0

I0
I1

D7

I7
E
S0
S1
S2

D8

I0
I1

S0
S1
S2

D15
0
S3

S4

S1

1
2-to-4
2
Decoder
S2
3

I7
E
S0
S1
S2

8-to-1
MUX

Y

8-to-1
MUX Y

F
D16

I0
I1

8-to-1
MUX Y
D23

I7
E
S0
S1
S2

D24

I0
I1

D31

I7
E
S0
S1
S2

8-to-1
MUX Y

Figure 8
...


Multiplexers and Demultiplexers

297

3
...
8
...


Figure 8
...


4-to-1 multiplexer
4
...

Fig
...
30

0
Difference
1
A

2

B

2

Bin

2

2
1
0

2
3-to-8
Decoder

3
4
5
6
7

Figure 8
...


Borrow Out

298

Digital Electronics

Further Reading
1
...

3
...

5
...
L
...
, USA
...
L
...
, USA
...
J
...
, NJ, USA
...
P
...

Rafiquzzaman, M
...

6
...
and Kime, C
...
(2003) Logic and Computer Design Fundamentals, Prentice-Hall Inc
...




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