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MICROPROCESSOR 8085
• Reference Book:
– Ramesh S
...

• Week 2 - Architecture of 8085
• Week 3 - Addressing Modes and Instruction set of 8085
• Week 4 – Interrupts of 8085
• Week 5 onwards – Peripherals
...
Includes memory, I/O
etc
...


What is a Microprocessor?
• The word comes from the combination micro and
processor
...
In
this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s
...
It is a general term that
describes all manipulation
...


What about micro?
• Micro is a new addition
...

• These devices performed the required operation, but were too
large and too slow
...
All of
the components that made up the processor were now
placed on a single piece of silicon
...
The “Micro”Processor
was born
...

– It went directly from discrete elements to a
single chip
...


• So, What is a microprocessor?

Definition of the Microprocessor
The microprocessor is a programmable device
that takes in numbers, performs on them
arithmetic or logical operations according to
the program stored in memory and then
produces other numbers as a result
...
)
• Lets expand each of the underlined words:
– Programmable device: The microprocessor can perform
different sets of operations on the data it receives depending
on the sequence of instructions supplied in the given
program
...

– Instructions: Each microprocessor is designed to execute a
specific group of operations
...
This instruction set defines what the
microprocessor can and cannot do
...
)
– Takes in: The data that the microprocessor
manipulates must come from somewhere
...

• These are devices that bring data into the system
from the outside world
...


Definition (Contd
...
It
only understands binary numbers
...

The microprocessor recognizes and processes a group of bits
together
...

The number of bits in a Microprocessor’s word, is a measure of its
“abilities”
...
)
– Words, Bytes, etc
...

– They processed information 8-bits at a time
...
They can handle large numbers, but in
order to process these numbers, they broke them into 8-bit pieces
and processed each group of 8-bits separately
...

– A group of 8-bits were referred to as a “half-word” or “byte”
...

– Also, 32 bit groups were given the name “long word”
...
)
– Arithmetic and Logic Operations:
• Every microprocessor has arithmetic operations such as add
and subtract as part of its instruction set
...

– Some of the newer ones will have complex operations such as
square root
...

Such as AND, OR, XOR, shift left, shift right, etc
...


Definition (Contd
...

– Memory is a collection of storage devices
...
Also, in most kinds of memory, these
storage devices are grouped into groups of 8
...
So, one can only read or
write in terms of bytes to and form memory
...

It is measured in Kilos, Megas and lately Gigas
...
So, a KB (KiloByte) is 1024
bytes
...


Definition (Contd
...
Then as the microprocessor starts
to execute the instructions, it brings the instructions
from memory one at a time
...

– The microprocessor reads (brings in) the data from
memory when it needs it and writes (stores) the results
into memory when it is done
...
)
– Produces: For the user to see the result of the
execution of the program, the results must be
presented in a human readable form
...

• This can be the monitor, a paper from the printer, a
simple LED or many other forms
...

– The Arithmetic/Logic Unit (ALU)
– The Control Unit
...


Organization of a microprocessorbased system
• Let’s expand the picture a bit
...
It provides
this information to the microprocessor whenever
it is needed
...
This sub-system
includes:
– The registers inside the microprocessor
– Read Only Memory (ROM)
• used to store information that does not change
...

• used to store information supplied by the user
...


Memory Map and Addresses
• The memory map is a picture representation
of the address range and shows where the
different memory chips are located within
the address range
...

– The microprocessor then reads these instructions and
whatever data is needed from memory, executes the
instructions and places the results either in memory or
produces it on an output device
...

• To use the right names for the cycles:
– The microprocessor fetches each instruction,
– decodes it,
– Then executes it
...


Machine Language
• The number of bits that form the “word” of a
microprocessor is fixed for that particular
processor
...

• For example an 8-bit microprocessor can have at most 28 = 256
different combinations
...

– Certain patterns are chosen and assigned specific
meanings
...

– The complete set of patterns makes up the
microprocessor’s machine language
...

– The 8085 uses a total of 246 bit patterns to form its
instruction set
...

• The reason for the difference is that some (actually most)
instructions have multiple different formats
...

• For example, the combination 0011 1100 which translates into
“increment the number in the register called the accumulator”,
is usually entered as 3C
...

– However, it still is difficult to understand what a program
written in hexadecimal does
...

– These codes are called “mnemonics”
...


Assembly Language
• Using the same example from before,
– 00111100 translates to 3C in hexadecimal (OPCODE)
– Its mnemonic is: “INR A”
...


• Another example is: 1000 0000,
– Which translates to 80 in hexadecimal
...

– “Add register B to the accumulator and keep the result in the
accumulator”
...

– In other words, they are not transferable from one
microprocessor to a different one
...

– The 8085 machine language is very different from that
of the 6800
...

– A program written for the 8085 cannot be executed on
the 6800 and vice versa
...

• The programmer translates each assembly language instruction
into its equivalent hexadecimal code (machine language)
...


– The other possibility is a program called an
“assembler”, which does the translation automatically
...

ALU: performs data processing function
...

Interrupts
Internal data bus

The ALU
• In addition to the arithmetic & logic circuits, the
ALU includes the accumulator, which is part of
every arithmetic & logic operation
...
This temporary register is not
accessible by the programmer
...

• The Program Counter (PC)
– This is a register that is used to control the sequencing
of the execution of instructions
...

– Since it holds an address, it must be 16 bits wide
...

– The memory this register points to is a special
area called the stack
...

– The stack is usually accessed in a Last In First
Out (LIFO) fashion
...
125 MHz internally
– 6
...

• The other 8 address bits are multiplexed (time
shared) with the 8 data bits
...

• During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of
the execution, they carry the 8 data bits
...


Demultiplexing AD7-AD0
– From the above description, it becomes obvious
that the AD7– AD0 lines are serving a dual purpose
and that they need to be demultiplexed to get all the
information
...
However, the low order
bits remain for only one clock period and they
would be lost if they are not saved externally
...

– To make sure we have the entire address for the
full three clock cycles, we will use an external latch
to save the value of AD7– AD0 when it is carrying
the address bits
...


Demultiplexing AD7-AD0
8085
A15-A8

ALE
AD7-AD0

Latch

A7- A0

D7- D0

– Given that ALE operates as a pulse during T1, we will
be able to latch the address
...


Demultiplexing the Bus AD7 – AD0
•
•
•
•

The high order address is placed on the address bus and hold for 3 clk
periods,
The low order address is lost after the first clk period, this address
needs to be hold however we need to use latch
The address AD7 – AD0 is connected as inputs to the latch 74LS373
...

• However, the 8085 only uses 246 combinations that represent a
total of 74 instructions
...


– These instructions can be grouped into five different
groups:
•
•
•
•
•

Data Transfer Operations
Arithmetic Operations
Logic Operations
Branch Operations
Machine Control Operations

Instruction and Data Formats
• Each instruction has two parts
...

• This part is called the “opcode” (operation code)
...


Data Transfer Operations
– These operations simply COPY the data from the
source to the destination
...

Data Byte to a register or memory location
...

Data between an I\O Device and the accumulator
...


The LXI instruction
• The 8085 provides an instruction to place
the 16-bit data into the register pair in one
step
...

• The upper two digits are placed in the 1st register of
the pair and the lower two digits in the 2nd
...

– The memory location will become the “memory” register M
...


– Which memory location?

• The memory location is identified by the contents
of the HL register pair
...


Using the Other Register Pairs
– There is also an instruction for moving data from
memory to the accumulator without disturbing the
contents of the H and L register
...

– This instruction only uses the BC or DE pair
...


Indirect Addressing Mode
• Using data in memory directly (without loading
first into a Microprocessor’s register) is called
Indirect Addressing
...

– The HL register pair is always used in conjunction with
the memory register “M”
...


Arithmetic Operations
– Addition (ADD, ADI):
– Any 8-bit number
...

– The contents of a memory location
...


– Subtraction (SUB, SUI):
– Any 8-bit number
– The contents of a register
– The contents of a memory location

• Can be subtracted from the contents of the accumulator
...


Arithmetic Operations Related to
Memory
• These instructions perform an arithmetic operation
using the contents of a memory location while
they are still in memory
...


– All of these use the contents of the HL register pair to
identify the memory location being used
...

• No need to disturb the contents of the accumulator
...

• INX Rp
• DCX Rp

(Increment the 16-bit number in the register pair)
(Decrement the 16-bit number in the register pair)

– The register pair is incremented or decremented as one
entity
...
It is taken care of automatically
...

– ANA, ANI, ORA, ORI, XRA and XRI
• Source: Accumulator and
– An 8-bit number
– The contents of a register
– The contents of a memory location

• Destination: Accumulator
ANA R/M
ANI #

AND Accumulator With Reg/Mem
AND Accumulator With an 8-bit number

ORA
ORI

R/M
#

OR Accumulator With Reg/Mem
OR Accumulator With an 8-bit number

XRA
XRI

R/M
#

XOR Accumulator With Reg/Mem
XOR Accumulator With an 8-bit number

Logic Operations
– Complement:
• 1’s complement of the contents of the accumulator
...

– RLC
– RAL
– RRC
– RAR

Rotate the accumulator left
...

Rotate the accumulator left through the carry
...

Rotate the accumulator right
...

Rotate the accumulator right through the carry
...


RLC vs
...

– CMP

R/M

– CPI

#

Compare the contents of the register
or memory location to the contents of
the accumulator
...


• The compare instruction sets the flags (Z, Cy, and S)
...

A – (R / M / #)

Branch Operations
• Two types:
– Unconditional branch
...


– Conditional branch
...


Unconditional Branch
– JMP

Address

• Jump to the address specified (Go to)
...


– RET
• Return from a subroutine
...


Conditional Branch
– Go to new location if a specified condition is met
...


• JNZ Address (Jump on NOT Zero)
– Go to address specified if the Zero flag is not set
...


• JNC Address (Jump on No Carry)
– Go to the address specified if the Carry flag is not set
...


Machine Control
– HLT
• Stop executing the program
...

• Usually used for delay or to replace instructions
during debugging
...
It will occupy a different
number of memory bytes
...

– The exception is any instruction that contains
immediate data or a memory address
...

– One for the opcode and the other for the 8-bit data
...

– One for the opcode, and the other two for the 16-bit address
...

– MVI

A, 32

• Operation: MVI A
• Operand: The number 32
• Binary Code:

0011 1110 3E 1st byte
...


Instruction with a Memory
Address
• Operation: go to address 2085
...

2nd byte
3rd byte

Addressing Modes
• The microprocessor has different ways of
specifying the data for the instruction
...

• The 8085 has four addressing modes:
–
–
–
–

Implied
Immediate
Direct
Indirect

CMA
MVI B, 45
LDA 4000
LDAX B

• Load the accumulator with the contents of the memory location
whose address is stored in the register pair BC)
...


– It is important to recognize that the microprocessor
deals with 0’s and 1’s
...

• It is the job of the user to add a meaning to these strings
...

– There are four ways of reading this value:
• It is an unsigned integer expressed in binary, the equivalent
decimal number would be 65
...
That would make it, 41
...
That would make it the
letter A
...


ASCII stands for American Standard Code for Information Interchange
...

• A loop is set up with a conditional jump
instruction that loops back or not depending on
whether the count has reached the termination
count
...

Initialize

Body of loop

Update the count

No

Is this
Final
Count?
Yes

Sample ALP for implementing a loop
Using DCR instruction
MVI C, 15H
LOOP

DCR C
JNZ LOOP

Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for a
maximum count of 255 times
...

– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags
...


Using a Register Pair as a Loop
Counter
• The following is an example of a loop set
up with a register pair as the loop counter
...

• Knowing the combinations of cycles, one can
calculate how long such an instruction would
require to complete
...

– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State
...
of T-States / Frequency
• For example a “MVI” instruction uses 7 T-States
...
5 µSeconds
to complete
...

• The following is an example of a delay
loop:
MVI C, FFH
LOOP DCR C
JNZ LOOP

7 T-States
4 T-States
10 T-States

• The first instruction initializes the loop counter and is
executed only once requiring only 7 T-States
...


Delay Loops (Contd
...

• Therefore, we must deduct 3 T-States from the total
delay to get an accurate delay calculation
...


Delay Loops (Contd
...


Using a Register Pair as a Loop
Counter
• Using a single register, one can repeat a loop for a
maximum count of 255 times
...

– A minor problem arises in how to test for the final
count since DCX and INX do not modify the flags
...


Using a Register Pair as a Loop
Counter
• The following is an example of a delay loop
set up with a register pair as the loop
counter
...


Nested Loops

Initialize loop 2
Body of loop 2

• Nested loops can be
easily setup in
Assembly language by
using two registers for
the two loop counters
and updating the right
register in the right
loop
...


Initialize loop 1
Body of loop 1
Update the count1

No

Is this
Final
Count?

Yes
Update the count 2

No

Is this
Final
Count?
Yes

Nested Loops for Delay
• Instead (or in conjunction with) Register Pairs, a
nested loop structure can be used to increase the
total delay produced
...

– Start with the inner loop, then plug that delay in
the calculation of the outer loop
...


– TDelay = 7 + 57405 = 57412 T-States

• Total Delay
– TDelay = 57412 X 0
...
706 mSec

Increasing the delay
• The delay can be further increased by using
register pairs for each of the loop counters
in the nested loops setup
...


Timing Diagram
Representation of Various Control signals generated during
Execution of an Instruction
...

•Lower Address/Data bus
•ALE
•RD
•WR
•IO/M

Timing Diagram
Instruction:
A000h

MOV A,B

Corresponding Coding:
A000h

78

Timing Diagram
Instruction:
A000h

MOV A,B

Corresponding Coding:
A000h

78

OFC

8085

Memory

Timing Diagram
Instruction:
A000h

T1

MOV A,B

T2

T3

T4

A0h

A15- A8 (Higher Order Address bus)

Corresponding Coding:
A000h

00h

78h

78
ALE
RD

WR

OFC

8085

Memory

IO/M

Op-code fetch Cycle

Timing Diagram
Instruction:
A000h

MVI A,45h

Corresponding Coding:
A000h

3E

A001h

45

Timing Diagram
Instruction:
A000h

MVI A,45h

Corresponding Coding:
A000h

OFC

3E

MEMR

A001h

45
8085

Memory

Timing Diagram
T1

T2

T3

T4

T5

T6

A0h

T7

A0h

A15- A8 (Higher Order Address bus)
00h

3Eh

01h

45h

DA7-DA0 (Lower order address/data Bus)

Instruction:
A000h MVI A,45h

ALE

Corresponding Coding:
A000h

3E

A001h

RD

45
WR

IO/M

Op-Code Fetch Cycle

Memory Read Cycle

Timing Diagram
Instruction:
A000h

LXI A,FO45h

Corresponding Coding:
A000h

21

A001h

45

A002h

F0

Timing Diagram
Instruction:
A000h

LXI A,FO45h

Corresponding Coding:

OFC

A000h

MEMR

21

A001h

45

A002h

F0

MEMR

8085

Memory

Timing Diagram

T1

T2

T3

Memory Read Cycle

Memory Read Cycle

Op-Code Fetch Cycle

T4

T5

A0h

T6

T7

T8

T9

A0h

T10

A0h

A15- A8 (Higher Order Address bus)
00h

21h

DA7-DA0 (Lower order address/data Bus)

ALE
RD

WR

IO/M

01h

45h

02h

F0h

Timing Diagram
Instruction:
A000h

MOV A,M

Corresponding Coding:
A000h

7E

Timing Diagram
Instruction:
A000h

MOV A,M
OFC

Corresponding Coding:
A000h

MEMR

7E
8085

Memory

Timing Diagram
T1

T2

T3

T4

T5

T6

A0h

T7

Content Of Reg H

A15- A8 (Higher Order Address bus)
00h

Instruction:

7Eh

L Reg

Content Of M

DA7-DA0 (Lower order address/data Bus)

A000h MOV A,M
Corresponding Coding:
A000h

7E

ALE
RD

WR

IO/M

Op-Code Fetch Cycle

Memory Read Cycle

Timing Diagram
Instruction:
A000h

MOV M,A

Corresponding Coding:
A000h

77

Timing Diagram
Instruction:
A000h

MOV M,A
OFC

Corresponding Coding:
A000h

MEMW

77
8085

Memory

Timing Diagram
T1

T2

T3

T4

T5

T6

A0h

T7

Content Of Reg H

A15- A8 (Higher Order Address bus)
00h

Instruction:

7Eh

L Reg

Content of Reg A

DA7-DA0 (Lower order address/data Bus)

A000h MOV M,A
Corresponding Coding:
A000h

77

ALE
RD

WR

IO/M

Op-Code Fetch Cycle

Memory Write Cycle

Chapter 9
Stack and Subroutines

The Stack
• The stack is an area of memory identified by the
programmer for temporary storage of information
...

– Last In First Out
...

– In other words, the programmer
defines the bottom of the stack
and the stack grows up into
reducing address range
...

• In the 8085, the stack is defined by setting the SP
(Stack Pointer) register
...


Saving Information on the Stack
• Information is saved on the stack by PUSHing it
on
...


• The 8085 provides two instructions: PUSH and
POP for storing information on the stack and
retrieving it back
...


The PUSH Instruction
• PUSH B
– Decrement SP
– Copy the contents of register B to the memory
location pointed to by SP
– Decrement BSP C
F3
12
– Copy the contents of register C to the memory
location pointed to by SP F3
FFFB
FFFC
FFFD
FFFE
FFFF

12

SP

The POP Instruction
• POP D
– Copy the contents of the memory location
pointed to by the SP to register E
– Increment SP
– Copy the contents of the memory location
D
E
F3
12
pointed to by the SP to register D
– Increment SP
F3
SP
FFFB
FFFC
FFFD
FFFE
FFFF

12

Operation of the Stack
• During pushing, the stack operates in a
“decrement then store” style
...


• During poping, the stack operates in a “use then
increment” style
...


• The SP pointer always points to “the top of the
stack”
...

PUSH B
PUSH D

...

– This register pair is made up of the Accumulator and
the Flags registers
...

– The result is that the contents of the Accumulator and
the status of the Flags are returned to what they were
before the operations were executed
...

– Rather than repeat the same instructions several times,
they can be grouped into a subroutine that is called
from the different locations
...

– However, it is customary to place subroutines
separately from the main program
...

– The CALL instruction is used to redirect
program execution to the subroutine
...


The CALL Instruction
• CALL 4000H
– Push the address of the instruction
immediately following the CALL onto the
stack
2000
CALL 4000
2003
– Load the program PC 2 0 0 3with the 16-bit
counter
address supplied with the CALL instruction
...

2003
PC
4014
4015


...

– You must set the SP correctly BEFORE using the
CALL instruction
...

– Do not modify the stack pointer in a subroutine
...


Passing Data to a Subroutine
• In Assembly Language data is passed to a
subroutine through registers
...


• The other possibility is to use agreed upon
memory locations
...


Call by Reference and Call by
Value
• If the subroutine performs operations on the
contents of the registers, then these modifications
will be transferred back to the calling program
upon returning from a subroutine
...

– The original values are restored before execution
returns to the calling program
...

• There has to be as many POP’s as there are
PUSH’s
...


• It is not advisable to place PUSH or POP inside a
loop
...

– The same conditions used with conditional JUMP
instructions can be used
...

CNC, call subroutine if Carry flag is not set
RC, return from subroutine if Carry flag is set
RNC, return from subroutine if Carry flag is not set
Etc
...


– Has a single exit point
• There should be one return statement from any subroutine
...


The Design and Operation of Memory
Memory in a microprocessor system is where
information (data and instructions) is kept
...
)

The simple view of RAM is that it is made up of registers that
are made up of flip-flops (or memory elements)
...


ROM on the other hand uses diodes instead of the flip-flops
to permanently hold the information
...

Identify the memory location (using the rest of the
address bus)
...

2

Tri-State Buffers
An important circuit element that is used
extensively in memory
...

When this circuit is in high impedance mode it looks
as if it is disconnected from the output completely
...

The first input behaves like the normal input for the
circuit
...





If it is set high, the output follows the proper circuit
behavior
...


Input

Output

Enable

OR

Input

Output

Enable

4

The Basic Memory Element

The basic memory element is similar to a D
latch
...

It has an enable input and an output on which
data comes out
...

Data is always present on the input and the output is
always set to the contents of the latch
...

Data Input

D

WR

Data Output
Q
RD

Enable
EN

6

The Basic Memory Element
The WR signal controls the input buffer
...

So, if WR is 0 the input data reaches the latch input
...


The RD signal controls the output in a similar
manner
...


D2

Q

EN

Q

D

EN

Q

EN

o

o

D1

D2

o

RD

D0

9

D3

Externally Initiated Operations
External devices can initiate (start) one of the 4
following operations:
Reset


All operations are stopped and the program counter is reset to 0000
...

This routine “handles” the interrupt, (perform the necessary
operations)
...


10

A group of Memory Registers
If we represent each memory location (Register) as
a block we get the following
I0

I1

I2

WR

Input Buffers

EN0

Memory Reg
...
1

EN2

Memory Reg
...
3

RD

I3

Output Buffers

O0

O1

O2

O3
11

The Design of a Memory Chip
Using the RD and WR controls we can determine the
direction of flow either into or out of memory
...

What we have just designed is a memory with 4
locations and each location has 4 elements (bits)
...

12

The Enable Inputs
How do we produce these enable line?
Since we can never have more than one of these
enables active at the same time, we can have them
encoded to reduce the number of lines coming into
the chip
...


13

The Design of a Memory Chip
So, the previous diagram would now look like the
following:
I
I
I
I
0

WR

A1
A0

1

2

3

Input Buffers

A
d
d
r
e
s
s

D
e
c
o
d
e
r

Memory Reg
...
1
Memory Reg
...
3
Output Buffers

RD
O0

O1

O2

O3
14

The Design of a Memory Chip

WR

Since we have tri-state buffers on both the inputs
and outputs of the flip flops, we can actually use
one set of pins only
...
now look likeDthis:
would 0
d e

D0

0

A1
A0

RD

d
r
e
s
s

c
o
d
e
r

Memory Reg
...
2

D2

A0

D2

Memory Reg
...

The address is applied to the address decoder which
generates a single Enable signal to turn on only
one of the memory registers
...

16

Dimensions of Memory
Memory is usually measured by two numbers: its length
and its width (Length X Width)
...

The width is the number of bits in each location
...

# of memory locations = 2( # of address lines)



So, a memory chip with 10 address lines would have

210 = 1024 locations (1K)



Looking at it from the other side, a memory chip with 4K locations
would need

Log2 4096=12 address lines

17

The 8085 and Memory
The 8085 has 16 address lines
...

Then it will need 1 memory chip with 64 k locations, or 2
chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K
chips, etc
...
The chip will only work if an active signal is
applied on that input
...

These address lines are decoded to generate the 2n
necessary CS inputs for the memory chips to be used
...

We will need to use 2 inputs and a decoder to
identify which chip will be used at what time
...

20

Chip Selection Example
RD
WR

D0
D1
RD WR

RD WR

RD WR

RD WR

A0

A0

A0

A0

A1

A1

A1

A1

CS

CS

CS

CS

A0
A1

A2

2 X4

A3

Decoder

21

Memory Map and Addresses
The memory map is a picture representation of
the address range and shows where the different
memory chips are located within the address
range
...

An example for the address range and its relationship to the
memory chips would be the Post Office Boxes in the post
office
...
(memory
locations)
• The boxes are grouped into groups
...

23

Address Range of a Memory Chip
The above example can be modified slightly to make it closer
to our discussion on memory
...

• Let’s also say that these are grouped into 10 groups of 100 boxes each
...


We can look at the box number as if it is made up of two
pieces:
• The group number and the box’s index within the group
...


The upper digit of the box number identifies the group and the lower two
digits identify the box within the group
...
So, it can
address a total of 64K memory locations
...

The 1K memory chip needs 10 address lines to
uniquely identify the 1K locations
...

25

The 8085 and Address Ranges
Now, we can break up the 16-bit address of the 8085
into two pieces:
Chip Selection

Location Selection within the Chip

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Depending on the combination on the address lines A15 - A10 , the
address range of the specified chip is determined
...


Keep in mind that the 10 address lines on the chip gives a range of
00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips
...

Changing the combination of the address bits connected to
the chip select changes the address range for the memory
chip
...

In the second case, it occupies the piece identified as
after
...
Low-Order Address Lines
The address lines from a microprocessor can be
classified into two types:
High-Order


Used for memory chip selection

Low-Order


Used for location selection within a memory chip
...

30

Data Lines
All of the above discussion has been regarding memory
length
...

We said that the width is the number of bits in each
memory word
...

What if they don’t?




It is very common to find memory chips that have only 4 bits per
location
...
One chip will supply 4
of the data bits per address and the other chip supply the other 4 data
bits for the same address
...

– The process starts from the I/O device
– The process is asynchronous
...

– The Microprocessor should respond to it as soon as
possible
...

– Each interrupt will most probably have its own ISR
...

• There are two ways of redirecting the execution to
the ISR depending on whether the interrupt is
vectored or non-vectored
...
This Interrupt Enable flip flop is
controlled using the two instructions “EI” and
“DI”
...

– The non-maskable interrupt is not affected by the value
of the Interrupt Enable flip flop
...

– The INTR input
...

• INTR is maskable using the EI/DI instruction pair
...
5, RST 6
...
5 are all automatically
vectored
...
5, RST 6
...
5 are all maskable
...
5
Yes
Yes
RST 6
...
5
Yes
Yes
TRAP
No
Yes

Interrupt Vectors and the Vector
Table
• An interrupt vector is a pointer to where the ISR is
stored in memory
...

– The IVT is usually located in memory page 00 (0000H
- 00FFH)
...

– The IVT is divided into several blocks
...
The interrupt process should be enabled using the
EI instruction
...
The 8085 checks for an interrupt during the
execution of every instruction
...
If there is an interrupt, the microprocessor will
complete the executing instruction, and start a
RESTART sequence
...
The RESTART sequence resets the interrupt flip
flop and activates the interrupt acknowledge signal
(INTA)
...
Upon receiving the INTA signal, the interrupting
device is expected to return the op-code of one of
the 8 RST instructions
...
When the microprocessor executes the RST
instruction received from the device, it saves the
address of the next instruction on the stack and
jumps to the appropriate entry in the IVT
...
The IVT entry must redirect the microprocessor to
the actual service routine
...
The service routine must include the instruction EI
to re-enable the interrupt process
...
At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted
...

– each of these would send the
execution to a predetermined
hard-wired memory location:

CALL
0000H

RST1

CALL
0008H

RST2

CALL
0010H

RST3

CALL
0018H

RST4

CALL
0020H

RST5

CALL
0028H

RST6

CALL
0030H

RST7

CALL
0038H

Restart Sequence
• The restart sequence is made up of three machine
cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal
...


– In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is saved on the stack
...


Restart Sequence
• The location in the IVT associated with the
RST instruction can not hold the complete
service routine
...

– Only a JUMP instruction to the ISR’s location
is kept in the IVT block
...

– So, the device needs to set the bits of the data
bus to the appropriate value in response to an
INTA signal
...

– This signal will enable the Tri-state buffers, which will
place the value EFH on the data bus
...


• The RST 5 instruction is exactly equivalent to
CALL 0028H

Issues in Implementing INTR
Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock
cycle before the last T-state of each instruction
...

– The INTR must remain active long enough to allow for
the longest instruction
...


Therefore, the INTR must remain active for 17
...


Issues in Implementing INTR
Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed
...

– The worst case situation is when EI is the first
instruction in the ISR
...


Therefore, INTR should be turned off as soon as the
INTA signal is received
...

– They will only be enabled after the execution of the EI
instruction
...

If the EI instruction is placed early in the ISR, other
interrupt may occur before the ISR is done
...

– Therefore, we must allow the signal from only
one of the devices to reach the microprocessor
...


The Priority Encoder
• The solution is to use a circuit called the priority
encoder (74366)
...

– The inputs are assigned increasing priorities according
to the increasing index of the input
...


– The 3 outputs carry the index of the highest priority
active input
...
4 in the book shoes how this circuit can be
used with a Tri-state buffer to implement an interrupt
priority scheme
...


Multiple Interrupts & Priorities
• Note that the opcodes for the different RST
instructions follow a set pattern
...

• The other bits are always 1
...


• The one draw back to this scheme is that the only
way to change the priority of the devices
connected to the 74366 is to reconnect the
hardware
...
7

Dev
...
5

O7
O6
O5
O4
O3
O2
O1
O0

INTR Circuit
INTA Circuit
RST Circuit

7
4
1
3
8

+5 V

Dev
...
3

Dev
...
1

Dev
...

– RST 5
...
5, RST 7
...

• They are automatically vectored according to the following
table:
Interrupt

Vector

RST 5
...
5

0034H

RST 7
...
That’s why they have names like RST 5
...


Masking RST 5
...
5 and
RST 7
...

• The Interrupt Enable flip flop controls the whole
maskable interrupt process
...

• These flip flops control the interrupts individually
...
5 Memory
RST 7
...
5

RST 6
...
5

RST 5
...
5

INTR
Interrupt
Enable
Flip Flop

The 8085 Maskable/Vectored
Interrupt Process
1
...

2
...

3
...

4
...


The 8085 Maskable/Vectored
Interrupt Process
5
...

6
...

7
...

8
...


Manipulating the Masks
• The Interrupt Enable flip flop is manipulated using
the EI/DI instructions
...
5, RST 6
...
5 are manipulated using the SIM
instruction
...


How SIM Interprets the
Accumulator
6

5 4

3

2

1

0

SDO
SDE
XXX
R7
...
5
M6
...
5

7

Serial Data Out

Enable Serial Data
0 - Ignore bit 7
1 - Send bit 7 to SOD pin

Not Used

RST5
...
5 Mask
RST7
...
5 Flip Flop to reset

SIM and the Interrupt Mask
• Bit 0 is the mask for RST 5
...
5 and bit 2 is the mask for RST 7
...

• If the mask bit is 0, the interrupt is available
...


• Bit 3 (Mask Set Enable - MSE) is an enable for
setting the mask
...

• If it is set to 1, the new setting are applied
...

– It is also used to control functionality such as Serial Data
Transmission
...
5 interrupt is the only 8085 interrupt that has
memory
...
5 arrives while it is masked, a flip flop will
remember the signal
...
5 is unmasked, the microprocessor will be interrupted
even if the device has removed the interrupt signal
...
5 interrupt
...
5 memory even if the
microprocessor did not respond to it
...

– One bit at a time can be sent out serially over the SOD
pin
...


• The value to be sent out on SOD has to be placed
in bit 7 of the accumulator
...
5 is enabled, RST6
...
5 is enabled
...
5
- Disable 6
...
5
- Allow setting the masks
- Don’t reset the flip flop
- Bit 5 is not used
- Don’t use serial data
- Serial data is ignored
EI
MVI A, 0A
SIM

bit 0 = 0
bit 1 = 1
bit 2 = 0
bit 3 = 1
bit 4 = 0
bit 5 = 0
bit 6 = 0
bit 7 = 0

SDO
SDE
XXX
R7
...
5
M6
...
5

– First, determine the contents of the accumulator
0 0 0 0 1 0 1 0
Contents of accumulator are: 0AH

; Enable interrupts including INTR
; Prepare the mask to enable RST 7
...
5, disable 6
...
5 is positive edge sensitive
...
5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt
...

• The line must go to zero and back to one before a new interrupt
is recognized
...
5 and RST 5
...

• The interrupting signal must remain present until the
microprocessor checks for interrupts
...

RST7
...
5
M 7
...
5
P6
...
5
IE
M7
...
5
M5
...
5
M 6
...
5
M 5
...
5
P6
...
5
IE
M7
...
5
M5
...
5 Interrupt Pending
RST6
...
5 Interrupt Pending

RST5
...
5 Mask
RST7
...
5, RST 6
...
5
• They return the contents of the three mask flip flops
...


• Bit 3 shows whether the maskable interrupt
process is enabled or not
...

• It can be used by a program to determine whether or not
interrupts are enabled
...
5, RST 6
...
5
• Bits 4 and 5 return the current value of the RST5
...
5
pins
...
5 memory flip flop
...

• The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit
...

– Using the RIM instruction, the programmer can read
the status of the interrupt lines and find if there are any
pending interrupts
...
5, RST 6
...
5 without having to
enable low level interrupts like INTR
...
5 without
modifying the masks for RST5
...
5
...
5
and RST7
...

– Then we can use the SIM instruction to set the masks
using this information
...


Using RIM and SIM to set
Individual Masks

SDI
P7
...
5
P5
...
5
M6
...
5

– Assume the RST5
...
5 are enabled and the interrupt process
is disabled
...


ORI 08H

;00001000
; Set bit 4 for MSE
...
5 flip flop, and set the mask
; for RST6
...
Don’t cares are
; assumed to be 0
...


SDO
SDE
XXX
R7
...
5
M6
...
5

0 0 0 0 1 0 0 0

TRAP
• TRAP is the only non-maskable interrupt
...


• It has the highest priority amongst interrupts
...

– It needs to be high and stay high to be recognized
...


• TRAP is usually used for power failure and
emergency shutoff
...

– The interrupts are ordered as follows:
•
•
•
•
•

TRAP
RST 7
...
5
RST 5
...


The 8085 Interrupts
Interrupt
Name

Maskable

Masking
Method

Vectored

Memory

Triggerin
g Method

INTR

Yes

DI / EI

No

No

Level
Sensitive

Yes

DI / EI
SIM

Yes

No

Level
Sensitive

Yes

DI / EI
SIM

Yes

Yes

Edge
Sensitive

No

Level &
Edge
Sensitive

RST 5
...
5
RST 7
...

• It can vector an interrupt anywhere in memory
without additional H/W
...

• The priority scheme can be extended to 64 levels
using a hierarchy 0f 8259 device
...

– It requires additional hardware to produce the RST
instruction opcodes
...


• Therefore, we need a device like the 8259A to
expand the priority scheme and allow mapping to
pages other than 00H
...
7

Dev
...
4

I7

INTA

I6

Dev
...
3

I3
I2
I1

Dev
...
1

Dev
...

After that, the following sequence occurs:
1
...

2
...
The 8259A sends an INTR signal to the
microprocessor
...
The microprocessor responds with an INTA signal
and turns off the interrupt enable flip flop
...
The 8259A responds by placing the op-code for the
CALL instruction (CDH) on the data bus
...
When the microprocessor receives the op-code for
CALL instead of RST, it recognizes that the device
will be sending 16 more bits for the address
...
The microprocessor sends a second INTA signal
...
The 8259A sends the high order byte of the ISR’s
address
...
The microprocessor sends a third INTA signal
...
The 8259A sends the low order byte of the ISR’s
address
...
The microprocessor executes the CALL instruction
and jumps to the ISR
...

– This process employs the HOLD pin on the
microprocessor
• The external DMA controller sends a signal on the HOLD pin
to the microprocessor
...

• Once the DMA controller is done, it turns off the HOLD signal
and the microprocessor takes back control of the buses
...

• Memory-mapped
...


– Enable the device using the Read and Write control
signals
...

• Write for an output device
...


Basic Concepts in Serial I/O
• Controlling the transfer of data:
– Microprocessor control
...


– Device control
...


Synchronous Data Transmission
• The transmitter and receiver are synchronized
...


• Usually used for high speed transmission
...


• Message based
...


Asynchronous Data Transmission
• Transmission occurs at any time
...

– Each character is sent separately
...

– Less the 20 K bits/sec
...

• Logic 0 is known as space
...

– Then the seven or eight bits representing the
character are transmitted
...

D0 D1 D2 D3 D4 D5 D6 D7
One Character

Time

Stop

Simplex and Duplex
Transmission
• Simplex
...

– Only one wire is needed to connect the two devices
– Like communication from computer to a printer
...

– Two-way transmission but one way at a time
...


• Full-Duplex
...

– Two wires are needed
...


Rate of Transmission
• For parallel transmission, all of the bits are sent at
once
...

– Therefore, there needs to be agreement on how “long”
each bit stays on the line
...


Length of Each Bit
• Given a certain baud rate, how long should
each bit last?
– Baud = bits / second
...

– At 1200 baud, a bit lasts 1/1200 = 0
...


Transmitting a Character
• To send the character A over a serial
communication line at a baud rate of 56
...

– Must add a start bit and two stop bits:
• 11 01000001 0

– Each bit should last 1/56
...
66 µ Sec
...


– Set up a delay loop for 17
...


Error Checking
• Various types of errors may occur during
transmission
...


• Error checking techniques:
– Parity Checking
...


• These techniques are for error checking not
correction
...

– They do not indicate where or what the correct
information is
...

– Given that ASCII is a 7-bit code, bit D7 is used to carry
the parity information
...
If there
is an odd number of 1’s, bit D7 is set to 1 to make the total
number of 1’s even
...

– If it doesn’t match, there was an error in the transmission
...

• The transmitter adds all of the bytes in the
message without carries
...

• The receiver adds all of the bytes in the message
including the last byte
...

– If it isn’t an error has occurred
...

–
–
–
–
–

The most common communication standard
...

It uses voltages between +15 and –15 V
...

Restricted to distances of less than 50 feet (15 m)
...

– However, in reality only three of these wires are
needed
...

– Transmit a start bit for one complete bit length
...

– Calculate parity and transmit it if needed
...

– Transmission line returns to logic 1
...

• Start bit

– Read the value of the line over the next 8 bit lengths
...


– Calculate parity and compare it to bit 8 of the character
...


– Verify the reception of the appropriate number of stop
bits
...


SIM and Serial Output
• As was discussed in Chapter 12, the SIM
instruction has dual use
...


• The figure below shows how SIM uses the
accumulator for Serial Output
...
5
MSE
M7
...
5
M5
...
5
P6
...
5
IE
M7
...
5
M5
...

– The two pins themselves can be considered as
the ports
...


Example
• Transmit an ASCII character stored in
register B using the SOD line
...

Determine addresses of Ports B,C and control register
...

Connect DIP switches connected to the to input ports and
LEDs to the output ports
...
Read switch positions of port CL and
display the reading at port CU

BSR (Bit Set/Reset ) Mode
BSR control word
D7
0

D6
X

D5
X

D4
X

D3

D2
BIT SELECT

D1

D0
S/R

000 = Bit 0
001 = Bit 1

Not used,
Generally reset to 0
1

1= Set

010 = Bit 2

BSR Mode

0 = Reset

011 = Bit 3
100 = Bit 4
101 = Bit 5
110 = Bit 6
111 = Bit 7

Problem 2)


1

Write an ALP to set bits PC7 and PC 3
and reset them after 10 ms in BSR
mode
...

Assuming that an A-to-d converter is
connected with port A as an interrupt I/O
and a printer is connected with port B as a
status check I/O

8086 MICROPROCESSOR

Pinouts

I-46

8086 Pins
The 8086 comes in a 40 pin package which means that some pins have
more than one use or are multiplexed
...

In particular, the address lines 0 - 15 are multiplexed with data lines 0-15,
address lines 16-19 are multiplexed with status lines
...

BHE stands for Byte High Enable
...

The 8086 has two modes of operation that changes the function of some pins
...
This is a simple single processor mode
...
This is the mode
required for a coprocessor like the 8087
...

In the minimum mode
HOLD

When this pin is high, another master is requesting control of the
local bus, e
...
, a DMA controller
...


WR’

Write: the processor is performing a write memory or I/O operation
...


DT/R’

Data Transmit or Receive
...


ALE

Address Latch Enable: the address is on the address/data pins
...


INTA’

Interrupt acknowledge: acknowledges external interrupt requests
...

The following are
VCC

+ 5 volt power supply pin
...


READY Acknowledgement from wait-state logic that the data transfer will
be completed
...
Must be high
for 4 clocks
...

TEST’

The WAIT instruction waits for this pin to go low
...


NMI

Non Maskable Interrupt: transition from low to high causes an
interrupt
...


INTR

Interrupt request: masked by the IF bit in FLAG register
...
e
...

I-49

8086 Features
• 16-bit Arithmetic Logic Unit
• 16-bit data bus (8088 has 8-bit data bus)
• 20-bit address bus - 220 = 1,048,576 = 1 meg
The address refers to a byte in memory
...
In the 8086, bytes at even addresses come in on the low
half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper
half of the data bus (bits 8-15)
...
The 8088 needs two operations in either case
...


I-8

8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU)
...

• The EU decodes and executes the instructions using the 16-bit ALU
...
Data is fetched using a segment register (usually the DS)
and an effective address (EA) computed by the EU depending on the
addressing mode
...

The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a
High byte and a Low byte
...
8085 source
code could be translated in 8086 code and assembled
...
It also contains information which controls the
operation of the microprocessor
...


CODE
STACK

64K Data
Segment

DATA
EXTRA

Segment
Registers

64K Code
Segment

Segments are < or = 64K,
can overlap, start at an address
that ends in 0H
...

Note that the Code segment is < 64K since 0FFFFFH is the highest address
...

The offset is given by the IP for the Code Segment
...

The physical address is also called the absolute address
...

The stack is always referenced with respect to the stack segment register
...

The SP points to the last or top item on the stack
...

The effective address (EA) is the offset
...


I-18

8086 memory Organization

Even addresses are on the low half
of the data bus (D0-D7)
...

A0 = 0 when data is on the low
half of the data bus
...


MAX and MIN Modes
• In minmode, the 9 signals correspond to
control signals that are needed to operate
memory and I/O devices connected to the
8088
...


Why MIN and MAX modes?
• Minmode signals can be directly decoded
by memory and I/O circuits, resulting in a
system with minimal hardware
requirements
...
g
...


The 9 pins (min)
•
•
•
•
•
•
•
•
•

**ALE: address latch enable (AD0 – AD7)
**DEN: data enable (connect/disc
...
bus
*QS1, QS0: queue status (tracking of
internal instruction queue)
...
g
...
g
...
It always follows the rule of
last-in-firs-out
— Generally, SS and SP are used to trace where is the latest date written into stack

 PUSH Source
— Push data (word) onto stack
— It does not modify flags
— For Example: PUSH AX (assume ax=1234H, SS=1000H, SP=2000H
before PUSH AX)
1000:1FFD

??

1000:1FFE

34

??

1000:1FFF

12

??

1000:2000

??

1000:1FFD
1000:1FFE

??

1000:1FFF
SS:SP

??

1000:2000

SS:SP

Before PUSH AX, SP = 2000H

After PUSH AX, SP = 1FFEH

12

34
AX

 Decrementing the stack pointer during a push is a standard way of implementing stacks in hardware

Instructions for Stack Operations
 PUSHF
— Push the values of the flag register onto stack
— It does not modify flags

 POP Destination
— Pop word off stack
— It does not modify flags
— For example: POP AX
1000:1FFD

1000:1FFD

??

1000:1FFE

34

1000:1FFE

34

1000:1FFF

12

1000:1FFF

12

1000:2000

SP

??

EC

1000:2000

EC

Before POP, SP = 1FFEH

SP

After POP AX, SP = 2000H

 POPF
— Pop word from the stack to the flag register
— It modifies all flags

12

34
AX

Data Transfer Instructions
 SAHF
— Store data in AH to the low 8 bits of the flag register
— It modifies flags: AF, CF, PF, SF, ZF

 LAHF
— Copies bits 0-7 of the flags register into AH
— It does not modify flags

 LDS Destination Source
— Load 4-byte data (pointer) in memory to two 16-bit registers
— Source operand gives the memory location
— The first two bytes are copied to the register specified in the destination operand;
the second two bytes are copied to register DS
— It does not modify flags

 LES Destination Source
— It is identical to LDS except that the second two bytes are copied to ES
— It does not modify flags

Data Transfer Instructions
 LEA Destination Source
— Transfers the offset address of source (must be a memory location) to the
destination register
— It does not modify flags

 XCHG Destination Source
— It exchanges the content of destination and source
— One operand must be a microprocessor register, the other one can be a register
or a memory location
— It does not modify flags

 XLAT
— Replace the data in AL with a data in a user defined look-up table
— BX stores the beginning address of the table
— At the beginning of the execution, the number in AL is used as the
index of the look-up table
— It does not modify flags

String Instructions
 String is a collection of bytes, words, or long-words that can be up to 64KB
in length
 String instructions can have at most two operands
...

— For Example:

MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor will execute MOVSB 5 times
...
e
...

The displacement is the number that, when added to the IP, changes the
IP to point at the jump target
...

The loop instructions perform several operations at one time but do not
change any flags
...

LOOPNZ or LOOPNE -- loop while not zero or not equal: decrements CX
and jumps if CX is not zero or the zero flag ZF = 0
...

The conditional jump instructions often follow a compare CMP or TEST
instruction
...
CMP does a SUBtract (dest - src) and TEST does an AND
...

Test is used to see if a bit or bits are set in a word or byte such as when
determining the status of a peripheral device
...


Select counter 0

Select counter 1

Select Counter 2

Read-Back command

BCD:
0

Binary Counter 16-bits

1

Binary Coded Decimal (BCD) Counter

M2

M1

M0

0

0

0

Mode 0

0

0

1

Mode 1

X

1

0

Mode 2

X

1

1

Mode 3

1

0

0

Mode 4

1

0

1

Mode 5

MODE 0 : Interrupt on terminal count

Clk
WR
Output
Interrupt

3

2

1

0

MODE 1 : HARDWARE-RETRIGGERABLE
ONE-SHOT
Clk
WR
Output

3

2

1

0

MODE 2 : RATE GENERATOR CLOCK
Clk
WR
OUTPUT

3

2

1

0

3

MODE 3 : Square Wave Generator
Clk
OUTPUT(n=4) 4

2

4

2

OUTPUT(n=5) 5

4

2

5

4

2

4

2
5

4

2
2

MODE 4 : SOFTWARE TRIGGERED STROBE
In this mode OUT is initially high; it goes low for one
clock period at the end of the count
...


MODE 5 : HARWARE TRIGGERED STROBE

• This mode is similar to MODE 4 except that
it is triggered by the rising pulse at the gate
...
At the end of the count the
OUT goes low for one clock period
...

1

1

COU
NT

STAT CNT2 CNT1 CNT0
US

0

Data Transfer
Schemes

Why do we need data transfer
schemes ?
• Availability of wide variety of I/O devices
because of variations in manufacturing
technologies e
...
electromechanical, electrical,
mechanical, electronic etc
...

• Wide variation in the format of data
...

• These programs are executed by the CPU
when an I/O device is ready to transfer data
...

• This scheme is very slow and thus suitable
when small amount of data is to be transferred
...

• In this case the status of the I/O device is not
checked before data transfer
...


• Memory compatible with MPU are available
...

• The I/O devices compatible in speed with
MPU are usually not available
...

• This scheme is used when speed of I/O device
does not match with that of MPU and the
timing characteristics are not predictable
...


• The data transfer instructions are executed
only when the I/O device is ready to accept or
supply data
...


Disadvantages
• A lot of MPU time is wasted during looping to
check the device status which may be
prohibitive in many situations
...
In such a case MPU goes on checking
whether data is available on the port or not
...

• When the device gets ready, it sends a signal
to the MPU through a special input line called
an interrupt line
...


• The MPU saves the contents of the PC on the
stack first and then takes up a subroutine called
ISS (Interrupt Service Subroutine)
...

• It is efficient because precious time of MPU is
not wasted while the I/O device gets ready
...


Multiple Interrupts
• The MPU has one interrupt level and several
I/O devices to be connected to it which are
attended in the order of priority
...


• The MPU has several interrupt levels and
more than one I/O devices are to be
connected to each interrupt level
...
5
RST6
...
5
INTR

These interrupts are implemented by the
hardware

Interrupt Instructions
• EI ( Enable Interrupt) This instruction sets the
interrupt enable Flip Flop to activate the interrupts
...
e
...


This also resets the interrupt enable Flip

• SIM (Set Interrupt Mask) This enables\disables
interrupts according to the bit pattern in
accumulator obtained through masking
...


Call Locations and Hex – codes
for RST n
RST n
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7

Hex - code
C7
CF
D7
DF
E7
EF
F7
FF

Call location
0000
0008
0010
0018
0020
0028
0030
0038

These instructions are implemented by the software

DMA Data Transfer scheme
• Data transfer from I/O device to memory or
vice-versa is controlled by a DMA controller
...

• The DMA requests the control of buses
through the HOLD signal and the MPU
acknowledges the request through HLDA
signal and releases the control of buses to
DMA
...


Block mode of data transfer
In this scheme the I/O device withdraws
the DMA request only after all the data
bytes have been transferred
...




---