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1
DIFFERENCES WITH COMBINATIONAL CIRCUIT
Introduction
Inputs
...
Combinational
Logic Gates
...
Outputs
Memory Elements
(Flip-Flops)
Clock
2
DIFFERENCES WITH COMBINATIONAL CIRCUIT
Sequential logic can have one or more, inputs and one or
more outputs
...
Sequential logic requires memory to store these
previous outputs values
...
Examples: Flipflops, Latch, Counters, Shift Registers etc
3
CLOCK AND FREQUENCY
A signal used to synchronize the operations of an
electronic system
...
In electronics and especially synchronous digital circuits,
a clock signal is a particular type of signal that oscillates
between a high and a low state and is utilized to
coordinate actions of circuits
...
A clock signal is produced by a clock generator
...
Clock speed refers to the number of pulses per second
generated by an oscillator that sets the tempo for the
processor
...
Clock speed is usually measured in MHz megahertz, or
millions of pulses per second or GHz gigahertz, or billions
of pulses per second
...
Clock period
5
MORE ABOUT CLOCKS
Clocks are used extensively in computer architecture
...
Modern chips run at frequencies up to 3
...
This works out to a cycle time as little as 0
...
Be careful
...
6
CLOCK AND FREQUENCY
Positive Edge Transition
1
0
1
0
Negative Edge Transition
7
LATCH
The primary difference between a flip-flop and latch
is the EN/CLOCK input
...
8
LATCH: OTHER DIFFERENCES
It’s difficult to control the timing of latches in a large
circuit
...
Flip-flops allow us to quickly write the memory at clearly
defined times
...
9
FLIP-FLOPS
Introduction
Flip-Flop: Bi-stable memory device with edgetriggering (with clock) meaning the flip-flop’s
output changes on the edge (rising or falling)
of the CLOCK input, samples its inputs, and
changes its output only at times determined by
a clocking signal
...
The latch is transparent
...
Race condition occurs when the flip-flop is unstable
...
The latch is transparent
...
15
JK FLIP-FLOP: EXCITATION TABLE AND TIMING DIAGRAM
J
Q
CLK
K
SET
TOGGLE
Q
TOGGLE
CLEAR
Qp
Qn
J
K
0
0
0
X
0
1
1
X
1
0
X
1
1
1
X
0
NO
CHANGE
SET
NO
CHANGE
Q
J
K
CLK
16
D FLIP-FLOP
Single input flip flop
Also known as a data or delay flip-flop
Can be viewed as a memory cell
They form the basis for shift registers, which are an essential part of many
electronic devices
Constructed from a pair of cross-coupled NOR logic gates OR NAND Logic gates
With Clock high, the signals can pass through the input gates to the
encapsulated latch
...
With Clock low, the latch is closed (opaque) and remains in the state it was left
the last time Clock was high
Modification of SR Flip-flop that removes race around condition
17
D FLIP-FLOP: CHARARCTERISTIC TABLE AND EQUATION
D
CLK
Q
Q
0
0
1
1
1
0
: Rising Edge of Clock
Qn=D
clock
D
Qp
Qn
O
X
X
No
change
1
O
O
O
1
O
1
O
1
1
O
1
1
1
1
1
18
D FLIP-FLOP: EXCITATION TABLE AND TIMING DIAGRAM
D
Q
CLK Q
Q=D=1
Q=D=0
Q=D=0
No Change
Q=D=1
Qp
Qn
D
0
0
0
0
1
1
1
0
0
1
1
1
Q=D=1
No Change
Q=D=0
Q=D=0
No Change
Q
D
CLK
19
T FLIP-FLOP
Single input flip flop
Also known as a Toggle or Triggered flip-flop
They form the basis for counters
Constructed from a pair of cross-coupled NOR logic gates OR NAND Logic gates
With Clock high, the signals can pass through the input gates to the
encapsulated latch
...
With Clock low, the latch is closed (opaque) and remains in the state it was left
the last time Clock was high
Modification of JK Flip-flop
20
T FLIP-FLOP: CHARARCTERISTIC TABLE AND EQUATION
T
CLK
Q
Q
0
1
0
1
0
1
clock
T
Qp
Qn
O
X
X
No
change
1
O
O
O
1
O
1
1
1
1
O
1
1
1
1
O
: Rising Edge of Clock
Qn=TQ’p+T’Qp
Qn=T XOR Qp
21
T FLIP-FLOP: EXCITATION TABLE AND TIMING DIAGRAM
T
Q
CLK Q
Qp
Qn
T
0
0
0
0
1
1
1
0
1
1
1
0
T=1 and
clock is in
positive edge
22
Master Slave Flip-Flop
Figure alongside shows
Master Slave JK Flipflop
and Master Slave D
Flipflop
Also known as Pulse
Triggering flipflop
The circuit accepts
input data when the
clock signal is "HIGH",
and passes the data to
the output on the
falling-edge of the
clock signal
...
Basically two gated D flip-flops connected together in a series configuration with the
slave having an inverted clock pulse
...
The Preset (PR) input forces the output to:
Q 1 & Q 0
PR
D
Q
The Clear (CLR) input forces the output to:
Q 0 & Q 1
The table below is for an
active low consideration
PR
CLR
CLK
D
PRESET
CLEAR
CLOCK
DATA
1
1
1
1
0
CLK
Q
CLR
Q
Q
0
0
1
1
1
0
1
X
X
1
0
Asynchronous Preset
1
0
X
X
0
1
Asynchronous Clear
0
0
X
X
1
1
ILLEGAL CONDITION
24
ASYNCHRONOUS INPUTS OF A FLIP-FLOP
Flip-flops are subject to a problem called metastability, which can happen when
two inputs, such as data and clock or clock and reset, are changing at about the
same time
...
In a computer system, this metastability can cause corruption of data or a program
crash, if the state is not stable before another circuit uses its value; in particular, if
two different logical paths use the output of a flip-flop, one path can interpret it as
a 0 and the other as a 1 when it has not resolved to stable state, putting the
25
machine into an inconsistent state
D FLIP-FLOP: PR & CLR TIMING (Active low consideration)
Q=D=1
Q=D=0
Clocked
Clocked
Q=D=0
Q=D=1
Q=D=1
Q=D=0
Clocked
Clocked
Clocked
Clocked
Q
PR
Q=1
Q=1
Preset
Preset
Q=0
Clear
CLR
D
CLK
26
PARAMETERS OF A FLIP-FLOP (Operating Characteristics)
Data Input
(D,J, or K)
Positive
Edge
Clock
1
0
tS
tH
Setup Time
Hold Time
1
0
Setup Time (tS): The time interval before the active transition of the clock signal
during which the data input (D, J, or K) must be maintained
...
27
PARAMETERS OF A FLIP-FLOP (Operating Characteristics)
PROPAGATION TIME: It is defined as the time after the clock transition,
required for a flip-flop to generate output
...
28
OTHER FLIP-FLOPS FROM D FLIP-FLOP
D to T Flip-Flop
D to JK Flip-Flop
D to SR Flip-Flop
29
OTHER FLIP-FLOPS FROM SR FLIP-FLOP
SR to D Flip-Flop
SR to T Flip-Flop
SR to JK Flip-Flop
30
OTHER FLIP-FLOPS FROM JK FLIP-FLOP
JK to D Flip-Flop
JK to T Flip-Flop
31
OTHER FLIP-FLOPS FROM JK FLIP-FLOP
JK to SR Flip-Flop
Qp Qn
Required is SR(Characteristic Table)
J
K
0
0
0
X
S
R
Qp
Qn
0
1
1
X
0
0
0
0
1
0
X
1
0
0
1
1
1
1
X
0
0
1
0
0
1
1
Given is JK (Excitation Table)
S
R
Qp
Qn
J
K
0
0
0
0
0
0
X
1
0
0
0
1
1
X
0
0
0
1
0
1
0
0
0
X
1
0
1
1
0
1
1
0
X
1
1
1
0
RACE
1
0
0
1
1
X
1
1
1
RACE
1
0
1
1
X
0
1
1
0
RACE
X
X
1
1
1
RACE
X
X
Diagram is in next slide
32
OTHER FLIP-FLOPS FROM JK FLIP-FLOP
JK to SR Flip-Flop
J=S
K=R
33
OTHER FLIP-FLOPS FROM T FLIP-FLOP
T to D Flip-Flop
Required is D (Characteristic Table)
D
Qp
Qn
T
0
0
0
O
D
Qp
Qn
0
1
0
1
0
0
0
1
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
Given is T (Excitation Table)
Qp
Qn
T
0
0
0
0
1
1
1
0
1
1
1
0
T = D XOR Qp
34
OTHER FLIP-FLOPS FROM T FLIP-FLOP
T to JK Flip-Flop
Required is JK(Characteristic Table)
Qp
Qn
T
0
0
0
0
1
1
1
0
1
1
1
0
Given is T (Excitation Table)
J
K
Qp
Qn
0
0
0
0
0
0
1
1
0
1
0
0
J
K
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
Diagram is in next slide
T=JQ’p+KQp
Qp Qn
T
35
OTHER FLIP-FLOPS FROM T FLIP-FLOP
T to JK Flip-Flop
T=JQ’p+KQp
36
OTHER FLIP-FLOPS FROM T FLIP-FLOP
T to SR Flip-Flop
Required is SR(Characteristic Table)
Qp
Qn
T
0
0
0
0
1
1
1
0
1
1
1
0
Given is T (Excitation Table)
S
R
Qp
Qn
0
0
0
0
0
0
1
1
0
1
0
0
S
R
Qp
Qn
T
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
1
1
0
1
0
0
0
1
1
0
RACE
0
1
1
0
1
1
1
1
RACE
1
0
0
1
1
1
0
1
1
0
1
1
0
RACE
X
1
1
1
RACE
X
Diagram is in next slide
T=SQ’p+RQp
37
OTHER FLIP-FLOPS FROM T FLIP-FLOP
T to SR Flip-Flop
T=SQ’p+RQp
38
BASIC FLIP-FLOP APPLICATIONS
1
...
Counting
Asynchronous down counting from 15 to 0
40
BASIC FLIP-FLOP APPLICATIONS
3
...
Frequency
Division
1 Flip-flop- Divide the clock frequency by 2
2 Flip-flop- Divide the clock frequency by 4
3 Flip-flop- Divide the clock frequency by 8
4 Flip-flop- Divide the clock frequency by 16
5 Flip-flop- Divide the clock frequency by 32
6 Flip-flop- Divide the clock frequency by 64
7 Flip-flop- Divide the clock frequency by 128
n Flip-flop- Divide the clock frequency by 2n
42