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UNIT-1 Fundamentals of Low Power VLSI Design
Need for Low Power Circuit Design:
The increasing prominence of portable systems and the need to limit power consumption
(and hence, heat dissipation) in very-high density ULSI chips have led to rapid and innovative
developments in low-power design during the recent years
...
In most of these cases, the requirements of low power consumption must be met along
with equally demanding goals of high chip density and high throughput
...

The limited battery lifetime typically imposes very strict demands on the overall power
consumption of the portable system
...
The energy density (amount of energy stored per unit weight)
offered by the new battery technologies (e
...
, NiMH) is about 30 Watt-hour/pound, which is still
low in view of the expanding applications of portable systems
...

The need for low-power design is also becoming a major issue in high-performance
digital systems, such as microprocessors, digital signal processors (DSPs) and other applications
...
If the clock frequency of the chip increases then the power dissipation of
the chip, and thus, the temperature, increase linearly
...
Several high-performance microprocessor chips
designed in the early 1990s (e
...
, Intel Pentium, DEC Alpha, PowerPC) operate at clock
frequencies in the range of 100 to 300 MHz, and their typical power consumption is between 20
and 50 W
...

There is a close correlation between the peak power dissipation of digital circuits and reliability
problems such as electro migration and hot-carrier induced device degradation
...
Consequently, the
reduction of power consumption is also crucial for reliability enhancement
...
Device characteristics (e
...
,
threshold voltage), device geometries and interconnect properties are significant factors in
lowering the power consumption
...
Architecture-level measures include smart power management
of various system blocks, utilization of pipelining and parallelism, and design of bus structures
...


Sources of Power Dissipation
The average power dissipation in conventional CMOS digital circuits can be classified
into three main components, namely,
(1) The dynamic (switching) power dissipation
(2) The short-circuit power dissipation and
(3) The leakage power dissipation
...

This means that the output node voltage of a CMOS logic gate makes a power consuming
transition
...
During the charge-up phase, the output
node voltage typically makes a full transition from 0 to VDD, and the energy used for the
transition is relatively independent of the function performed by the circuit
...
below
...

The total capacitive load at the output of the NOR gate consists of
(1) The output capacitance of the gate itself
(2) The total interconnect capacitance, and
(3) The input capacitances of the driven gates
...
The important
feature to highlight here is that the amount of capacitance is approximately a linear function of
the junction area
...


Total interconnect capacitance:
The interconnect lines between the gates contribute to the total interconnect capacitance
...

Input capacitances:
The input capacitances are mainly due to gate oxide capacitances of the transistors
connected to the input terminal
...

Generic representation of a CMOS logic gate

Any CMOS logic gate making an output voltage transition can thus be represented by its nMOS
network, pMOS network, and the total load capacitance connected to its output node, as seen in
above Fig
...


……
...

……
...
Hence, given an input pattern, the switching delay
times have no relevance to the amount of power consumption during the switching events as
long as the output voltage swing is between 0 and VDD
...

Another way to limit the dynamic power dissipation of a CMOS logic gate is to reduce
the amount of switched capacitance at the output
...
This can be seen by examining
the following propagation delay expressions for the CMOS inverter circuit
...
(4)
Assuming that the power supply voltage is being scaled down while all other variables
are kept constant, it can be seen that the propagation delay time will increase
...
8 V and VT,p = - 0
...
The normalized variation of the average switching power dissipation as a function
of the supply voltage is also shown on the same plot
...
Equation (3)
suggests a quadratic improvement (reduction) of power consumption as the power supply voltage
is reduced
...
e
...
If the circuit is always operated at the
maximum frequency allowed by its propagation delay, on the other hand, the number of
switching events per unit time (i
...
, the operating frequency) will obviously drop as the
propagation delay becomes larger with the reduction of the power supply voltage
...


The analysis of switching power dissipation presented above is based on the
assumption that the output node of a CMOS gate faces one power-consuming transition (0to-VDD transition) in each clock cycle
...

To better represent this behavior, we will introduce T (node transition factor), which is
the effective number of power-consuming voltage transitions experienced per clock cycle
...
Since there is a parasitic node capacitance
associated with each internal node, these internal transitions contribute to the overall power
dissipation of the circuit
...


In the most general case, the internal node voltage transitions can also be partial transitions, i
...
,
the node voltage swing may be only Vi which is smaller than the full voltage swing of VDD
...


(2)Short-Circuit Power Dissipation:
The switching power dissipation discussed above is purely due to the energy required to charge
up the parasitic capacitances in the circuit, and the switching power is independent of the rise
and fall times of the input signals
...


Short-circuit current component is the current component which passes through both the
nMOS and the pMOS devices during switching
...

This component is particularly powerful if the output load capacitance is small, and/or if
the input signals rise and fall times are large, as shown in below Fig
...
The nMOS transistor in
the circuit starts conducting when the rising input voltage exceeds the threshold voltage VT,n
...

Thus, there is a time window during which both transistors are turned on
...
The
drain-to-source voltage drop of the pMOS transistor becomes nonzero, which allows the pMOS
transistor to conduct as well
...
A similar event is responsible for
the short- circuit current component during the falling input transition, when the output voltage
starts rising while both transistors are on
...
The pMOS transistor also conducts
the current which is needed to charge up the small output load capacitance, but only during the
falling-input transition (the output capacitance is discharged through the nMOS device during the
rising-input transition)
...
The average of both of these current components determines the total amount of power
drawn from the supply
...
If the inverter is driven with an input
voltage waveform with equal rise and fall times (t = trise = tfall), it can be derived that the timeaveraged short circuit current drawn from the power supply is

Hence, the short-circuit power dissipation becomes

Note that the short-circuit power dissipation is linearly proportional to the input signal rise and
fall times, and also to the transconductance of the transistors
...


Now consider the same CMOS inverter with a larger output load capacitance and smaller
input transition times
...

Although both the nMOS and the pMOS transistors are on simultaneously during the
transition, the pMOS transistor cannot conduct a significant amount of current since the voltage
drop between its source and drain terminals is approximately equal to zero
...
Again, both transistors will be on
simultaneously during the input voltage transition, but the nMOS transistor will not be able to
conduct a significant amount of current since its drain-to-source voltage is approximately equal
to zero
...

Note that the peak value of the supply current to charge up the output load capacitance is
larger in this case
...


The short-circuit power dissipation can be reduced by making the output voltage transition times
larger and/or by making the input voltage transition times smaller
...

(3)Leakage Power Dissipation
The nMOS and pMOS transistors used in a CMOS logic gate generally have nonzero reverse
leakage and sub threshold currents
...
The magnitude of the leakage currents is
determined mainly by the processing parameters
...
The reverse-biased drain junction then conducts a reverse
saturation current which is eventually drawn from the power supply
...
Although the pMOS transistor is turned off, there will be a reverse potential
difference of VDD between its drain and the n-well, causing a diode leakage through the drain
junction
...
Therefore, another significant leakage current component exists due to
the n-well junction

A similar situation can be observed when the input voltage is equal to zero, and the output
voltage is charged up to VDD through the pMOS transistor
...

The magnitude of the reverse leakage current of a pn-junction is given by the following
expression

Where Vbias is the magnitude of the reverse bias voltage across the junction, J S is the reverse
saturation current density and the A is the junction area
...

Note that the reverse leakage occurs even during the stand-by operation when no switching takes
place
...

Subthreshold leakage current:
Another component of leakage currents which occur in CMOS circuits is the
subthreshold current, which is due to carrier diffusion between the source and the drain region of
the transistor in weak inversion
...
The amount of the subthreshold current may become significant when the gateto source voltage is smaller than, but very close to the threshold voltage of the device
...
The subthreshold leakage current is shown in Fig
...


Note the sub threshold leakage current also occurs when there is no switching activity in the
circuit, and this component must be carefully considered for estimating the total power
dissipation in the stand-by operation mode
...


One relatively simple measure to limit the subthreshold current component is to avoid
very low threshold voltages, so that the VGS of the nMOS transistor remains safely below VT,n
when the input is logic zero, and the |VGS| of the pMOS transistor remains safely below |VT,p|
when the input is logic one
...
One example is the pseudo-nMOS logic circuits which utilize a pMOS
transistor as the pull-up device
...


GLITCH POWER DISSIPATION:
The glitching power dissipation occurs due to finite delay
...

In multi-level logic circuits, the finite propagation delay from one logic block to the next
can cause spurious signal transitions, or glitches as a result of critical races or dynamic hazards
...
But a
dynamic hazard or glitch can occur if input signals change at different times
...
In
some cases, the signal glitches are only partial, i
...
, the node voltage does not make a full
transition between the ground and VDD levels, yet even partial glitches can have a significant
contribution to dynamic power dissipation
...
Such a mismatch in path length results in a mismatch of signal timing with respect to
the primary inputs
...
Assuming that all
XOR blocks have the same delay, it can be seen that the network in Fig
...

In the network shown in Fig
...
Such redesign can significantly reduce the glitching transitions, and
consequently, the dynamic power dissipation in complex multi-level networks
...
(b) Results in smaller overall propagation delay
...


Short-Channel Effects
Short-Channel Devices:
A MOSFET device is considered to be short when the channel length is the same order of
magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction
...

Short-Channel Effects
The short-channel effects are attributed to two physical phenomena:
1
...
The modification of the threshold voltage due to the shortening channel length
...
Drain-induced barrier lowering and punch through
2
...
Velocity saturation
4
...
Hot electron effect
Drain-induced barrier lowering and punch through:
The expressions for the drain and source junction widths are:

And

Where VSB and VDB are source-to-body and drain-to-body voltages
There exists a potential barrier between source and drain which is to be lowered by
applying gate voltage
...
As the source & drain get closer, they become
electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at
the source junction
...
As the drain depletion region
continues to increase with the bias, it can actually interact with the source to channel junction
and hence lowers the potential barrier
...

When the source junction barrier is reduced, electrons are easily injected into the channel
and the gate voltage has no longer any control over the drain current
...
Hence, for such devices, the threshold
voltage is virtually independent of the channel length and drain bias
...


Punchthrough:
When the drain is at high enough voltage with respect to the source, the depletion region
around the drain may extend to the source, causing current to flow irrespective of gate voltage
(i
...
even if gate voltage is zero)
...
So when channel length L decreases (i
...
short
channel length case), punch through voltage rapidly decreases
...
As the channel length is reduced, if the doping is
kept constant, the separation between the depletion region boundaries decreases
...
When the
combination of channel length and reverse bias leads to the merging of the depletion regions,
punchthrough is said to have occurred
...
Since the carrier transport in a MOSFET is confined within
the narrow inversion layer, and the surface scattering (that is the collisions suffered by the
electrons that are accelerated toward the interface by εx) causes reduction of the mobility, the
electrons move with great difficulty parallel to the interface, so that the average surface mobility,
even for small values of εy, is about half as much as that of the bulk mobility
...
At low εy, the electron drift velocity vde in
the channel varies linearly with the electric field intensity
...

Note that the drain current is limited by velocity saturation instead of pinchoff
...
Using vde(sat), the maximum gain possible for a MOSFET can be defined as

Impact ionization
Another undesirable short-channel effect, especially in NMOS, occurs due to the high
velocity of electrons in presence of high longitudinal fields that can generate electron-hole (e-h)
pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them
...
Moreover, the region
between the source and the drain can act like the base of an npn transistor, with the source
playing the role of the emitter and the drain that of the collector
...
6V, the normally reversed-biased substrate-source pn junction will
conduct appreciably
...
They can gain enough energy as they
travel toward the drain to create new electron hole pairs
...


Hot electron effect:
Another problem, related to high electric fields, is caused by so-called hot electrons
...




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