Notesale: Turn your study into money

Document Preview

Extracts from the notes are below, to see the PDF you'll receive please use the links above

---

Phase Locked Loop Circuits

Reading:

General PLL Description: T
...
Lee, Chap
...
Gray and Meyer, 10
...
Razavi, Design of Analog CMOS Integrated
Circuits, Chap
...


1
...
A PLL is a feedback system that includes a VCO, phase detector, and low
pass filter within its loop
...
The PLL is a control system allowing one
oscillator to track with another
...

φout (t ) = φin (t ) + const
...
The former
provides a baseband output that tracks the phase variation at the input
...
Either
phase or frequency can be used as the input or output variables
...
Clock generation
b
...
Clock recovery in a serial data link

UCSB/ECE Department

Prof S
...

2
...
KD is the gain of the phase
detector (V/rad)
...
Recall that the mixer takes the product of two inputs
...
If,
A(t) = A cos(ω0t + φA)
B(t) = B cos(ω0t + φB)
Then, A(t)B(t) = (AB/2)[ cos(2ω0t + φA + φB) + cos(φA - φB)]
Since the two inputs are at the same frequency when the loop is locked, we have one
output at twice the input frequency and an output proportional to the cosine of the phase
difference
...
Any phase difference then shows up as the control voltage to the VCO, a DC or
slowly varying AC signal after filtering
...
Note that
in many implementations, the characteristic may be shifted up in voltage (single
supply/single ended)
...
The slope of the
characteristic in either case is KD
...
VCO
...

Excess phase of the VCO is the system output
...
Long

4/27/05

2

t

φout = K O ∫ Vcont dt '
−∞

The VCO oscillates at an angular frequency, ωout
...
Frequency is assumed to be linearly proportional to the
control voltage with a gain coefficient KO or KVCO (rad/s/v)
...
Let’s define φout – φin = φο
...
Razavi, Ch
...
cit
...

The XOR function produces an output pulse whenever there is a phase misalignment
...
From the upper right figure, we see that
a control voltage V1 will be necessary to produce this output frequency
...
In order to
minimize the required phase offset or error, the PLL loop gain, KD KO, should be
maximized, since

φ0 =

V1 ω1 − ω0
=
K D K D KO

Thus, a high loop gain is beneficial for reducing phase errors
...
PLL dynamic response: To see how the PLL works, suppose that we introduce a
phase step at the input at t = t1
...
Long

4/27/05

3

(Figure from B
...
15, op
...
)
Since we have a step in phase, it is clear that the initial and final frequencies must be
identical: ω1
...

The area under ωout gives the additional phase because Vcont is proportional to
frequency
...
This shows that Vcont(t) [shown as VLPF (t) in the figure above] can be used to
monitor the dynamic phase response of the PLL
...
This in turn causes the control voltage, Vcont, to increase, moving
the VCO frequency up to catch up with the input reference signal
...


UCSB/ECE Department

Prof S
...
Razavi, Ch
...
cit
...


5
...
Range of input signal frequencies over which the loop remains locked
once it has captured the input signal
...

a
...
For the phase detector type
shown (Gilbert multiplier or mixer), the voltage vs
...
Thus the frequency would change in the opposite direction to that required to
maintain the locked condition
...
Long

4/27/05

5

Ve-max = ± KD π/2
When the phase detector output voltage is applied through the loop filter to the VCO,
∆ωout – max = ± KV π/2 = ωL (lock range)
where KV = KO KD, the product of the phase detector and VCO gains
...

Doesn’t depend on the loop filter
Does depend on DC loop gain
b
...
Oscillator
tuning range is limited by capacitance ratios or current ratios and is finite
...

6
...
Sometimes a
frequency detector is added to the phase detector to assist in initial acquisition of lock
...

7
...
But, at this point, we will treat the PLL as a linear feedback system
...
A frequency domain approach will be
used, specifically describing transfer functions in the s-domain
...
Because of this, a PLL is always at least a first
order feedback system
...
Long

4/27/05

6

PLL is a feedback system
IN(s)

Σ

ε(s)

OUT(s)

KFWD(s)

KFB(s)

Loop Gain:

T ( s ) = K FWD ( s ) K FB ( s )

Transfer Function:

(s)
K
OUT ( s )
= H ( s ) = FWD
1 + T (s)
IN ( s)

The Loop gain can be described as a polynomial:

T ( s) =

K ' ( s + a )( s + b)"
s n ( s + α )( s + β ) "

ORDER = the order of the polynomial in the denominator
TYPE = n (the exponent of the s factor in the denominator)
PHASE ERROR =

ε ( s) =

IN ( s)
1 + T (s)

STEADY STATE ERROR =

ε SS = lim [ sε ( s )] = lim ε (t )

s →0
t →∞
(this is the Laplace Transform final value theorem)

SS error is a characteristic of feedback control systems
...
Once again, you can
see that a large loop gain T(s) leads to a small phase error
...
Long

4/27/05

7

Frequency and phase tracking loop:
First we will consider the PLL with feedback = 1; therefore, input and output frequencies
are identical
...


Φ
φ
φinrefr

Loop filter

Phase Detector

+

Σ

F(s)

KD

VCO
KO /s

φφout
vco

–
Transfer Function: H(s) = forward path gain / [1 + T(s)]
...
When the synthesizer frequency is changed, it is a
discontinuous step in modulus, and we want to have zero steady state phase error in this
case
...
Long 4/27/05

8

We will start from the open loop gain, T(s)
...
Let’s start with a simple
RC lowpass network
...
Thus, the filter transfer function
is a simple lowpass,

F (s) =

1

...


UCSB/ECE Department

Prof S
...

ω1
0
∠T(jω)
-90
PM

-180

If the loop filter frequency is lower than the crossover frequency, which you might want
to do to attenuate the high frequency ripple from the phase detector, then the phase
margin can become unacceptably small
...
Thus, we have a
conflict between stability of the loop and minimizing the phase error
...
But, then we may have insufficient filtering of the
phase detector output
...

Root Locus: Since there are no zeros, the root locus represents the roots of the
denominator of the closed loop transfer function
...


s=−

ω1 ⎛⎜

4 KV
1
1
±
−
2 ⎜⎝
ω1

⎞
⎟
⎟
⎠

We see that as KV is increased, the roots approach one another then become complex
conjugates
...
Long 4/27/05

10

ω1
2

1−

4 KV

ω1

ω1

ω1/2

We can have a very underdamped response when ω1 << KV
...


⎛ω
4 KV
e −ω1t / 2 sin ⎜⎜ 1 1 −
ω1
⎝ 2

⎞
⎟t
⎟
⎠

There is an exponentially decaying term determined by the real part of the roots that
shows how long it takes the system to settle after a phase or frequency step and a ringing
frequency dictated by the imaginary part of the pole pair
...

It is sometimes useful to define a natural frequency, ωn, and a damping factor, ζ
...
The key is to put the
denominator of the closed loop transfer function, 1 + T(s), into a “standard” form:
either

s 2 + 2ζω n s + ω n2
or

UCSB/ECE Department

Prof S
...


Taking the first formula, 1 + T(s) can be written as:

s 2 + ω1s + KV ω1
so, we can associate ωn and ζ with:

ω n = KV ω1
ζ =

1 ω1
2 KV

This form allows you to use standard equations and normalized plots to describe the
frequency and transient response of the system
...

For example, the transient response for a Type 1, second order lowpass system such as
this is plotted in the next figure taken from Motorola App
...
It is clear that
damping factors less than 0
...

In the frequency domain, the closed loop transfer function will also exhibit gain peaking
when the system is underdamped
...


UCSB/ECE Department

Prof S
...
You can’t obtain a
narrow loop bandwidth without reducing the phase margin/damping factor
...


UCSB/ECE Department

Prof S
...
From the system design perspective, overshoot can be quite harmful,
since it will cause the frequency to temporarily exceed the steady state value
...
Settling time can also be critical since many TDM applications use different
receive and transmit frequencies
...


Ref
...
Razavi, RF Microelectronics, Prentice-Hall, 1998
...


UCSB/ECE Department

Prof S
...


R1
C

R2

F (s) =

1 + s / ω2
1 + s / ω1

where

ω1 =

1
( R1 + R2 )C

ω2 =

1
R2C

Thus, the zero frequency is always higher than the pole frequency
...


UCSB/ECE Department

Prof S
...

ω1

ω2

0
∠T(jω)
-90
PM
-180
Note that the phase margin has increased
...
Note how phase margin now improves when the crossover
frequency is increased due to higher gain
...


φo
(1 + s ω2 )
= 2
φin
⎛ 1
s
1 ⎞
+ s⎜
+
⎟ +1
KV ω1
⎝ KV ω2 ⎠

The denominator is of the form 1 + T(s)
...


UCSB/ECE Department

Prof S
...


s = − ζωn ± ωn ζ 2 − 1

ω2

ω1

We see that ωn is the same as with the simple RC filter, but the damping factor has an
added term
...
We still have a type 1 system, but we have an
added term that we can use to improve stability, the zero frequency
...
It will
affect the frequency and transient response
...
Long 4/27/05

17

According to Gardner1, the loop bandwidth for this Type 1, second-order loop with a
forward path zero is given by:

[

ω h = ω n 1 + 2ζ 2 + (1 + 2ζ 2 ) + 1

]

1/ 2

According to this, we have a bandwidth of about 2ωn for ζ = 0
...

Refer to Fig
...
3 from Gardner
...
A high gain PLL is defined by KV/ω2 >> 1
...
M
...
, Wiley, 1979
...
Long 4/27/05

18

From this plot, we can see how the 3 dB frequency and gain flatness varies with ζ
...
This is a consequence of the zero added to the transfer function
...

PHASE ERROR
There is no frequency error when the loop is locked
• Input frequency = output frequency
But, it is possible to have a phase error for some input transient phase conditions
...
To analyze in the
frequency domain, we assume a sinusoidal phase variation at the input
...
2
...
707
...
This is because |T(jw)| is large at low frequency
...
Long 4/27/05

19

TRANSIENT PHASE ERROR
• Inverse Laplace transform of ε(s)
Now, let’s look more closely at how the phase error is affected by the type of transient
phase signal at the input of the Type I PLL
...
Phase step
...


ε ss

UCSB/ECE Department

∆θ
s
= lim
=0
s →0
KV ⎛ 1 + s / ω 2 ⎞
⎟
⎜
1+
s ⎜⎝ 1 + s / ω1 ⎟⎠
s

Prof S
...
This is reasonable, because
the control voltage must return to the same value after the phase step is completed
...

2
...


s

∆ω

∆ω
∆ω
s2
= lim
=
s →0
⎛ 1 + s / ω 2 ⎞ KV
K ⎛ 1 + s / ω2 ⎞ s →0
⎟⎟
⎟⎟
s + KV ⎜⎜
1 + V ⎜⎜
+
s ⎝ 1 + s / ω1 ⎠
s
/
1
ω
⎝
1⎠

ε ss = lim

There is a static “error”, but it can be made small by increasing KV
...
The
phase error needed to generate this control voltage step varies inversely with the loop
gain
...
Frequency ramp
...
This gives an unlimited steady state error
...

Summarizing:

Type I; second order:

Input
Phase step
Freq
...
ramp

UCSB/ECE Department

F ( s )=

1 + s / ω2
1 + s / ω1

φin(s)
∆θ/s
∆ω/s2
A/s3

Prof S
...
When the synthesizer frequency is changed, it is a
discontinuous step in modulus, and we want to have zero steady state phase error in this
case
...
To eliminate this phase error, we need a
TYPE = 2 loop gain function
...


Type 2; second order:

Input
Phase step
Freq
...
ramp

F ( s )=

1 + s / ω2
s / ω1

φref(s)
∆θ/s
∆ω/s2
A/s3

εss
0
0
kA

Placing an opamp RC integrator or charge pump in the loop will give a filter transfer
function of the form:

F( s ) =

1 + s / ω2
s / ω1

where providing a pole at s = 0 and a zero at ω2
...


Now find the closed loop transfer function by inserting F(s)
...
Long 4/27/05

22

H( s ) =

φout
K D KO F( s ) / s
=
φin 1 + K D K O F ( s ) / s

H( s ) =

( 1 + s / ω2 )
s2
s
+
+1
K D K O ω1 ω 2

Thus, we can see that

ω n = K D K O ω1
ς=

UCSB/ECE Department

ωn
2ω 2

Prof S
...
Motorola AN535
Here we see the phase and frequency step response for a type 2 PLL in terms of the key
loop parameters
...
For example, if settling to 5% were the criteria and if ζ = 1, the
response first falls within the boundary of 0
...
05 for ωnt = 4
...
Then settling time t
can be determined since natural frequency ωn will also be known
...
Long 4/27/05

24

Root Locus:
Let KV = KOKD

Now, find the poles of 1 + T(s) = 0

s2
KV ω1

+

s

ω2

+ 1=0

s = − ζω n ± ω n ζ 2 − 1

Now examine the root locus
...
The locus follows a circle centered around the zero
...
This happens when KV = 4ω22/ω1
...


Increasing KV

(2)

- ω2

UCSB/ECE Department

Prof S
...
It is
determined by ωn and ζ, so bandwidth must be determined in conjunction with the
overshoot and settling time specifications
...


[

ω h = ω3 dB = ω n 1 + 2ζ 2 + ( 2ζ 2 + 1 )2 + 1
ω3db = 2 ωn
ω3db = 2
...
707
for ζ = 1

Since the loop gain peaking and overshoot is greater when the zero is present, we also
expect bandwidth to be higher as this shows
...


Loop Filter – OpAmp
C
R2

Vin
R1

Vbias

Vout

+

An op amp can be used to form a filter that includes a pole at s = 0 and a finite zero
...


F( s ) =

Vout 1 + s R2 C
=
Vin
s R1C

Vbias can be used to level shift between the phase detector and the VCO
...
Long 4/27/05

26

Synthesizer PLL
We will now add the divider 1/N to the feedback path
...


φosc
Φ
r
1/M

Phase Detector
+

φref

Σ

Loop filter

VCO

F(s)

KO /s

KD

φφoutvco

–

φN

Thus,

1/N

φN
1
=
φout N
ω
and also, N = out
ωref

We can calculate the loop gain, T(s):

T (s) =
•
•
•

K D K O F ( s)
Ns

We see that the loop gain is reduced by a factor of N
...
Long 4/27/05

27

where ω1 = 1/R1C and ω2 = 1/R2C,

1 + T ( s) = 1 +

KV ⎛ 1 + s / ω 2 ⎞
⎜
⎟=0
Ns ⎜⎝ s / ω1 ⎟⎠

Ns 2
s
1 + T ( s) =
+
+1= 0
KV ω1 ω 2
We can now determine how the natural frequency and damping are affected by N:

ωn =
ζ=

UCSB/ECE Department

KV ω1
=
N

ωn
R
= 2
2ω 2
2

KV
R1CN
KV C
R1 N

Prof S
...
As opposed to the XOR phase detector that we first considered, this one
produces two outputs: QA and QB, or as is customary, UP and DOWN respectively
...
J
...
Razavi, High Speed CMOS for Optical Receivers, Kluwer
Academic Publishing, 2001
...
It also has
zero offset when the phases are aligned and is insensitive to the duty cycle of the inputs
since edge-triggered flip-flops are used
...
Long 4/27/05

29

PFD characteristic
...
When there is a
phase or frequency error, the width of the UP or DOWN pulses increases
...

Because both outputs must be combined to obtain the desired output, the loop filter must
be modified for differential inputs as shown below
...


R2

DOWN

R1

_

C

+

UP
R1
R2

C

UCSB/ECE Department

Prof S
...
It is very convenient to implement in CMOS
...


•

Charge pump current sources I1 and I2 must produce exactly equal currents
...


•

If there is a static phase error ∆φ at the PFD input, the capacitor, C, will be
charged indefinitely – therefore, the DC gain is infinite: an ideal integrator
...
This is unlike the type I loop which
gave ∆φ = ∆ω/KV steady state phase error
...

This phase comparison occurs on every cycle
...
Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
...
15
...
Here we assume that I1 = I2 = IP and that a phase step ∆φ
occurs at t = 0
...
Long 4/27/05

31

(from B
...

First consider the time domain picture above
...

2π
IP charges Cp by

∆V =

IP
I φ
∆t = P 0 Tin
CP
C P 2π

in every period
...
Long 4/27/05

32

The derivative of the step response is the impulse response, so we can determine the
frequency domain transfer function
...


H( s ) =

φin(s)
+

Σ

Vout ( s )
I
1 K PFD
= P
=
2πC P s
∆φ
s

φout(s)

KPFD/s

KVCO/s

−

PFD/CP/LPF

VCO

Here is the block diagram of the CP PLL
...
Thus, it is a type II loop
...
The phase margin is always zero as shown
by the Bode plot below
...
Long 4/27/05

33

20 log |T(jω)|

Crossover freq
...


IP
QA

A

UP

PFD
B

VCO

DOWN
QB

RP
IP
CP

UCSB/ECE Department

Prof S
...

ωz

0
∠T(jω)
-90

-180
Now, we can see that an increase in the loop gain will improve phase margin
...

New filter:

Vout(s)
I(s)
RP
CP

UCSB/ECE Department

Prof S
...
So, the current source can be modeled as:

I( s ) I P
=

...
To do this, just replace
the impedance 1/sCP with Z(s) = RP + 1/sCP
...

=
∆φ
2π ⎝
sC P ⎟⎠
The loop gain T(s) is therefore

T( s ) =

=

φout ( s ) I P ⎛
1 ⎞ KVCO
⎜⎜ RP +
⎟
=
2π ⎝
sC P ⎟⎠ s
φin

I P KVCO (RP C P s + 1)
2πC P
s2

We see that a zero at ω = 1/RPCP has been added to the transfer function
...

Of course a frequency divider can be placed in the feedback path if the output frequency
is to be multiplied by the PLL
...


UCSB/ECE Department

Prof S
...


T( s ) =

I P KVCO (RP C P s + 1)
2πNC P
s2

Now, let’s retain the factor of 1/N for completeness, and derive the closed loop transfer
function
...


φout ( s )
KV ( s / ω z + 1) / s 2
=
φin
1 + KV ( s / ω z + 1) / Ns 2
=

N ( s / ω z + 1)
N 2 s
+1
s +
ωz
KV

Having put this in one of the standard forms, we can extract ωn and ζ from the
denominator
...
With added RP, the damping factor can be increased
...
Long 4/27/05

37

that stability will decrease with increasing N
...

The root locus of the modified charge pump PLL is shown below
...


(2)
-1/RPCP

As loop gain is increased by increasing IPKVCO, the dual poles at s = 0 split and form a
circular locus, rejoining the real axis at – 1/2RPCP
...
Long 4/27/05

38

Closed Loop Frequency Response
The closed loop frequency response can be evaluated from H(jω)
...
2-3, Gardner
has plotted the magnitude as a function of ω/ωn
...
It is
determined by ωn and ζ, so bandwidth must be determined in conjunction with the
overshoot and settling time specifications
...


[

ω h = ω3dB = ω n 1 + 2ζ 2 + (2ζ 2 + 1) 2 + 1
ω3db = 2 ωn
ω3db = 2
...
707
for ζ = 1

Since the loop gain peaking and overshoot is greater when the zero is present, we also
expect bandwidth to be higher as this shows
...
Thus, the phase noise of the
reference source passes through the PLL and is filtered as shown in Fig
...
Below the
3 dB frequency, we have little attenuation of input noise
...

Also note that for ζ < 2, there is gain peaking
...
For some applications,
this is inconsequential
...
1 dB of gain peaking is allowed
...
Cascaded transfer functions with gain peaking leads to amplification of jitter
(phase noise) close to the 3 dB frequency
...
Long 4/27/05

39

Third-order CP PLL
There is still one residual problem that we have overlooked
...
Now that we have added the resistor, however, we find that the control
voltage coming out of the charge pump will jump up or down before settling to its steady
state value
...
This jumpy control voltage frequency modulates the VCO at the reference
frequency, creating reference spurs
...
But, at larger N values, it creates
sidebands and jitter
...
The magnitude of the reference spur
sidebands is reduced by a factor of ωREF/ωC2
...
Long 4/27/05

40

pole of finite frequency that will reduce the stability of the PLL
...


C P + C2
RP C P C 2

IP
QA

φIN

UP

PFD

VCO

DOWN
QB

RP

C2

IP
CP

20 log |T(jω)|

Crossover freq
...
Long 4/27/05

41

The pole frequency is given by RP in parallel with the series combination of CP and C2
...
We can see that the added
pole reduces the phase margin
...
So, we must be careful that the pole frequency added by C2 is much
higher than the loop bandwidth
...


UCSB/ECE Department

Prof S
...
But it also plays a role in the PLL noise behavior
...
There are at least 2 main
sources:
1
...
VCO noise – often high
...


The effect caused by each of these noise sources can be seen from the closed loop
transfer functions
...
Its magnitude approaches N as s becomes small
...
Reference phase noise can
be quite low when a crystal oscillator is used to generate the reference frequency
...


φout
=N
φref
This is a serious limitation for large N values
...


UCSB/ECE Department

Prof S
...
It approaches a magnitude of 1 as s
becomes large
...

RC or ring oscillator VCOs can be built with very wide tuning range but poor phase
noise
...

VCO phase noise is unattenuated at offset frequencies beyond the loop bandwidth
...
Reference input noise (reference source noise, data jitter, phase noise on FM input
signal, etc
...
It is passed through and multiplied by N
...
A narrow bandwidth loop
filter will help to suppress high frequency noise coming into the PLL from the reference
port
...
VCO jitter is suppressed by the PLL within the loop bandwidth
...
Thus, to suppress VCO noise, we want a large loop bandwidth
...
Long 4/27/05

44

Reference Spurs
...
The phase detector produces pulses that are at the
reference frequency, fR
...
Any residual reference frequency component on the VCO tuning voltage
produces frequency modulation
...

The natural frequency of the loop must be well below the reference frequency so that the
reference frequency component is well attenuated by the loop filter
...
Compromises must be made
...

R2

R1/2

PD inputs

R1/2

_

C2
R1/2
C2

C1

+
R1/2
R2
C1

Resistor R1 has been split in half and capacitor C2 added to produce a finite pole at

ωC 2 = 4 / R1C 2
...


UCSB/ECE Department

Prof S
...
Long 4/27/05

46



---