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Digital Circuits - Shift Registers
A flip-flop can store a single piece of data, as we are all too
aware
...
The collection of flip-flops used to store
binary data is referred to as a "register
...
A 'N' bit shift register contains
'N' flip-flops
...

Serial In − Serial Out shift register
• Serial In − Parallel Out shift register
• Parallel In − Serial Out shift register
• Parallel In − Parallel Out shift register
Serial In − Serial Out SISOSISO Shift Register
The shift register, which allows serial input and produces serial
output is known as Serial In – Serial Out SISOSISO shift register
...

•

This block diagram shows three cascaded D flip-flops
...
All flip-flops are synced with one another
since they all get the same clock signal
...
Flops As a result, this input is sometimes
referred to as a serial input
...
We are able to extract bits serially from the right-most
D flip-output as a consequence
...

Example
Let us see the working of 3-bit SISO shift register by sending the
binary information “011” from LSB to MSB serially at the input
...
We can understand
the working of 3-bit SISO shift register from the following table
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Here, the serial output is coming
from Q0Q0
...

Therefore, the 3-bit SISO shift register requires five clock pulses
in order to produce the valid output
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Serial In - Parallel Out SIPOSIPO Shift Register
The shift register, which allows serial input and produces parallel
output is known as Serial In – Parallel Out SIPOSIPO shift register
...


This circuit consists of three D flip-flops, which are cascaded
...
All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one
...
Hence, this input is also called as serial
input
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In this case, we can access the
outputs of each D flip-flop in parallel
...

Example
Let us see the working of 3-bit SIPO shift register by sending the
binary information “011” from LSB to MSB serially at the input
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Here, Q2Q2 & Q0Q0 are MSB & LSB respectively
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Q2MSBMSB Q1 Q0LSBLSB

No of positive
edge of Clock

Serial
Input

0

-

0

0

0

1

1LSBLSB

1

0

0

2

1

1

1

0

3

0MSBMSB

0

1

1

The initial status of the D flip-flops in the absence of clock signal
is Q2Q1Q0=000Q2Q1Q0=000
...

So, the 3-bit SIPO shift register requires three clock pulses in
order to produce the valid output
...

Parallel In − Serial Out PISOPISO Shift Register
The shift register, which allows parallel input and produces serial
output is known as Parallel In − Serial Out PISOPISO shift register
...


This circuit consists of three D flip-flops, which are cascaded
...
All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one
...
For every positive edge
triggering of clock signal, the data shifts from one stage to the
next
...

Example
Let us see the working of 3-bit PISO shift register by applying the
binary information “011” in parallel through preset inputs
...
We can understand the working
of 3-bit PISO shift register from the following table
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So, the LSB 11 is
received before applying positive edge of clock and the
MSB 00 is received at 2nd positive edge of clock
...
Similarly, the N-bit PISO
shift register requires N-1 clock pulses in order to shift ‘N’ bit
information
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The block diagram of 3-bit PIPO shift
register is shown in the following figure
...

That means, output of one D flip-flop is connected as the input
of next D flip-flop
...

In this shift register, we can apply the parallel inputs to each D
flip-flop by making Preset Enable to 1
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These two are asynchronous
inputs
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In this

case, the effect of outputs is independent of clock transition
...

Example
Let us see the working of 3-bit PIPO shift register by applying the
binary information “011” in parallel through preset inputs
...

So,
the
binary
information “011” is obtained in parallel at the outputs of D flipflops before applying positive edge of clock
...
Similarly, the N-bit PIPO
shift register doesn’t require any clock pulse in order to shift ‘N’
bit information
...

Based on the requirement, we can use one of those shift
registers
...

•

•

Shift register is used as Parallel to serial converter,
which converts the parallel data into serial data
...

Shift register is used as Serial to parallel converter,
which converts the serial data into parallel data
...

Shift register along with some additional
gatess generate the sequence of zeros and ones
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Shift registers are also used as counters
...

Those are Ring counter and Johnson Ring counter
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Ring Counter
In previous chapter, we discussed the operation of Serial In Parallel Out SIPOSIPO shift register
...

Similarly, ‘N’ bit Ring counter performs the similar operation
...
Therefore, Ring counter produces a sequence of
states patternofzerosandonespatternofzerosandones and
it
repeats for every ‘N’ clock cycles
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The 3-bit Ring counter contains only a 3-bit SIPO shift register
...

Assume, initial status of the D flip-flops from leftmost to
rightmost
is Q2Q1Q0=001Q2Q1Q0=001
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We can
understand the working of Ring counter from the following
table
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This status repeats for every
three positive edge transitions of clock signal
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Serial input of first D flip-flop gets the previous output
of third flip-flop
...

• The previous outputs of first and second D flip-flops are
right shifted by one bit
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Johnson Ring Counter
The operation of Johnson Ring counter is similar to that of Ring
counter
...
Therefore, ‘N’ bit Johnson Ring
counter
produces
a
sequence
of
states patternofzerosandonespatternofzerosandones and
it
repeats for every ‘2N’ clock cycles
...
The block diagram of 3-bit Johnson Ring
counter is shown in the following figure
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The complemented output of rightmost D flip-flop
is connected to serial input of left most D flip-flop
...

So, Q2Q1Q0=000Q2Q1Q0=000
...
We can understand the working of Johnson
Ring counter from the following table
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This status repeats for every six
positive edge transitions of clock signal
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•

•

Serial input of first D flip-flop gets the previous
complemented output of third flip-flop
...

The previous outputs of first and second D flip-flops are
right shifted by one bit
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Digital Circuits - Counters
In previous two chapters, we discussed various shift registers
& counters using D flipflops
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We know that T flip-flop toggles the output
either for every positive edge of clock signal or for negative edge
of clock signal
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If the counter
counts from 0 to 2𝑁 − 1, then it is called as binary up counter
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There are two types of counters based on the flip-flops that are
connected in synchronous or not
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The output of system
clock is applied as clock signal only to first flip-flop
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Hence, the outputs of all flip-flops do not
change affectaffect at the same time
...

Asynchronous Binary up counter
• Asynchronous Binary down counter
Asynchronous Binary Up Counter
•

An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flipflops
...
The block diagram of 3-bit
Asynchronous binary up counter is shown in the following figure
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All
these flip-flops are negative edge triggered but the outputs
change asynchronously
...
So, the output of first T flip-flop toggles for every
negative edge of clock signal
...
So, the output of second T flip-flop toggles for every
negative edge of output of first T flip-flop
...

Assume the initial status of T flip-flops from rightmost to
leftmost is Q2Q1Q0=000Q2Q1Q0=000
...
We can understand the working of 3-bit
asynchronous binary counter from the following table
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Q1Q1 toggled for every Q0Q0 that goes from 1 to 0,
otherwise
remained
in
the
previous
state
...

The initial status of the T flip-flops in the absence of clock signal
is Q2Q1Q0=000Q2Q1Q0=000
...
This pattern repeats
when further negative edges of clock signal are applied
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It counts from 2𝑁 − 1 to 0
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The block diagram of 3-bit Asynchronous binary down counter is
similar to the block diagram of 3-bit Asynchronous binary up
counter
...
Complemented
output goes from 1 to 0 is same as the normal output goes from
0 to 1
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Here, Q2Q2 & Q0Q0 are
MSB & LSB respectively
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No of negative edge
of Clock

Q0LSBLSB

Q1

Q2MSBMSB

0

0

0

0

1

1

1

1

2

0

1

1

3

1

0

1

4

0

0

1

5

1

1

0

6

0

1

0

7

1

0

0

Here Q0Q0 toggled for every negative edge of clock
signal
...

Similarly, Q2Q2 toggled for every Q1Q1 that goes from 0 to 1,
otherwise remained in the previous state
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This is decremented by one for
every negative edge of clock signal and reaches to the same
value at 8th negative edge of clock signal
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Synchronous Counters
If all the flip-flops receive the same clock signal, then that
counter is called as Synchronous counter
...

Now, let us discuss the following two counters one by one
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It counts from 0 to 2𝑁 − 1
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The 3-bit Synchronous binary up counter contains three T flipflops & one 2-input AND gate
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The T inputs of first, second
and third flip-flops are 1, Q0Q0 & Q1Q0Q1Q0 respectively
...
The output of second T flip-flop toggles for every
negative edge of clock signal if Q0Q0 is 1
...

Synchronous Binary Down Counter
An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flipflops
...
The block diagram of 3-bit
Synchronous binary down counter is shown in the following
figure
...
All these flip-flops are negative
edge
triggered
and
the
outputs
of
flip-flops
change affectaffect synchronously
...

The output of first T flip-flop toggles for every negative edge of
clock signal
...
The output of third T
flip-flop toggles for every negative edge of clock signal if
both Q1′Q1′ & Q0′Q0′ are 1

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