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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

Module 1 learning unit 1
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A Computer is a programmable machine
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It can execute a prerecorded list of instructions (a program )
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The actual machinery wires, transistors, and circuits is called hardware
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All general-purpose computers require the following hardware components:
Memory: Enables a computer to store, at least temporarily, data and programs
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Common mass storage devices include disk drives and tape drives
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Output device: A display screen, printer, or other device that lets you see what
the computer has accomplished
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In addition to these components, many others make it possible for the basic
components to work together efficiently
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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

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Computers can be generally classified by size and power as follows, though there
is considerable overlap:
• Personal computer: A small, single-user computer based on a microprocessor
...

• Working station: A powerful, single-user computer
...

• Minicomputer: A multi-user computer capable of supporting from 10 to
hundreds of users simultaneously
...

• Supercomputer: An extremely fast computer that can perform hundreds of
millions of instructions per second
...
In size and power, minicomputers lie between workstations
and mainframes
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• Typically, minicomputers have been stand-alone computers (computer systems
with attached terminals and other devices) sold to small and mid-size businesses
for general business applications and to large enterprises for department-level
operations
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IBM's AS/400e is a good example
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• The AS/400 uses the PowerPC microprocessor with its reduced instruction set
computer technology
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• With multi-terabytes of disk storage and a Java virtual memory closely tied into
the operating system, IBM hopes to make the AS/400 a kind of versatile allpurpose server that can replace PC servers and Web servers in the world's
businesses, competing with both Wintel and Unix servers, while giving its present
enormous customer base an immediate leap into the Internet
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• Workstations generally come with a large, high- resolution graphics screen, at
least 64 MB (mega bytes) of RAM, built-in network support, and a graphical user
interface
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Krishna Kumar/IISc
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• The most common operating systems for workstations are UNIX and Windows
NT
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• High-end personal computers are equivalent to low-end workstations
...

• Like personal computers, most workstations are single-user computers
...

2) In networking, workstation refers to any computer connected to a local-area
network
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• Mainframe: A very large and expensive computer capable of supporting
hundreds, or even thousands, of users simultaneously
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• In some ways, mainframes are more powerful than supercomputers because they
support more simultaneous programs
...
The
distinction between small mainframes and minicomputers is vague, depending
really on how the manufacturer wants to market its machines
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• Microcomputers are designed to be used by individuals, whether in the form of
PCs, workstations or notebook computers
...

• Microprocessor: A silicon chip that contains a CPU
...

• A microprocessor (sometimes abbreviated µP) is a digital electronic component
with miniaturized transistors on a single semiconductor integrated circuit (IC)
...

• Microprocessors made possible the advent of the microcomputer
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• Microprocessors also control the logic of almost all digital devices, from clock
radios to fuel-injection systems for automobiles
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• Bandwidth: The number of bits processed in a single instruction
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Microprocessors and Microcontrollers/Architecture of Microprocessors

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Lecture Notes

In both cases, the higher the value, the more powerful the CPU
...

In addition to bandwidth and clock speed, microprocessors are classified as being
either RISC (reduced instruction set computer) or CISC (complex instruction set
computer)
...

A supercomputer is typically used for scientific and engineering applications that
must handle very large databases or do a great amount of computation (or both)
...

The term is also sometimes applied to far slower (but still impressively fast)
computers
...

In general, there are two parallel processing approaches: symmetric
multiprocessing (SMP) and massively parallel processing (MPP)
...

Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers
...

A microcontroller differs from a microprocessor, which is a general-purpose chip
that is used to create a multi-function computer or device and requires multiple
chips to handle various tasks
...

The great advantage of microcontrollers, as opposed to using larger
microprocessors, is that the parts-count and design costs of the item being
controlled can be kept to a minimum
...

Microcontrollers are sometimes called embedded microcontrollers, which just
means that they are part of an embedded system that is, one part of a larger device
or system
...

For example, disk drives, display screens, keyboards and printers all require
controllers
...

When you purchase a computer, it comes with all the necessary controllers for
standard components, such as the display screen, keyboard, and disk drives
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Krishna Kumar/IISc
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Controllers must be designed to communicate with the computer's expansion bus
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When you purchase a controller, therefore, you must ensure that it conforms to
the bus architecture that your computer uses
...

Most modern PCs include a PCI bus in addition to a more general IAS expansion
bus
...

PCI is a 64-bit bus, though it is usually implemented as a 32 bit bus
...

At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps
...

Nearly all Apple Macintosh computers, excluding only the earliest Macs and the
recent iMac, come with a SCSI port for attaching devices such as disk drives and
printers
...
In addition, you can attach many
devices to a single SCSI port, so that SCSI is really an I/O bus rather than simply
an interface
Although SCSI is an ANSI standard, there are many variations of it, so two SCSI
interfaces may be incompatible
...

While SCSI has been the standard interface for Macintoshes, the iMac comes with
IDE, a less expensive interface, in which the controller is integrated into the disk
or CD-ROM drive
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SCSI-2: Same as SCSI-1, but uses a 50-pin connector instead of a 25-pin
connector, and supports multiple devices
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Wide SCSI: Uses a wider cable (168 cable lines to 68 pins) to support 16-bit
transfers
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Fast Wide SCSI: Uses a 16-bit bus and supports data rates of 20 MBps
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Wide Ultra2 SCSI: Uses a 16-bit bus and supports data rates of 80 MBps
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Also called Ultra
Wide SCSI
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Microprocessors and Microcontrollers/Architecture of Microprocessors

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Lecture Notes

Embedded system: A specialized computer system that is part of a larger system
or machine
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Virtually all appliances that have a digital Interface- watches, microwaves, VCRs,
cars -utilize embedded systems
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MICRO CONTROLLER

MICRO PROCESSER

• It is a single chip
• Consists Memory,
I/o ports

• It is a CPU
• Memory, I/O Ports to be
connected externally

CP

CPU

MEMORY

MEMORY
I/O PORTS

I/O PORTS

Definitions:
• A Digital Signal Processor is a special-purpose CPU (Central Processing Unit)
that provides ultra-fast instruction sequences, such as shift and add, and multiply
and add, which are commonly used in math-intensive signal processing
applications
...

Digital
– operating by the use of discrete signals to represent data in the form of
numbers
...

Processing
– to perform operations on data according to programmed instructions
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• Digital signal processing (DSP) is the study of signals in a digital representation
and the processing methods of these signals
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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

DSP has three major subfields:
• Audio signal processing, Digital image processing and Speech processing
...

• Often, the required output signal is another analog output signal, which requires a
digital to analog converter
...

• Special Instructions for SIMD (Single Instruction, Multiple Data) operations
...

• The ability to act as a direct memory access device if in a host environment
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• analog input-->ADC-->DSP-->DAC--> analog output
...

• In order to implement this efficiently, the DSP has an hardware multiplier, an
accumulator with an adequate number of bits to hold the sum of products and at
explicit multiply-accumulate instructions
...

Program memory and data memory
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Krishna Kumar/IISc
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Krishna Kumar/IISc
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This arrangement doubles the
processor memory bandwidth
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The term zero overhead looping means that the processor can execute loops
without consuming cycles to test the value of the loop counter, perform a
conditional branch to the top of the loop, and decrement the loop counter
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Krishna Kumar/IISc
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Simplicity:
• some things can be done more easily digitally than with analogue systems
• DSP is used in a very wide variety of applications but most share some common
features:
• they use a lot of multiplying and adding signals
...

• they require a response in a certain time
...

In contrast, general-purpose processors or microcontrollers (GPPs / MCUs for
short) are either not specialized for a specific kind of applications (in the case of
general-purpose processors), or they are designed for control-oriented
applications (in the case of microcontrollers)
...

Specialized addressing modes, for example, pre- and post-modification of address
pointers, circular addressing, and bit-reversed addressing
...
DSPs generally feature multiple-access memory
architectures that enable DSPs to complete several accesses to memory in a single
instruction cycle
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Usually, DSP processors provide a loop instruction
that allows tight loops to be repeated without spending any instruction cycles for
updating and testing the loop counter or for jumping back to the top of the loop
• DSP processors are known for their irregular instruction sets, which generally
allow several operations to be encoded in a single instruction
...

• In general, DSP processor instruction sets allow a data move to be performed in
parallel with an arithmetic operation
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• What is really important is to choose the processor that is best suited for your
application
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• It is also worth noting that the difference between DSPs and GPPs/MCUs is
fading: many GPPs/MCUs now include DSP features, and DSPs are increasingly
adding microcontroller features
...

• It is manufactured with N-MOS technology
...

• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7
...

• It supports external interrupt request
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• It requires a signal +5V power supply and operates at 3
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• It is enclosed with 40 pins DIP (Dual in line package)
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5
RST 6
...
5

7

34

RESE OUT

Serial i/p, o/p signals

8
9

37

8085 A

READY

RESET IN
IO /

M

S1

33
32

RD

31

WR

30

ALE

29

S0

28

A15
A14

16

27
26
25

INTR

10

IN T A
AD0

11

AD1

13

AD2

14

AD3

15

AD4

12

AD5

DMA

A13
A12

17

24

A11

AD6

18

23

A10

AD7

19

22

A9

VSS

20

21

A8

Pin Diagram of 8085
Signal Groups of 8085
+5V

SID

XTAL
X1 X2
5

SOD

Vcc

GND
Vss
A15
A8

4

TRAP
RESET 7
...
5
RESET 5
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5

INTA

RES
6
...
5

TRAP

SID

Lecture Notes

SIO

INT
SERIAL I / O CONTROL

INTERRUPT CONTROL

8 BIT INTERNAL
DATA BUS

INSTRUCTION
REGISTER( 8 )

(8)
TEMP REG

ACCUMULATOR
(8)

FLAG ( 5)
FLIP FLOPS
INSTRUCTION
DECODER AND
MACHINE
ENCODING

ARITHEMETIC
LOGIC UNIT ( ALU)
(8)

+5V
GND
X1
X2

CLK
GEN

CLK
OUT

MULTIPLXER
W(8)
R
TEMP
...

E
C REG ( 8 )
G
B REG ( 8 )

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The total
addressable memory size is 64 KB
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Jump, branch
and call instructions use 16-bit addresses, i
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they can be used to jump/branch
anywhere within 64 KB
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• Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere
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Stack grows downward
...

Interrupts
• The processor has 5 interrupts
...
When the interrupt occurs the
processor fetches from the bus one instruction, usually one of these instructions:
• One of the 8 RST instructions (RST0 - RST7)
...

• CALL instruction (3 byte instruction)
...

• RST5
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When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 2CH
(hexadecimal) address
...
5 is a maskable interrupt
...

• RST7
...
When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 3CH
(hexadecimal) address
...
When this interrupt is received the processor
saves the contents of the PC register into stack and branches to 24H
(hexadecimal) address
...

RST 5
...
5 and RST7
...

Reset Signals
• RESET IN: When this signal goes low, the program counter (PC) is set to Zero,
µp is reset and resets the interrupt enable and HLDA flip-flops
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• RESET IN is a Schmitt-triggered input, allowing connection to an R-C network
for power-on RESET delay
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• For proper reset operation after the power – up duration, RESET IN should be
kept low a minimum of three clock periods
...
Typical
Power-on RESET RC values R1 = 75KΩ, C1 = 1µF
...
This signal can be used
to reset other devices
...

Serial communication Signal
• SID - Serial Input Data Line: The data on this line is loaded into accumulator bit
7 whenever a RIM instruction is executed
...

DMA Signals
• HOLD: Indicates that another master is requesting the use of the address and data
buses
...

• Internal processing can continue
...

• When the HOLD is acknowledged, the Address, Data RD, WR and IO/M lines are
3-stated
...

• HLDA goes low after the Hold request is removed
...

• READY: This signal Synchronizes the fast CPU and the slow memory,
peripherals
...

• If READY is low, the CPU will wait an integral number of clock cycle for
READY to go high before completing the read or write cycle
...

Registers
• Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and
load/store operations
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• Sign - set if the most significant bit of the result is set
...

• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result
...

• Carry - set if there was a carry during addition, or borrow during
subtraction/comparison/rotation
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When
used as a pair the C register contains low-order byte
...

• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair
...
Some instructions may use
DE register as a data pointer
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When
used as a pair the L register contains low-order byte
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• Stack pointer is a 16 bit register
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• Program counter is a 16-bit register
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• Arithmetic - add, subtract, increment and decrement
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• Control transfer - conditional, unconditional, call subroutine, return from
subroutine and restarts
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• Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations,
etc
...

Register indirect - instruction specifies register pair containing address, where
the data is located
...

Module 1: learning unit 3
8086 Microprocessor
•It is a 16-bit µp
...

•It can support up to 64K I/O ports
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•It has multiplexed address and data bus AD0- AD15 and A16 – A19
...

•8086 is designed to operate in two modes, Minimum and Maximum
...

•It requires +5V power supply
...
This is a
single microprocessor configuration
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This is a
multi micro processors configuration
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Krishna Kumar/IISc
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•The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands
...

•EU executes instructions from the instruction system byte queue
...
This results in efficient use of the
system bus and system performance
...

•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,
Flag register
...

•The bus interface unit is responsible for performing all external bus operations
...

•The BIU uses a mechanism known as an instruction stream queue to implement a
pipeline architecture
...
When ever the queue
of the BIU is not full, it has room for at least two more bytes and at the same time the EU

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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction
...
With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle
...

•The EU accesses the queue from the output end
...
If the queue is full and the EU is not requesting access
to operand in memory
...

•If the BIU is already in the process of fetching an instruction when the EU request it to
read or write operands from memory or I/O, the BIU first completes the instruction fetch
bus cycle before initiating the operand read / write cycle
...
This address is formed by adding an appended
16 bit segment address and a 16 bit offset address
...

•The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write
...

•The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the
read or write bys cycles to memory or I/O and perform the operation specified by the
instruction on the operands
...

•If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue
...

•Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue
...

•The 8086 operates in single processor or multiprocessor configuration to achieve high
performance
...

•The 8086 signals can be categorised in three groups
...

•The second are the signals which have special functions for minimum mode and third
are the signals having special functions for maximum mode
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•AD15-AD0: These are the time multiplexed memory I/O address and data lines
...

•These lines are active high and float to a tristate during interrupt acknowledge and local
bus hold acknowledge cycles
...

•During T1 these are the most significant address lines for memory operations
...
During memory or I/O operations, status
information is available on those lines for T2,T3,Tw and T4
...

•The S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as in below fig
...
The status line
S6 is always low
...


S4

S3

0
0
1
1

0
1
0
1

Indication
Alternate Data
Stack
Code or none
Data

• BHE /S7: The bus high enable is used to indicate the transfer of data over the higher
order ( D15-D8 ) data bus as shown in table
...
BHE is
low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus
...
The signal is active low and tristated during hold
...


BHE
0
0
1
1

A0
0
1
0
1

Indication
Whole word
Upper byte from or to odd address
even address
Lower byte from or to even address
None

• RD Read: This signal on low indicates the peripheral that the processor is performing s
memory or I/O read operation
...
The signal remains tristated during the hold acknowledge
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The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086
...

•INTR-Interrupt Request: This is a triggered input
...
If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle
...
This signal is active
high and internally synchronized
...
If the TEST pin goes low,
execution will continue, else the processor remains in an idle state
...

•CLK- Clock Input: The clock input provides the basic timing for processor operation
and bus control activity
...

•MN/ MX : The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode
...

•M/ IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode
...
This line becomes active high in
the previous T4 and remains active till final T4 of the current cycle
...

• INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles
...
e
...

•ALE – Address Latch Enable: This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches
...

•DT/ R – Data Transmit/Receive: This output is used to decide the direction of data
flow through the transreceivers (bidirectional buffers)
...

•DEN – Data Enable: This signal indicates the availability of valid data over the
address/data lines
...
It is active from the middle of
T2 until the middle of T4
...

•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus access
...
•At the same time, the processor floats the local bus and control lines
...
HOLD is an
asynchronous input, and is should be externally synchronized
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The request occurs on or before T2 state of the current cycle
...
The current cycle is not operating over the lower byte of a word
...
The current cycle is not the first acknowledge of an interrupt acknowledge sequence
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A Lock instruction is not being executed
...

•S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor
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S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Indication
Interrupt Acknowledge
Read I/O port
Write I/O port
Halt
Code Access
Read memory
Write memory
Passive

• LOCK This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low
...
When the CPU is executing a critical instruction
which requires the system bus, the LOCK prefix instruction ensures that other processors
connected in the system will not gain the control of the bus
...

•QS1, QS0 – Queue Status: These lines give information about the status of the codeprefetch queue
...

•This modification in a simple fetch and execute architecture of a conventional
microprocessor offers an added advantage of pipelined processing of the instructions
...
Thus even the largest (6bytes) instruction can be prefetched from the memory and stored in the prefetch
...

•In 8085 an instruction is fetched, decoded and executed and only after the execution of
this instruction, the next one is fetched
...
This is known as instruction pipelining
...
Initially, the queue will be empty an the microprocessor starts a fetch
operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd
or two bytes at a time, if the CS:IP address is even
...

•The second byte is then decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as instruction data
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•The next byte after the instruction is completed is again the first opcode byte of the next
instruction
...
•The fetch operation of the next instruction is overlapped with the execution of
the current instruction
...

•While the execution unit is busy in executing an instruction, after it is completely
decoded, the bus interface unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status
...

•Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1
...

•Request/Grant sequence is as follows:
1
...

2
...
The CPU bus interface unit is likely
to be disconnected from the local bus of the system
...
A one clock wide pulse from the another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the next clock
cycle
...

There must be at least one dead clock cycle after each bus exchange
...

•For the bus request those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as in case of HOLD and HLDA in
minimum mode
...

•The main reason behind multiplexing address and data over the same pins is the
maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP
package
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Krishna Kumar/IISc
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•Basically, all the processor bus cycles consist of at least four clock cycles
...
The address is transmitted by the processor during T1
...

•The negative edge of this ALE pulse is used to separate the address and the data or status
information
...

•Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal
...

Memory read cycle
T2
T3
Tw

T1

T4

T1

Memory write cycle
T2
T3
Tw

T4

CLK
ALE
S2 – S0
Add/stat

A19-A16

S3-S7
Bus reserve
for Data In

BHE
Add/data

A19-A16
BHE

A0-A15

D15-D0

S3-S7

Data Out D15 – D0
A0-A15

RD/INTA

DT/R

Ready

Ready

READY
Wait

D15-D0

Wait

DEN
WR

Memory access time
General Bus Operation Cycle in Maximum Mode

Minimum Mode 8086 System
•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1
...

There is a single microprocessor in the minimum mode system
...
Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the system
...
They are
used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086
...
Krishna Kumar/IISc
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They are required to separate the valid data from the time multiplexed
address/data signals
...

•The DEN signal indicates the direction of data, i
...
from or to the processor
...

•Usually, EPROM are used for monitor storage, while RAM for users program storage
...

•The working of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than qualitatively describing the operations
...
Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle
...
During the negative going edge of this signal, the valid address is
latched on the local bus
...
From T1 to T4 , the M/IO
signal indicates a memory or I/O operation
...
The bus is
then tristated
...

•The read (RD) signal causes the address device to enable its data bus drivers
...

•The addressed device will drive the READY line high
...

•A write cycle also begins with the assertion of ALE and the emission of the address
...
In T2, after sending
the address in T1, the processor sends the data to be written to the addressed location
...
The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating)
...

•The M/IO, RD and WR signals indicate the type of data transfer as specified in table
below
...
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If it is received active by the processor before T4 of the previous cycle or during
T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the bus will be given to another requesting master
...
When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock
...
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...

•In this mode, the processor derives the status signal S2, S1, S0
...

•In the maximum mode, there may be more than one microprocessor in the system
configuration
...

•The basic function of the bus controller chip IC8288, is to derive control signals like RD
and WR ( for memory and I/O devices), DEN, DT/R, ALE etc
...

•The bus controller chip has input lines S2, S1, S0 and CLK
...

•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC
...

•AEN and IOB are generally grounded
...
The significance
of the MCE/PDEN output depends upon the status of the IOB pin
...

•INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to
an interrupting device
...
These
signals enable an IO interface to read or write the data from or to the address port
...

•All these command signals instructs the memory to accept or send data from or to the
bus
...

•Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals
...
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•R0, S1, S2 are set at the beginning of bus cycle
...

•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC
...
For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4
...

•If reader input is not activated before T3, wait state will be inserted between T3 and T4
...
The request/grant
pins are checked at each rising pulse of clock input
...

•When the requesting master receives this pulse, it accepts the control of the bus, it sends
a release pulse to the processor using RQ/GT pin
...
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...
Krishna Kumar/IISc
...

Clk

RQ / GT

Another master
request bus access

CPU grant bus

Master releases

RQ/GT Timings in Maximum Mode
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

•The minimum mode signal can be divided into the following basic groups: address/data
bus, status, control, interrupt and DMA
...
As an address bus is 20 bits long
and consists of signal lines A0 through A19
...
A
20bit address gives the 8086 a 1Mbyte memory address space
...

•The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0
through A15 respectively
...
D15 is the MSB
and D0 LSB
...

Vcc

GND

INTR

A0-A15,A16/S3 – A19/S6

INTA

Interrupt
interface

Address / data bus
TEST
D0 – D15

NMI
8086
MPU

RESET

ALE
BHE / S7
M / IO

HOLD

DMA
interface

DT / R

Memory I/O
controls

RD

HLDA

WR
Vcc
DEN

Mode select

READY

MN / MX
CLK clock

Block Diagram of the Minimum Mode 8086 MPU
•Status signal:
The four most significant address lines A19 through A16 are also multiplexed but in this
case with status signals S6 through S3
...

•Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal
segment registers are used to generate the physical address that was output on the address
bus during the current bus cycle
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

•Status line S5 reflects the status of another internal characteristic of the 8086
...
The last status bit S6 is always at the logic 0 level
...

•Control Signals:
The control signals are provided to support the 8086 memory I/O interfaces
...

•ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on
the bus
...

•Another control signal that is produced during the bus cycle is BHE bank high enable
...
These lines also serves a second function, which is as the S7
status line
...

•The logic level of M/IO tells external circuitry whether a memory or I/O transfer is
taking place over the bus
...

•The direction of data transfer over the bus is signaled by the logic level output at DT/R
...
Therefore, data are either written into memory or output to an I/O device
...
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This
corresponds to reading data from memory or input of data from an input port
...
The 8086 switches WR to logic 0 to signal external device that valid write or
output data are on the bus
...

During read operations, one other control signal is also supplied
...

•There is one other control signal that is involved with the memory and I/O interface
...

•READY signal is used to insert wait states into the bus cycle such that it is extended by
a number of clock periods
...

•Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and
interrupt acknowledge ( INTA)
...

•Logic 1 at INTR represents an active interrupt request
...

•The TEST input is also related to the external interrupt interface
...

•If the logic 1 is found, the MPU suspend operation and goes into the idle state
...

•As TEST switches to 0, execution resume with the next instruction in the program
...

•There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and
the reset interrupt RESET
...
The RESET input is used to provide a hardware reset for the 8086
...

•DMA Interface signals:The direct memory access DMA interface of the 8086
minimum mode consist of the HOLD and HLDA signals
...
At the completion of the current bus cycle, the
8086 enters the hold state
...

The 8086 signals external device that it is in this state by switching its HLDA output to
logic 1 level
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

•By multiprocessor environment we mean that one microprocessor exists in the system
and that each processor is executing its own program
...

•They are called as global resources
...
These are known as local or private resources
...
In this two
processor does not access the bus at the same time
...

•In the maximum-mode 8086 system, facilities are provided for implementing allocation
of global resources and passing bus control to other microprocessor or coprocessor
...

•Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced
by the 8086
...
This 3- bit bus status code identifies which type of bus cycle is to follow
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

Status Inputs

CPU Cycles

S2

S1

S0

0
0
0
0

0
0
1
1

0
1
0
1

Interrupt Acknowledge

1

0

0

Instruction Fetch

1

0

1

Read Memory

1

1
1

0

Write Memory

1

Read I/O Port
Write I/O Port
Halt

Passive

1

Lecture Notes

8288
Command
INTA
IORC
IOWC, AIOWC
None
MRDC
MRDC
MWTC, AMWC
None

Bus Status Codes
•The 8288 produces one or two of these eight command signals for each bus cycles
...

•In the code 111 is output by the 8086, it is signaling that no bus activity is to take place
...
These 3 signals
provide the same functions as those described for the minimum system mode
...

•The output of 8289 are bus arbitration signals:
Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority
in (BPRN), bus request (BREQ) and bus clock (BCLK)
...

•In this way the processor can be assured of uninterrupted access to common system
resources such as global memory
...
Together they form a 2-bit queue
status code, QS1QS0
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

QS1

Lecture Notes

Queue Status

QS0

0 (low)

0

No Operation
...


0

1

First Byte
...


0

Queue Empty
...


1 (high)
1

1

Subsequent Byte
...


Queue status codes
•Local Bus Control Signal – Request / Grant Signals: In a maximum mode
configuration, the minimum mode HOLD, HLDA interface is also changed
...
They provide a
prioritized bus access mechanism for accessing the local bus
...
They are the
instruction pointer, four data registers, four pointer and index register, four segment
registers
...

•Most of the registers contain data/instruction offsets within 64 KB memory segment
...
To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
•Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions
...
CS register cannot be changed directly
...

•Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack
...
SS register
can be changed directly using POP instruction
...
By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment
...

•Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX
...
Accumulator can be used
for I/O operations and string manipulation
...
Krishna Kumar/IISc
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BL in this case contains the low-order byte of the word,
and BH contains the high-order byte
...

•Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX
...
Count register can be used
in Loop, shift/rotate instructions and as a counter in string manipulation,
...
When combined, DL register contains the loworder byte of the word, and DH contains the high-order byte
...
In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number
...

•Base Pointer (BP) is a 16-bit register pointing to data in stack segment
...

•Source Index (SI) is a 16-bit register
...

•Destination Index (DI) is a 16-bit register
...

Other registers:
•Instruction Pointer (IP) is a 16-bit register
...

•Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand
...
If cleared then the index registers will be auto-incremented
...

•Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction
...

•Zero Flag (ZF) - set if the result is zero
...

•Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even
...

Addressing Modes
•Implied - the data value/data address is implicitly associated with the instruction
...

•Immediate - the data is provided in the instruction
...


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Microprocessors and Microcontrollers/Architecture of Microprocessors

Lecture Notes

•Register indirect - instruction specifies a register containing an address, where data is
located
...

•Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register
(BX or BP), the resulting value is a pointer to location where data resides
...

•Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is
a pointer to location where data resides
...
As the
most of the processor instructions use 16-bit pointers the processor can effectively
address only 64 KB of memory
...

•16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
•Program memory - program can be located anywhere in memory
...

•All conditional jump instructions can be used to jump within approximately +127 to 127 bytes from current instruction
...

•Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment)
...
The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries
...

•Stack memory can be placed anywhere in memory
...

Reserved locations:
•0000h - 03FFh are reserved for interrupt vectors
...

•FFFF0h - FFFFFh - after RESET the processor always starts program execution at the
FFFF0h address
...
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The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction
...

Interrupt processing routine should return with the IRET instruction
...
Interrupt is processed in the same way as the INTR
interrupt
...
e
...
This interrupt has higher priority then the maskable interrupt
...
This is a type 3 interrupt
...

•INTO instruction - interrupt on overflow
•Single-step interrupt - generated if the TF flag is set
...
When the
CPU processes this interrupt it clears TF flag before calling the interrupt processing
routine
...

•Software interrupt processing is the same as for the hardware interrupts
...
Krishna Kumar/IISc

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