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DIGITAL ELECTRONICS

PART-II

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map
Truth table and K-map for voting m/c
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

V
0
0
0
1
0
1
1
1

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map

The terms shown in the gray area of the K-map are

These two terms can be combined to give

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map
K-map for four variables

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map
K-map for four variables

X
Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map
K-map for four variables

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

K-map
K-map for four variables

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Sequential Logic Circuit

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

SR NOR latch

SR latch operation
Action
Last state

S
0

R
0

0
1

1
0

Q = 0, Reset state
Q = 1 ,Set state

1

1

Forbidden input combination

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Clocked SR latch

Clocked SR latch is level sensitive

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Z

Clocked D latch

Clocked D latch based on SR NOR latch
The Clocked D latch has only one input (D for Data)
apart from the clock
...

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

D latch versus D flip-flop
The D latch is used to capture, or ``latch'' the logic level which is
present on the Data line when the clock input is high
...
The positive edge
triggered D flip-flop is used to capture the logic level which is
present on the Data line on the rising edge of the clock pulse

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Edge triggered SR flip-flop

Logic diagram of edge triggered SR flip-flop
Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Search
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...

When the clock goes low, Q remains unchanged
...
For a D latch, it would be the level 1
...


Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Serial-in serial-out (SISO) shift register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Serial-in serial-out (SISO) shift register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

SISO Shift Register

3 bit SISO shift register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Serial-In to Parallel-Out (SIPO) shift register

4-bit serial-in to parallel-out (SIPO) shift register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

4-bit Parallel-in/Parallel-out (PIPO) Shift Register

4-bit Parallel-in/Parallel-out (PIPO) Shift Register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Parallel in Serial out (PISO) Shift Register

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Ripple or Asynchronous counter

Each bit in this four-bit sequence toggles
when the bit before it (the bit having a lesser
significance, or place-weight), toggles from 1
to 0

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Ripple or Asynchronous counter

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Ripple or Asynchronous counter

Alternate method of realizing 4-bit ripple or
asynchronous counter
Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Ripple or Asynchronous counter

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Ripple or Asynchronous counter
REVIEW:

An "up" counter may be made by connecting the clock inputs of
positive-edge triggered J-K flip-flops to the Q' outputs of the
preceding flip-flops
...
In either case, the J and K inputs of all flipflops are connected to Vcc or Vdd so as to always be "high”
...
These types of counter circuits are called
asynchronous counters, or ripple counters
...
K-map, maxterm simplification

Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Problems on K-map
P2
...


Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Problems on K-map
P3
...


Department of Electronics and Communication Engineering,
Manipal Institute of Technology, Manipal, INDIA

Problems on K-map
P4

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