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Digital Design
With an Introduction to the Verilog HDL

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Digital Design
With an Introduction to the Verilog HDL

FIFTH EDITION

M
...
Ciletti
Emeritus Professor of Electrical and Computer Engineering
University of Colorado at Colorado Springs

Upper Saddle River Boston Columbus San Franciso New York
Indianapolis London Toronto Sydney Singapore Tokyo Montreal
Dubai Madrid Hong Kong Mexico City Munich Paris Amsterdam Cape Town

Vice President and Editorial Director, ECS:
Marcia J
...
Ciletti
Composition: Jouve India Private Limited
Full-Service Project Management: Jouve India Private
Limited
Printer/Binder: Edwards Brothers
Typeface: Times Ten 10/12

Copyright © 2013, 2007, 2002, 1991, 1984 Pearson Education, Inc
...
All rights reserved
...
This publication is
protected by Copyright, and permission should be obtained from the publisher prior to any prohibited reproduction,
storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying,
recording, or likewise
...
, Permissions Department, One Lake Street, Upper Saddle River, New Jersey 07458
...
Where
those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been
printed in initial caps or all caps
...
No part of this book may be reproduced, in any form or by any means, without permission in writing
from the publisher
...
, Blacksburg, VA 24062–0608
...
These efforts include the
development, research, and testing of the theories and programs to determine their effectiveness
...
The author and publisher shall not be liable in any event for incidental or consequential
damages in connection with, or arising out of, the furnishing, performance, or use of these programs
...
Photograph courtesy of mdc
Images, LLC (www
...
com)
...

Library of Congress Cataloging-in-Publication Data
Mano, M
...
Morris Mano, Michael D
...
—5th ed
...
cm
...

ISBN-13: 978-0-13-277420-8
ISBN-10: 0-13-277420-8
1
...
2
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3
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4
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 I
...
II
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TK7888
...
M343 2011
621
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1
1
...
3
1
...
5
1
...
7
1
...
9

2

ix

Digital Systems
Binary Numbers
Number‐Base Conversions
Octal and Hexadecimal Numbers
Complements of Numbers
Signed Binary Numbers
Binary Codes
Binary Storage and Registers
Binary Logic

1
1
3
6
8
10
14
18
27
30

Boolean Algebra and Logic Gates
2
...
2
2
...
4
2
...
6
2
...
8
2
...
1
3
...
3
3
...
5
3
...
7
3
...
9

4

Introduction
Combinational Circuits
Analysis Procedure
Design Procedure
Binary Adder–Subtractor
Decimal Adder
Binary Multiplier
Magnitude Comparator
Decoders
Encoders
Multiplexers
HDL Models of Combinational Circuits

125
125
125
126
129
133
144
146
148
150
155
158
164

Synchronous Sequential Logic
5
...
2
5
...
4
5
...
6
5
...
8

6

73
73
80
84
88
90
97
103
108

Combinational Logic
4
...
2
4
...
4
4
...
6
4
...
8
4
...
10
4
...
12

5

Introduction
The Map Method
Four‐Variable K-Map
Product‐of‐Sums Simplification
Don’t‐Care Conditions
NAND and NOR Implementation
Other Two‐Level Implementations
Exclusive‐OR Function
Hardware Description Language

73

Introduction
Sequential Circuits
Storage Elements: Latches
Storage Elements: Flip‐Flops
Analysis of Clocked Sequential Circuits
Synthesizable HDL Models of Sequential Circuits
State Reduction and Assignment
Design Procedure

190
190
190
193
196
204
217
231
236

Registers and Counters
6
...
2
6
...
4
6
...
6

Registers
Shift Registers
Ripple Counters
Synchronous Counters
Other Counters
HDL for Registers and Counters

255
255
258
266
271
278
283

Contents

7

Memory and Programmable Logic
7
...
2
7
...
4
7
...
6
7
...
8

8

299
299
300
307
312
315
321
325
329

Design at the Register
Tr a n s f e r L e v e l
8
...
2
8
...
4
8
...
6
8
...
8
8
...
10
8
...
12
8
...
1
9
...
3
9
...
5
9
...
7
9
...
9
9
...
11
9
...
13
9
...
15

Introduction to Experiments
Experiment 1: Binary and Decimal Numbers
Experiment 2: Digital Logic Gates
Experiment 3: Simplification of Boolean Functions
Experiment 4: Combinational Circuits
Experiment 5: Code Converters
Experiment 6: Design with Multiplexers
Experiment 7: Adders and Subtractors
Experiment 8: Flip‐Flops
Experiment 9: Sequential Circuits
Experiment 10: Counters
Experiment 11: Shift Registers
Experiment 12: Serial Addition
Experiment 13: Memory Unit
Experiment 14: Lamp Handball

vii

438
438
443
446
448
450
452
453
455
457
460
461
463
466
467
469

viii

Contents
9
...
17
9
...
19

10

Experiment 15: Clock‐Pulse Generator
Experiment 16: Parallel Adder and Accumulator
Experiment 17: Binary Multiplier
Verilog HDL Simulation Experiments
and Rapid Prototyping with FPGAs

473
475
478
480

Standard Graphic Symbols
10
...
2
10
...
4
10
...
6
10
...
8

Rectangular‐Shape Symbols
Qualifying Symbols
Dependency Notation
Symbols for Combinational Elements
Symbols for Flip‐Flops
Symbols for Registers
Symbols for Counters
Symbol for RAM

488
488
491
493
495
497
499
502
504

Appendix

507

Answers to Selected Problems

521

Index

539

Preface

Since the fourth edition of Digital Design, the commercial availability of devices using
digital technology to receive, manipulate, and transmit information seems to have
exploded
...
Underneath the attractive graphical user interface of all of these
devices sits a digital system that processes data in a binary format
...
Consequently, our refinement of our text has been guided by the need to equip our graduates with a solid understanding of digital machines and to introduce them to the
methodology of modern design
...
The focus of
the text has been sharpened to more closely reflect the content of a foundation course
in digital design and the mainstream technology of today’s digital systems: CMOS
circuits
...
The key elements that the book focuses
include (1) Boolean logic, (2) logic gates used by designers, (3) synchronous finite state
machines, and (4) datapath controller design—all from a perspective of designing digital systems
...
So the reader will not find here content for asynchronous machines or
descriptions of bipolar transistors
...
Today’s designers rely heavily on hardware description languages
ix

x

Preface
(HDLs), and this edition of the book gives greater attention to their use and presents
what we think is a clear development of a design methodology using the Verilog HDL
...
The so‐called VARK characterization of learning modalities identifies four major modes by which humans learn:
(V) visual, (A) aural, (R) reading, and (K) kinesthetic
...
Students who exploit the availability of free simulators to work assignments
are led through a kinesthetic (K) learning experience, including the positive feedback
and delight of designing a logic system that works
...
We have provided an abundance
of material and examples to support classroom lectures
...

For those who might still question the presentation and use of HDLs in a first course
in digital design, we note that industry has largely abandoned schematic‐based design
entry, a style which emerged in the 1980s, during the nascent development of CAD tools
for integrated circuit (IC) design
...
Unfortunately, it is difficult for anyone
in a reasonable amount of time to determine the functionality represented by the schematic of a logic circuit without having been instrumental in its construction, or without
having additional documentation expressing the design intent
...
g
...
The utility of a
schematic depends on the careful, detailed documentation of a carefully constructed
hierarchy of design modules
...
In today’s design
flow, designers using HDLs can express functionality directly and explicitly, without years
of accumulated experience, and use synthesis tools to generate the schematic as a by‐
product, automatically
...

We note, again in this edition, that introducing HDLs in a first course in designing
digital circuits is not intended to replace fundamental understanding of the building blocks
of such circuits or to eliminate a discussion of manual methods of design
...
Thus, we retain a thorough treatment of
combinational and sequential logic devices
...
What we are
presenting, however, is an emphasis on how hardware is designed, to better prepare a
student for a career in today’s industry, where HDL‐based design practices are dominant
...
Because modern
synthesis tools automatically perform logic minimization, Karnaugh maps and related
topics in optimization can be presented at the beginning of a treatment of digital design,
or they can be presented after circuits and their applications are examined and simulated
with an HDL
...
Our end‐
of‐chapter problems further facilitate this flexibility by cross referencing problems that
address a traditional manual design task with a companion problem that uses an HDL
to accomplish the task
...


NEW TO THIS EDITION
This edition of Digital Design uses the latest features of IEEE Standard 1364, but only
insofar as they support our pedagogical objectives
...
g
...
Moreover, the framework in which this material is presented treats the realistic situation in which status signals from the datapath are used by
the controller, i
...
, the system has feedback
...
Although it is presented with an
emphasis on HDL‐based design, the methodology is also applicable to manual‐based
approaches to design
...
Also, correct syntax does not guarantee that a model meets a functional
specification or that it can be synthesized into physical hardware
...
Failure to follow
this discipline can lead to software race conditions in the HDL models of such machines,
race conditions in the test bench used to verify them, and a mismatch between the results
of simulating a behavioral model and its synthesized physical counterpart
...
The industry‐based methodology we present
leads to race‐free and latch‐free designs
...


V E R I F I C AT I O N
In industry, significant effort is expended to verify that the functionality of a circuit is
correct
...
Our experience is that this view can lead to premature “high‐fives” and
declarations that “the circuit works beautifully
...

We demonstrate naming practices and the use of parameters to facilitate reusability and
portability
...
Advocating and illustrating the development of a test plan to guide the development of a test
bench, we introduce test plans, albeit simply, in the text and expand them in the solutions
manual and in the answers to selected problems at the end of the text
...
As in the previous edition, HDL material is inserted in separate sections so that it can be covered or
skipped as desired, does not diminish treatment of manual‐based design, and does not
dictate the sequence of presentation
...
The text prepares

Preface

xiii

students to work on signficant independent design projects and to succeed in a later
course in computer architecture and advanced digital design
...
pearsonhighered
...
The first simulator is VeriLogger Pro, a traditional Verilog simulator that can be
used to simulate the HDL examples in the book and to verify the solutions of HDL
problems
...
As an interactive simulator, Verilogger Extreme accepts the syntax of IEEE‐2001 as well as IEEE‐1995, allowing the designer to
simulate and analyze design ideas before a complete simulation model or schematic is
available
...
Students can access the Companion Website
at www
...
com/mano
...

Chapter 1 presents the various binary systems suitable for representing information
in digital systems
...
Examples are given for addition and subtraction of signed binary numbers and
decimal numbers in binary‐coded decimal (BCD) format
...
All possible
logic operations for two variables are investigated, and the most useful logic gates used
in the design of digital systems are identified
...

Chapter 3 covers the map method for simplifying Boolean expressions
...
All other possible two‐level gate circuits are considered, and their method
of implementation is explained
...


xiv

Preface
Chapter 4 outlines the formal procedures for the analysis and design of combinational circuits
...
Frequently used digital
logic functions such as parallel adders and subtractors, decoders, encoders, and multiplexers are explained, and their use in the design of combinational circuits is illustrated
...
The
procedure for writing a simple test bench to provide stimulus to an HDL design is
presented
...
The gate structure of several types of flip‐flops is presented
together with a discussion on the difference between level and edge triggering
...
A number of design examples are presented with emphasis on sequential circuits that use D‐type flip‐flops
...
HDL Examples are given to illustrate Mealy and
Moore models of sequential circuits
...
These digital components are the basic building blocks from
which more complex digital systems are constructed
...

Chapter 7 deals with random access memory (RAM) and programmable logic
devices
...
Combinational
and sequential programmable devices such as ROMs, PLAs, PALs, CPLDs, and FPGAs
are presented
...
The algorithmic state machine (ASM) chart is introduced
...
The design of a finite state machine to control a datapath is presented in detail, including the realistic situation in which status
signals from the datapath are used by the state machine that controls it
...

Chapter 9 outlines experiments that can be performed in the laboratory with hardware that is readily available commercially
...
Each experiment is presented informally and the student is
expected to design the circuit and formulate a procedure for checking its operation
in the laboratory
...
Today, software for synthesizing
an HDL model and implementing a circuit with an FPGA is available at no cost from
vendors of FPGAs, allowing students to conduct a significant amount of work in their
personal environment before using prototyping boards and other resources in a lab
...
With these resources, students can work prescribed lab
exercises or their own projects and get results immediately
...
These graphic symbols have been developed for small‐scale
integration (SSI) and medium‐scale integration (MSI) components so that the user can
recognize each function from the unique graphic symbol assigned
...


ACKNOWLEDGMENTS
We are grateful to the reviewers of Digital Design, 5e
...

Dmitri Donetski, Stony Brook University
Ali Amini, California State University, Northridge
Mihaela Radu, Rose Hulman Institute of Technology
Stephen J Kuyath, University of North Carolina, Charlotte
Peter Pachowicz, George Mason University
David Jeff Jackson, University of Alabama
A
...
Robinson, Vanderbilt University
Dinesh Bhatia, University of Texas, Dallas
We also wish to express our gratitude to the editorial and publication team at Prentice
Hall/Pearson Education for supporting this edition of our text
...

M
...
Ciletti
Emeritus Professor of Electrical and Computer Engineering
University of Colorado at Colorado Springs

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Chapter 1

Digital Systems and Binary Numbers

1
...
Digital systems are used in communication, business transactions, traffic control, spacecraft guidance, medical treatment, weather monitoring, the Internet, and many other commercial, industrial, and scientific enterprises
...
We enjoy music downloaded to our
portable media player (e
...
, iPod Touch™) and other handheld devices having high‐
resolution displays
...
Most, if not all,
of these devices have a special‐purpose digital computer embedded within them
...
It can follow a sequence
of instructions, called a program, that operates on given data
...
Because of this flexibility, general‐purpose digital computers can perform a variety of information‐processing
tasks that range over a wide spectrum of applications
...
Any set that is restricted to a finite number of elements
contains discrete information
...
Early
digital computers were used for numeric computations
...
From this application, the term digital computer emerged
...
Electrical signals such as voltages and currents are the most common
...
The signals in most present‐day electronic digital systems use just two discrete
values and are therefore said to be binary
...
Discrete elements of information are represented with groups of bits called binary
codes
...
g
...
How a pattern of
bits is interpreted as a number depends on the code system in which it resides
...

Then 01112 = 710, which is not the same as 011110, or one hundred eleven
...
Through various techniques, groups of bits can be made to represent discrete
symbols, not necessarily numbers, which are then used to develop the system in a digital
format
...
In today’s technology, binary systems are most
practical because, as we will see, they can be implemented with electronic components
...
On the one hand, a payroll
schedule is an inherently discrete process that contains employee names, social security
numbers, weekly salaries, income taxes, and so on
...
On the other hand, a research scientist may observe a
continuous process, but record only specific quantities in tabular form
...
In many cases, the quantization of a process can be performed automatically
by an analog‐to‐digital converter, a device that forms a digital (discrete) representation
of a analog (continuous) quantity
...

The major parts of a computer are a memory unit, a central processing unit, and input–
output units
...
The central processing unit performs arithmetic and other data‐processing
operations as specified by the program
...
An output
device, such as a printer, receives the results of the computations, and the printed results
are presented to the user
...
One very useful device is a communication unit that provides interaction with
other users through the Internet
...
In addition, it can
be programmed to make decisions based on internal and external conditions
...
Like a digital computer, most digital devices are programmable
...
Dramatic cost reductions in digital devices have come about

Section 1
...
As the number of transistors
that can be put on a piece of silicon increases to produce complex functions, the cost per
unit decreases and digital devices can be bought at an increasingly reduced price
...
Digital systems can be made to operate with extreme reliability by using error‐correcting codes
...
Digital information on a DVD is recorded
in such a way that, by examining the code in each digital sample before it is played back,
any error can be automatically identified and corrected
...
To understand the operation of each digital module, it is necessary to have a basic knowledge of digital circuits
and their logical function
...
Chapter 8 introduces digital design at the register transfer
level (RTL) using a modern hardware description language (HDL)
...

A major trend in digital design methodology is the use of a HDL to describe and simulate
the functionality of a digital circuit
...
It is used to simulate a digital system
to verify its operation before hardware is built
...
Because it is important that students become
familiar with an HDL‐based design methodology, HDL descriptions of digital circuits are
presented throughout the book
...
Ignorance of
these practices will lead to cute, but worthless, HDL models that may simulate a phenomenon, but that cannot be synthesized by design tools, or to models that waste silicon area or
synthesize to hardware that cannot operate correctly
...
Operands used for calculations may be expressed
in the binary number system
...
Digital circuits, also referred
to as logic circuits, process data by means of binary logic elements (logic gates) using
binary signals
...

The purpose of this chapter is to introduce the various binary concepts as a frame of
reference for further study in the succeeding chapters
...
2

BINARY NUMBERS
A decimal number such as 7,392 represents a quantity equal to 7 thousands, plus 3 hundreds, plus 9 tens, plus 2 units
...
, are powers of 10 implied
by the position of the coefficients (symbols) in the number
...
In
general, a number with a decimal point is represented by a series of coefficients:
a5a4a3a2a1a0
...

Thus, the preceding decimal number can be expressed as
105a5 + 104a4 + 103a3 + 102a2 + 101a1 + 100a0 + 10-1a-1 + 10-2a-2 + 10-3a-3
with a3 = 7, a2 = 3, a1 = 9, and a0 = 2
...
The binary system is a different
number system
...
Each coefficient aj is multiplied by a power of the radix, e
...
, 2j, and
the results are added to obtain the decimal equivalent of the number
...
g
...
For example, the decimal equivalent of the binary
number 11010
...
75, as shown from the multiplication of the coefficients by
powers of 2:
1 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 0 * 20 + 1 * 2-1 + 1 * 2-2 = 26
...
In general, a number expressed in a base‐r
system has coefficients multiplied by powers of r:
an # r n + an - 1 # r n - 1 + g + a2 # r 2 + a1 # r + a0 + a-1 # r-1
+ a-2 # r-2 + g + a-m # r-m
The coefficients aj range in value from 0 to r - 1
...
An example of a base‐5 number is
(4021
...
4)10
The coefficient values for base 5 can be only 0, 1, 2, 3, and 4
...
An example of an octal number
is 127
...
To determine its equivalent decimal value, we expand the number in a power
series with a base of 8:
(127
...
5)10
Note that the digits 8 and 9 cannot appear in an octal number
...
The letters of the alphabet are used
to supplement the 10 decimal digits when the base of the number is greater than 10
...
2

Binary Numbers

5

from the decimal system
...
An example of a hexadecimal number is
(B65F)16 = 11 * 163 + 6 * 162 + 5 * 161 + 15 * 160 = (46,687)10
The hexadecimal system is used commonly by designers to represent long strings of bits
in the addresses, instructions, and data in digital systems
...

As noted before, the digits in a binary number are called bits
...
Therefore, the conversion
from binary to decimal can be obtained by adding only the numbers with powers of two
corresponding to the bits that are equal to 1
...
The corresponding decimal number is the sum
of the four powers of two
...
1
...
Thus, 4K = 212 = 4,096 and 16M = 224 = 16,777,216
...
A byte is equal to eight bits and can accommodate (i
...
, represent the code of) one keyboard character
...

A terabyte is 1024 gigabytes, approximately 1 trillion bytes
...
When a base other than the familiar base 10 is used, one must be careful to
use only the r‐allowable digits
...
1
Powers of Two
n

2n

n

2n

n

2n

0
1
2
3
4
5
6
7

1
2
4
8
16
32
64
128

8
9
10
11
12
13
14
15

256
512
1,024 (1K)
2,048
4,096 (4K)
8,192
16,384
32,768

16
17
18
19
20
21
22
23

65,536
131,072
262,144
524,288
1,048,576 (1M)
2,097
,152
4,194,304
8,388,608

1011
* 101
1011
0000  
1011   
110111

6

Chapter 1

Digital Systems and Binary Numbers

The sum of two binary numbers is calculated by the same rules as in decimal, except
that the digits of the sum in any significant position can be only 0 or 1
...
Subtraction is slightly more complicated
...

(A borrow in the decimal system adds 10 to a minuend digit
...


1
...
For example, (0011)8 and (1001)2 are equivalent—both
have decimal value 9
...

We now present a general procedure for the reverse operation of converting a decimal
number to a number in base r
...
The conversion of a decimal integer to a number in base r is done
by dividing the number and all successive quotients by r and accumulating the remainders
...


EXAMPLE 1
...
First, 41 is divided by 2 to give an integer quotient of 20
and a remainder of 1
...
The process is continued until the integer quotient becomes 0
...


Section 1
...

■

EXAMPLE 1
...
The required base r is 8
...
Then 19 is divided by 8 to give an integer
quotient of 2 and a remainder of 3
...
This process can be conveniently manipulated as follows:
153
19

1

2

3

0

2 = (231)8

The conversion of a decimal fraction to binary is accomplished by a method similar
to that used for integers
...
Again, the method is best explained by example
...
3
Convert (0
...
First, 0
...

Then the new fraction is multiplied by 2 to give a new integer and a new fraction
...
The coefficients of the binary number are obtained from the integers as follows:
Integer

Fraction

Coefficient

0
...
3750

a-1 = 1

0
...
7500

a-2 = 0

0
...
5000

a-3 = 1

0
...
0000

a-4 = 1

8

Chapter 1

Digital Systems and Binary Numbers

Therefore, the answer is (0
...
a-1 a-2 a-3 a-4)2 = (0
...

To convert a decimal fraction to a number expressed in base r, a similar procedure is
used
...

■

EXAMPLE 1
...
513)10 to octal
...
513
0
...
832
0
...
248
0
...
104
0
...
656
5
...
984
7
...
513)10 = (0
...

Using the results of Examples 1
...
3, we obtain
(41
...
1011)2
From Examples 1
...
4, we have
(153
...
406517)8
■

1
...
Since 23 = 8 and 24 = 16, each octal digit corresponds to three
binary digits and each hexadecimal digit corresponds to four binary digits
...
2
...
The corresponding octal digit is then assigned to each group
...
7406)8
6

Section 1
...
2
Numbers with Different Bases
Decimal
(base 10)

Binary
(base 2)

Octal
(base 8)

Hexadecimal
(base 16)

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

Conversion from binary to hexadecimal is similar, except that the binary number is
divided into groups of four digits:
(10
2

1100
C

0110
6

1011
B

#

1111
F

0010)2 = (2C6B
...
2
...
Each octal digit is converted to its three‐digit binary equivalent
...
The procedure is
illustrated in the following examples:
(673
...
D)16 = (0011
3

0000
0

0110
6

#

1101)2
D

Binary numbers are difficult to work with because they require three or four times
as many digits as their decimal equivalents
...
However, digital computers use binary numbers, and it is
sometimes necessary for the human operator or user to communicate directly with the

10

Chapter 1

Digital Systems and Binary Numbers

machine by means of such numbers
...
By this
method, the human thinks in terms of octal or hexadecimal numbers and performs the
required conversion by inspection when direct communication with the machine is necessary
...
During communication between
people (about binary numbers in the computer), the octal or hexadecimal representation is more desirable because it can be expressed more compactly with a third or a
quarter of the number of digits required for the equivalent binary number
...

The choice between them is arbitrary, although hexadecimal tends to win out, since it
can represent a byte with two digits
...
5

COMPLEMENTS OF NUMBERS
Complements are used in digital computers to simplify the subtraction operation and for
logical manipulation
...
There are two types of complements for each base‐r system:
the radix complement and the diminished radix complement
...
When the value of the
base r is substituted in the name, the two types are referred to as the 2’s complement and
1’s complement for binary numbers and the 10’s complement and 9’s complement for
decimal numbers
...
e
...
For decimal numbers, r = 10
and r - 1 = 9, so the 9’s complement of N is (10 n - 1) - N
...
10 n - 1 is a number represented
by n 9’s
...
It follows
that the 9’s complement of a decimal number is obtained by subtracting each digit from 9
...

The 9>s complement of 012398 is 999999 - 012398 = 987601
...

Again, 2n is represented by a binary number that consists of a 1 followed by n 0’s
...
For example, if n = 4, we have 24 = (10000)2
and 24 - 1 = (1111)2
...
However, when subtracting binary digits from 1, we can

Section 1
...
Therefore, the 1’s complement of a binary number is formed by
changing 1’s to 0’s and 0’s to 1’s
...

The 1’s complement of 0101101 is 1010010
...


Radix Complement
The r’s complement of an n‐digit number N in base r is defined as r n - N for N ϶ 0 and
as 0 for N = 0
...

Thus, the 10’s complement of decimal 2389 is 7610 + 1 = 7611 and is obtained by adding
1 to the 9’s complement value
...

Since 10 is a number represented by a 1 followed by n 0’s, 10 n - N, which is the 10’s
complement of N, can be formed also by leaving all least significant 0’s unchanged,
subtracting the first nonzero least significant digit from 10, and subtracting all higher
significant digits from 9
...
The 10’s complement of the
second number is obtained by leaving the two least significant 0’s unchanged, subtracting 7 from 10, and subtracting the other three digits from 9
...
For example,
the 2’s complement of 1101100 is 0010100
and
the 2’s complement of 0110111 is 1001001
The 2’s complement of the first number is obtained by leaving the two least significant
0’s and the first 1 unchanged and then replacing 1’s with 0’s and 0’s with 1’s in the other
four most significant digits
...


12

Chapter 1

Digital Systems and Binary Numbers

In the previous definitions, it was assumed that the numbers did not have a radix point
...
The radix point is then restored to the
complemented number in the same relative position
...
To see this
relationship, note that the r’s complement of N is r n - N, so that the complement of the
complement is r n - (r n - N) = N and is equal to the original number
...

In this method, we borrow a 1 from a higher significant position when the minuend digit
is smaller than the subtrahend digit
...
However, when subtraction is implemented with digital
hardware, the method is less efficient than the method that uses complements
...
Add the minuend M to the r’s complement of the subtrahend N
...

2
...

3
...
To obtain the answer in a familiar form,
take the r’s complement of the sum and place a negative sign in front
...
5
Using 10’s complement, subtract 72532 - 3250
...
Both numbers must have the same
number of digits, so we write N as 03250
...
The occurrence of the end carry signifies that M Ú N
and that the result is therefore positive
...
5

Complements of Numbers

13

EXAMPLE 1
...

M = 03250
10>s complement of N = + 27468
Sum = 30718
There is no end carry
...

Note that since 3250 6 72532, the result is negative
...
When
subtracting with complements, we recognize the negative answer from the absence
of the end carry and the complemented result
...

Subtraction with complements is done with binary numbers in a similar manner, using
the procedure outlined previously
...
7
Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X by using 2’s complements
...
Therefore, the answer is Y - X = -(2>s complement of 1101111) =
-0010001
...
Remember that the (r - 1)>s complement is one less than the r’s complement
...
Removing the end carry and adding 1 to the sum is referred to as an
end‐around carry
...
8
Repeat Example 1
...

(a) X - Y = 1010100 - 1000011
X
1>s complement of Y
Sum
End@around carry
Answer: X - Y

=
1010100
= + 0111100
=
10010000
= +
1
=
0010001

(b) Y - X = 1000011 - 1010100
Y =
1000011
1>s complement of X = + 0101011
Sum =
1101110
There is no end carry
...

■
Note that the negative result is obtained by taking the 1’s complement of the sum, since
this is the type of complement used
...


1
...
However, to
represent negative integers, we need a notation for negative values
...
Because of hardware limitations, computers must represent everything with binary
digits
...
The convention is to make the sign bit 0 for positive and 1 for negative
...
The user determines whether the number
is signed or unsigned
...
If the binary number is assumed to
be unsigned, then the leftmost bit is the most significant bit of the number
...
The string of bits 11001 represents the binary equivalent of
25 when considered as an unsigned number and the binary equivalent of -9 when considered as a signed number
...
Usually, there is no confusion in
interpreting the bits if the type of representation for the number is known in advance
...
6

Signed Binary Numbers

15

The representation of the signed numbers in the last example is referred to as the
signed‐magnitude convention
...
This is the representation of signed
numbers used in ordinary arithmetic
...
In this system, a negative number is indicated by its complement
...
Since positive numbers always start with 0 (plus) in the leftmost position, the complement will always start with a 1, indicating a negative number
...

As an example, consider the number 9, represented in binary with eight bits
...
Note that all eight bits must have a value; therefore, 0’s
are inserted following the sign bit up to the first 1
...
In signed‐1’s-complement, -9 is obtained by complementing all the
bits of +9, including the sign bit
...

Table 1
...

The equivalent decimal number is also shown for reference
...
The
signed‐2’s‐complement system has only one representation for 0, which is always positive
...
Note that all negative numbers have a 1 in the
leftmost bit position; that is the way we distinguish them from the positive numbers
...
In the signed‐magnitude and the
1’s‐complement representations, there are eight positive numbers and eight negative
numbers, including two zeros
...

The signed‐magnitude system is used in ordinary arithmetic, but is awkward when
employed in computer arithmetic because of the separate handling of the sign and the
magnitude
...
The 1’s complement imposes some difficulties and is seldom used for arithmetic operations
...
The discussion of
signed binary arithmetic that follows deals exclusively with the signed‐2’s‐complement

16

Chapter 1

Digital Systems and Binary Numbers

Table 1
...
The same procedures can be applied to the
signed‐1’s‐complement system by including the end‐around carry as is done with
unsigned numbers
...
If the signs are the same, we add the two magnitudes and give
the sum the common sign
...
For
example, ( +25) + ( -37) = -(37 - 25) = -12 is done by subtracting the smaller magnitude, 25, from the larger magnitude, 37, and appending the sign of 37 to the result
...
The same procedure applies to binary numbers
in signed‐magnitude representation
...
The procedure is very simple and can be stated as follows for binary numbers:
The addition of two signed binary numbers with negative numbers represented in
signed‐2’s‐complement form is obtained from the addition of the two numbers, including their sign bits
...


Section 1
...
For example, -7 is
represented as 11111001, which is the 2s complement of +7
...
Any carry out of the sign‐bit position is discarded, and negative results are
automatically in 2’s‐complement form
...
If we start with two n‐bit numbers and the sum
occupies n + 1 bits, we say that an overflow occurs
...
We just add another 0 to a positive number or another 1 to a negative number
in the most significant position to extend the number to n + 1 bits and then perform the
addition
...

The complement form of representing negative numbers is unfamiliar to those used
to the signed‐magnitude system
...
For example, the signed binary number 11111001 is negative because
the leftmost bit is 1
...
We therefore recognize the original negative number to be equal to -7
...
A carry out of the sign‐bit position is discarded
...

But changing a positive number to a negative number is easily done by taking the 2’s
complement of the positive number
...
To
see this, consider the subtraction ( -6) - ( -13) = +7
...
The subtraction is changed to addition
by taking the 2’s complement of the subtrahend (-13), giving (+13)
...
Removing the end carry, we obtain the correct
answer: 00000111 ( +7)
...

Therefore, computers need only one common hardware circuit to handle both types of
arithmetic
...
The user or programmer must
interpret the results of such addition or subtraction differently, depending on whether
it is assumed that the numbers are signed or unsigned
...
7

BINARY CODES
Digital systems use signals that have two distinct values and circuit elements that
have two stable states
...
A binary number of n digits, for example, may be represented by n binary circuit elements, each having an output signal equivalent to 0 or 1
...
Any discrete element of information that is
distinct among a group of quantities can be represented with a binary code (i
...
, a
pattern of 0’s and 1’s)
...
However, it must be realized that binary
codes merely change the symbols, not the meaning of the elements of information
that they represent
...

An n‐bit binary code is a group of n bits that assumes up to 2n distinct combinations
of 1’s and 0’s, with each combination representing one element of the set that is being
coded
...
A set of eight elements requires a
three‐bit code and a set of 16 elements requires a four‐bit code
...
Each element
must be assigned a unique binary bit combination, and no two elements can have the
same value; otherwise, the code assignment will be ambiguous
...
For example,
the 10 decimal digits can be coded with 10 bits, and each decimal digit can be assigned
a bit combination of nine 0’s and a 1
...


Section 1
...
One way to resolve this difference is to convert decimal
numbers to binary, perform all arithmetic calculations in binary, and then convert the
binary results back to decimal
...
Since the computer can accept
only binary values, we must represent the decimal digits by means of a code that contains
1’s and 0’s
...

A binary code will have some unassigned bit combinations if the number of elements
in the set is not a multiple power of 2
...
A binary
code that distinguishes among 10 elements must contain at least four bits, but 6 out of
the 16 possible combinations remain unassigned
...
The code most commonly used for
the decimal digits is the straight binary assignment listed in Table 1
...
This scheme is
called binary‐coded decimal and is commonly referred to as BCD
...

Table 1
...
A number with k decimal
digits will require 4k bits in BCD
...
A decimal
number in BCD is the same as its equivalent binary number only when the number is
between 0 and 9
...
Moreover, the binary combinations 1010 through 1111 are not used and have no meaning in BCD
...
4
Binary‐Coded Decimal (BCD)
Decimal
Symbol

BCD
Digit

0
1
2
3
4
5
6
7
8
9

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

20

Chapter 1

Digital Systems and Binary Numbers

The BCD value has 12 bits to encode the characters of the decimal value, but the equivalent binary number needs only 8 bits
...
However, there is an advantage
in the use of decimal numbers, because computer input and output data are generated
by people who use the decimal system
...
The only difference between a
decimal number and BCD is that decimals are written with the symbols 0, 1, 2, c , 9
and BCD numbers use the binary code 0000, 0001, 0010, c , 1001
...
Decimal 10 is represented in BCD with eight bits as 0001 0000 and
decimal 15 as 0001 0101
...


BCD Addition
Consider the addition of two decimal digits in BCD, together with a possible carry
from a previous less significant pair of digits
...
Suppose we add the BCD digits as if they were binary numbers
...
In binary, this range will be from 0000 to
10011, but in BCD, it is from 0000 to 1 1001, with the first (i
...
, leftmost) 1 being a
carry and the next four bits being the BCD sum
...
However,
when the binary sum is greater than or equal to 1010, the result is an invalid BCD
digit
...
This is because a carry in the most significant bit
position of the binary sum and a decimal carry differ by 16 - 10 = 6
...
If the
binary sum is greater than or equal to 1010, we add 0110 to obtain the correct BCD sum
and a carry
...
In
the second example, the binary sum produces an invalid BCD digit
...
e
...
In the third
example, the binary sum produces a carry
...
Although the other four bits are less than 1001, the binary sum
requires a correction because of the carry
...
e
...


Section 1
...

Consider the addition of 184 + 576 = 760 in BCD:
BCD

Binary sum
Add 6
BCD sum

1
0001
+0101
0111
0111

1
1000
0111
10000
0110
0110

0100
0110
1010
0110
0000

184
+576

760

The first, least significant pair of BCD digits produces a BCD digit sum of 0000 and a
carry for the next pair of digits
...
The third pair of
digits plus a carry produces a binary sum of 0111 and does not require a correction
...
We can use either the familiar signed‐magnitude system or
the signed‐complement system
...
It is customary to
designate a plus with four 0’s and a minus with the BCD equivalent of 9, which is 1001
...
The signed‐complement
system can be either the 9’s or the 10’s complement, but the 10’s complement is the one
most often used
...
The 9’s complement is calculated from the subtraction of each digit from 9
...
Addition
is done by summing all digits, including the sign digit, and discarding the end carry
...
Consider the
addition ( +375) + ( -240) = +135, done in the signed‐complement system:
0 375
+9 760
0 135
The 9 in the leftmost position of the second number represents a minus, and 9760 is
the 10’s complement of 0240
...
Of course, the decimal numbers inside the computer, including
the sign digits, must be in BCD
...

The subtraction of decimal numbers, either unsigned or in the signed‐10’s‐complement
system, is the same as in the binary case: Take the 10’s complement of the subtrahend and
add it to the minuend
...
The user of the computer can specify
programmed instructions to perform the arithmetic operation with decimal numbers
directly, without having to convert them to binary
...
Many different
codes can be formulated by arranging four bits into 10 distinct combinations
...
5
...
The other six unused
combinations have no meaning and should be avoided
...
In a weighted code, each bit
position is assigned a weighting factor in such a way that each digit can be evaluated by
adding the weights of all the 1’s in the coded combination
...
The bit assignment 0110, for example, is interpreted by the weights to represent decimal 6 because
8 * 0 + 4 * 1 + 2 * 1 + 1 * 0 = 6
...

Note that some digits can be coded in two possible ways in the 2421 code
...


Table 1
...
7

Binary Codes

23

BCD adders add BCD values directly, digit by digit, without converting the numbers
to binary
...
BCD
adders require significantly more hardware and no longer have a speed advantage of
conventional binary adders [5]
...
Such
codes have the property that the 9’s complement of a decimal number is obtained
directly by changing 1’s to 0’s and 0’s to 1’s (i
...
, by complementing each bit in the pattern)
...

The 9’s complement of 604 is represented as 1001 0011 0111, which is obtained simply
by complementing each bit of the code (as with the 1’s complement of binary numbers)
...
Excess‐3 is an unweighted code in which each coded combination is obtained from the corresponding binary value plus 3
...

The 8, 4, -2, -1 code is an example of assigning both positive and negative weights
to a decimal code
...


Gray Code
The output data of many physical systems are quantities that are continuous
...

Continuous or analog information is converted into digital form by means of an analog‐to‐digital converter
...
6 to represent digital data that have been converted from analog data
...
For example,
in going from 7 to 8, the Gray code changes from 0100 to 1100
...
By contrast, with binary
numbers the change from 7 to 8 will be from 0111 to 1000, which causes all four bits
to change values
...
If binary numbers are used, a change, for example, from 0111 to
1000 may produce an intermediate erroneous number 1001 if the value of the rightmost
bit takes longer to change than do the values of the other three bits
...
The Gray code eliminates this
problem, since only one bit changes its value during any transition between two numbers
...
The shaft is partitioned into segments,
and each segment is assigned a number
...


24

Chapter 1

Digital Systems and Binary Numbers
Table 1
...
For instance,
consider a high‐tech company with thousands of employees
...
In addition, the same binary code must represent numerals and
special characters (such as $)
...
Such a set contains between 36 and 64 elements if only capital letters are
included, or between 64 and 128 elements if both uppercase and lowercase letters are
included
...

The standard binary code for the alphanumeric characters is the American Standard
Code for Information Interchange (ASCII), which uses seven bits to code 128 characters, as shown in Table 1
...
The seven bits of the code are designated by b1 through b7,
with b7 the most significant bit
...
The ASCII code also contains 94 graphic characters
that can be printed and 34 nonprinting characters used for various control functions
...


Section 1
...
7
American Standard Code for Information Interchange (ASCII)
b7b6b5
b4b3b2b1

000

001

010

011

100

101

110

111

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI

DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US

SP
!
“
#
$
%
&
‘
(
)
*
+
,

...
They
are listed again below the table with their functional names
...
There are three types
of control characters: format effectors, information separators, and communication‐control

26

Chapter 1

Digital Systems and Binary Numbers

characters
...
They include
the familiar word processor and typewriter controls such as backspace (BS), horizontal tabulation (HT), and carriage return (CR)
...
They include characters such as record separator
(RS) and file separator (FS)
...
Examples of
communication‐control characters are STX (start of text) and ETX (end of text), which are
used to frame a text message transmitted through a communication channel
...
Therefore, ASCII characters most often are stored one
per byte
...
For example, some printers recognize eight‐bit ASCII characters with the
most significant bit set to 0
...


Error‐Detecting Code
To detect errors in data communication and processing, an eighth bit is sometimes added
to the ASCII character to indicate its parity
...
Consider the following two
characters and their even and odd parity:
ASCII A = 1000001
ASCII T = 1010100

With even parity
01000001
11010100

With odd parity
11000001
01010100

In each case, we insert an extra bit in the leftmost position of the code to produce an
even number of 1’s in the character for even parity or an odd number of 1’s in the character for odd parity
...

The parity bit is helpful in detecting errors during the transmission of information
from one location to another
...
The eight‐bit characters that include parity bits
are transmitted to their destination
...
If the parity of the received character is not even, then at least one bit has
changed value during the transmission
...
An even combination of errors,
however, goes undetected, and additional error detection codes may be needed to take
care of that possibility
...
One
possibility is to request retransmission of the message on the assumption that the error
was random and will not occur again
...
8

Binary Storage and Registers

27

back the ASCII NAK (negative acknowledge) control character consisting of an even‐
parity eight bits 10010101
...
The sending end will respond to an
NAK by transmitting the message again until the correct parity is received
...


1
...
A binary cell is a device that possesses two stable
states and is capable of storing one bit (0 or 1) of information
...
The output of the cell is
a physical quantity that distinguishes between the two states
...


Registers
A register is a group of binary cells
...
The state of a register is an n‐tuple of 1’s and 0’s, with
each bit designating the state of one cell in the register
...
Consider, for example,
a 16‐bit register with the following binary content:
1100001111001001
A register with 16 cells can be in one of 216 possible states
...
For the particular example shown, the content of the register
is the binary equivalent of the decimal number 50,121
...
For the ASCII code with an even parity placed
in the eighth most significant bit position, the register contains the two characters C (the
leftmost eight bits) and I (the rightmost eight bits)
...
In the excess‐3 code, the register
holds the decimal number 9,096
...
From this example, it is clear that a register can store discrete elements of information and that the same
bit configuration may be interpreted differently for different types of data depending
on the application
...
In digital systems, a register transfer operation is a basic operation that consists of a transfer of binary information from one set of registers into another set of
registers
...
Figure 1
...
The input unit is assumed to have a
keyboard, a control circuit, and an input register
...

We shall assume that the code used is the ASCII code with an odd‐parity bit
...
After every transfer, the input register is cleared to enable the control to insert a
new eight‐bit code when the keyboard is struck again
...
When a transfer of four characters is completed, the processor register is
full, and its contents are transferred into a memory register
...
1
Transfer of information among registers

CONTROL

Section 1
...
1
...

To process discrete quantities of information in binary form, a computer must be
provided with devices that hold the data to be processed and with circuit elements that
manipulate individual bits of information
...
Binary variables are manipulated by means of digital logic circuits
...
2 illustrates the process of adding two 10‐bit binary numbers
...

The part of the processor unit shown consists of three registers—R1, R2, and R3—
together with digital logic circuits that manipulate the bits of R1 and R2 and transfer into
R3 a binary number equal to their arithmetic sum
...
However, the information stored in
memory can be transferred to processor registers, and the results obtained in processor
registers can be transferred back into a memory register for storage until needed again
...
2
Example of binary information processing

0 1 0 0 1 0 0 0 1 1 R3

30

Chapter 1

Digital Systems and Binary Numbers

into R1 and R2
...
The contents of R3 can now be transferred back to one of the memory registers
...
The registers of the system are the basic elements for storing
and holding the binary information
...
Digital logic circuits and registers are covered in Chapters 2
through 6
...
The description of register operations at the register transfer level and the design of digital systems are covered in
Chapter 8
...
9

BINARY LOGIC
Binary logic deals with variables that take on two discrete values and with operations
that assume logical meaning
...
), but for our purpose, it is convenient to
think in terms of bits and assign the values 1 and 0
...
The formal presentation of
Boolean algebra is covered in more detail in Chapter 2
...


Definition of Binary Logic
Binary logic consists of binary variables and a set of logical operations
...
, with each variable having two and only two distinct possible values: 1 and 0
...
Each operation produces a binary result, denoted by z
...
AND: This operation is represented by a dot or by the absence of an operator
...
” The logical operation
AND is interpreted to mean that z = 1 if and only if x = 1 and y = 1; otherwise
z = 0
...
) The result of the operation x # y is z
...
OR: This operation is represented by a plus sign
...
If both x = 0 and y = 0, then z = 0
...
NOT: This operation is represented by a prime (sometimes by an overbar)
...
In other words, if x = 1, then z = 0, but if x = 0, then z = 1
...
e
...

Binary logic resembles binary arithmetic, and the operations AND and OR have
similarities to multiplication and addition, respectively
...
9

Binary Logic

31

Table 1
...
However,
binary logic should not be confused with binary arithmetic
...
A logic variable is always either 1 or 0
...

For each combination of the values of x and y, there is a value of z specified by the
definition of the logical operation
...
A truth table is a table of all possible combinations of
the variables, showing the relation between the values that the variables may take and
the result of the operation
...
For each combination, the result of the operation is then listed in a
separate row
...
8
...


Logic Gates
Logic gates are electronic circuits that operate on one or more input signals to produce an output signal
...

Voltage‐operated logic circuits respond to two separate voltage levels that represent a
binary variable equal to logic 1 or logic 0
...
In practice,
each voltage level has an acceptable range, as shown in Fig
...
3
...
The intermediate region between the allowed regions is crossed only during a state transition
...
When the physical signal is in a particular range it is interpreted to be either a 0 or a 1
...
3
Signal levels for binary logic values

x

zϭxиy

y
(a) Two-input AND gate

x

z ‫ ؍‬x ϩy

x

xЈ

y
(b) Two-input OR gate

(c) NOT gate or inverter

FIGURE 1
...
1
...

The gates are blocks of hardware that produce the equivalent of logic‐1 or logic‐0 output
signals if input logic requirements are satisfied
...
These input signals
are shown in Fig
...
5 together with the corresponding output signal for each gate
...
The horizontal axis of the timing diagram represents the time, and the
vertical axis shows the signal as it changes between the two possible voltage levels
...
The
low level represents logic 0, the high level logic 1
...
The OR gate responds with a logic
1 output signal if any input signal is logic 1
...
The reason for this name is apparent from the signal response in the timing
diagram, which shows that the output signal inverts the logic sense of the input signal
...
5
Input–output signals for gates

A
B
C

F ϭ ABC

(a) Three-input AND gate

A
B
C
D

GϭAϩBϩCϩD

(b) Four-input OR gate

FIGURE 1
...
An AND gate with three inputs
and an OR gate with four inputs are shown in Fig
...
6
...
The output produces logic 0
if any input is logic 0
...


PROBLEMS
(Answers to problems marked with * appear at the end of the text
...
1

List the octal and hexadecimal numbers from 16 to 32
...


1
...
4G bytes?
1
...
4

What is the largest binary number that can be expressed with 16 bits? What are the equivalent decimal and hexadecimal numbers?

1
...

1
...
What is the
base of the numbers?

34

Chapter 1

Digital Systems and Binary Numbers

1
...

1
...
Which method is faster?

1
...
0101)2
(b)* (16
...
24)8
(d) (DADA
...
1101)2

1
...
10010,
(b) 110
...
Explain why the decimal answer in (b) is 4 times that in (a)
...
11 Perform the following division in binary: 111011 ÷ 101
...
12* Add and multiply the following numbers without converting them to decimal
...

(b) Hexadecimal numbers 2E and 34
...
13 Do the following conversion problems:
(a) Convert decimal 27

...

(b) Calculate the binary equivalent of 2/3 out to eight places
...
How close is the result to 2/3?
(c) Convert the binary result in (b) into hexadecimal
...

Is the answer the same?
1
...

1
...

1
...

Convert C3DF to binary
...

Convert the answer in (c) to hexadecimal and compare with the answer in (a)
...
17 Perform subtraction on the given unsigned numbers using the 10’s complement of the
subtrahend
...
Verify your answers
...
18 Perform subtraction on the given unsigned binary numbers using the 2’s complement of the
subtrahend
...

(a) 10011 - 10010
(b) 100010 - 100110
(c) 1001 - 110101
(d) 101000 - 10101
1
...

Convert them to signed-10’s‐complement form and perform the following operations
(note that the sum is +10,627 and requires five digits and a sign)
...
20 Convert decimal +49 and +29 to binary, using the signed‐2’s‐complement representation
and enough digits to accommodate the numbers
...
Convert the answers back to decimal and
verify that they are correct
...
21 If the numbers (+9,742)10 and (+641)10 are in signed magnitude format, their sum is (+10,383)10
and requires five digits and a sign
...
22 Convert decimal 6,514 to both BCD and ASCII codes
...

1
...

1
...
25 Represent the decimal number 6,248 in (a) BCD, (b) excess‐3 code, (c) 2421 code, and
(d) a 6311 code
...
26 Find the 9’s complement of decimal 6,248 and express it in 2421 code
...
25
...

1
...
Use the minimum
number of bits
...
28 Write the expression “G
...
Include the period and
the space
...
Each eight‐bit code should
have odd parity
...
Boolean algebra,
introduced in the next chapter, bears his name
...
29* Decode the following ASCII code:
1010011 1110100 1100101 1110110 1100101 0100000 1001010 1101111 1100010 1110011
...
30 The following is a string of ASCII characters whose bit patterns have been converted into
hexadecimal for compactness: 73 F4 E5 76 E5 4A EF 62 73
...
The remaining bits are the ASCII code
...

(b) Determine the parity used: odd or even?
1
...
32* What bit must be complemented to change an ASCII letter from capital to lowercase and
vice versa?
1
...
What is its content if it represents
(a) Three decimal digits in BCD?
(b) Three decimal digits in the excess‐3 code?
(c) Three decimal digits in the 84‐2‐1 code?
(d) A binary number?

36

Chapter 1

Digital Systems and Binary Numbers

1
...

1
...
1
...
P1
...
Use all eight possible combinations
of a, b, and c
...
35

1
...
1
...
P1
...
Use all four possible combinations of a
and b
...
36

REFERENCES
1
...

3
...

5
...
J
...
Digital Computer Arithmetic
...

Mano, M
...
1988
...
Englewood Cliffs, NJ:
Prentice‐Hall
...
P
...
T
...
D
...
D
...
1997
...
Upper Saddle River, NJ: Prentice Hall
...
1974
...
New York: John Wiley
...
H
...
2004
...
Upper Saddle
River, NJ: Prentice‐Hall
...
1

INTRODUCTION
Because binary logic is used in all of today’s digital computers and devices, the cost of
the circuits that implement it is an important factor addressed by designers—be they
computer engineers, electrical engineers, or computer scientists
...
Mathematical methods that simplify circuits rely primarily on
Boolean algebra
...


2
...
A set
of elements is any collection of objects, usually having a common property
...
A set with a denumerable number
of elements is specified by braces: A = {1, 2, 3, 4} indicates that the elements of set A
are the numbers 1, 2, 3, and 4
...
As an example,
consider the relation a * b = c
...
However, * is not a binary operator
if a, b H S, and if c x S
...
2

Basic Definitions

39

The postulates of a mathematical system form the basic assumptions from which it
is possible to deduce the rules, theorems, and properties of the system
...
Closure
...
For example, the set of natural numbers N = {1, 2, 3, 4, c} is closed with
respect to the binary operator + by the rules of arithmetic addition, since, for any
a, b H N, there is a unique c H N such that a + b = c
...

2
...
A binary operator * on a set S is said to be associative whenever
(x * y) * z = x * (y * z) for all x, y, z, H S
3
...
A binary operator * on a set S is said to be commutative whenever
x * y = y * x for all x, y H S
4
...
A set S is said to have an identity element with respect to a binary
operation * on S if there exists an element e H S with the property that
e * x = x * e = x for every x H S
Example: The element 0 is an identity element with respect to the binary operator
+ on the set of integers I = { c, -3, -2, -1, 0, 1, 2, 3, c}, since
x + 0 = 0 + x = x for any x H I
The set of natural numbers, N, has no identity element, since 0 is excluded from the set
...
Inverse
...

6
...
If * and # are two binary operators on a set S, * is said to be distributive over # whenever
x * (y # z) = (x * y) # (x * z)
A field is an example of an algebraic structure
...
The set of real numbers, together with the binary operators + and # ,

40

Chapter 2

Boolean Algebra and Logic Gates

forms the field of real numbers
...
The operators and postulates have the following meanings:
The binary operator + defines addition
...

The additive inverse defines subtraction
...

The multiplicative identity is 1
...
e
...

The only distributive law applicable is that of # over +:
a # (b + c) = (a # b) + (a # c)

2
...
In
1938, Claude E
...
For the
formal definition of Boolean algebra, we shall employ the postulates formulated by
E
...
Huntington in 1904
...
(a) The structure is closed with respect to the operator +
...

2
...

(b) The element 1 is an identity element with respect to # ; that is, x # 1 = 1 # x = x
...
(a) The structure is commutative with respect to +; that is, x + y = y + x
...

4
...

(b) The operator + is distributive over # ; that is, x + (y # z) = (x + y) # (x + z)
...
For every element x H B, there exists an element xЈ H B (called the complement of x)
such that (a) x + xЈ = 1 and (b) x # xЈ = 0
...
There exist at least two elements x, y H B such that x ϶ y
...
Huntington postulates do not include the associative law
...

2
...
e
...


Section 2
...
Boolean algebra does not have additive or multiplicative inverses; therefore, there
are no subtraction or division operations
...
Postulate 5 defines an operator called the complement that is not available in
ordinary algebra
...
Ordinary algebra deals with the real numbers, which constitute an infinite set of
elements
...

Boolean algebra resembles ordinary algebra in some respects
...
Although one can use some knowledge from
ordinary algebra to deal with Boolean algebra, the beginner must be careful not to
substitute the rules of ordinary algebra where they are not applicable
...
For example, the elements of the field of real
numbers are numbers, whereas variables such as a, b, c, etc
...
Similarly, in Boolean algebra, one defines the
elements of the set B, and variables such as x, y, and z are merely symbols that represent
the elements
...
the elements of the set B,
2
...
the set of elements, B, together with the two operators, satisfy the six Huntington
postulates
...
In our subsequent work, we deal only with a two‐valued
Boolean algebra (i
...
, a Boolean algebra with only two elements)
...

Our interest here is in the application of Boolean algebra to gate‐type circuits commonly
used in digital devices and computers
...
8
...

1
...

2
...

(b) 1 # 1 = 1
This establishes the two identity elements, 0 for + and 1 for # , as defined by
postulate 2
...
The commutative laws are obvious from the symmetry of the binary operator tables
...
(a) The distributive law x # (y + z) = (x # y) + (x # z) can be shown to hold from
the operator tables by forming a truth table of all possible values of x, y, and z
...

5
...

(b) x # xЈ = 0, since 0 # 0Ј = 0 # 1 = 0 and 1 # 1Ј = 1 # 0 = 0
...

6
...

We have just established a two‐valued Boolean algebra having a set of two elements,
1 and 0, two binary operators with rules equivalent to the AND and OR operations, and
a complement operator equivalent to the NOT operator
...
9
...
The formal

Section 2
...
The two‐valued Boolean algebra defined in this section is also called “switching
algebra” by engineers
...
9
...


2
...
3, the Huntington postulates were listed in pairs and designated by part
(a) and part (b)
...
This important property of Boolean algebra is
called the duality principle and states that every algebraic expression deducible from
the postulates of Boolean algebra remains valid if the operators and identity elements
are interchanged
...
The duality principle has many applications
...


Basic Theorems
Table 2
...
The notation
is simplified by omitting the binary operator whenever doing so does not lead to
confusion
...
1
Postulates and Theorems of Boolean Algebra
Postulate 2

(a)

x + 0 = x

(b)

x#1 = x

Postulate 5

(a)

x + xЈ = 1

(b)

x # xЈ = 0

Theorem 1

(a)

x + x = x

(b)

x #x = x

Theorem 2

(a)

x + 1 = 1

(b)

x #0 = 0

Postulate 3, commutative

(a)

x + y = y + x

Theorem 4, associative

(x Ј)Ј = x

Theorem 3, involution

(b)

x y = yx

(a) x + (y + z) = (x + y) + z

(b)

x (yz) = (x y)z

Postulate 4, distributive

(a)

x (y + z) = x y + x z

(b)

Theorem 5, DeMorgan

(a)

(x + y)Ј = x ЈyЈ

(b)

Theorem 6, absorption

(a)

x + xy = x

(b)

x + yz = (x + y)(x + z)
(x y)Ј = x Ј + yЈ
x (x + y) = x

44

Chapter 2

Boolean Algebra and Logic Gates

algebra
...
The postulates are basic axioms of the algebraic structure and
need no proof
...
Proofs of the theorems
with one variable are presented next
...

THEOREM 1(a): x + x = x
...

Statement

x#x =
=
=
=
=

xx + 0
xx + xxЈ
x(x + xЈ)
x#1
x

Justification
postulate 2(a)
5(b)
4(a)
5(a)
2(b)

Note that theorem 1(b) is the dual of theorem 1(a) and that each step of the proof
in part (b) is the dual of its counterpart in part (a)
...

THEOREM 2(a): x + 1 = 1
...

THEOREM 3: (xЈ)Ј = x
...
The complement of xЈ is x and is also (xЈ)Ј
...
4

Basic Theorems and Properties of Boolean Algebra

45

Therefore, since the complement is unique, we have (xЈ)Ј = x
...
Take, for example, the absorption theorem:
THEOREM 6(a): x + xy = x
...

The theorems of Boolean algebra can be proven by means of truth tables
...
The following truth table verifies
the first absorption theorem:
x

y

xy

x ؉ xy

0

0

0

0

0

1

0

0

1

0

0

1

1

1

1

1

The algebraic proofs of the associative law and DeMorgan’s theorem are long and will
not be shown here
...
For example,
the truth table for the first DeMorgan’s theorem, (x + y)Ј = xЈyЈ, is as follows:
x ؉ y (x ؉ y)؅

x

y

x؅

y؅

x؅y؅

0

0

0

0

1

1

1

1

1

1

0

1

0

0

1

0

1

1

1

0

0

1

0

1

0

0

0

0

Operator Precedence
The operator precedence for evaluating Boolean expressions is (1) parentheses,
(2) NOT, (3) AND, and (4) OR
...
The next operation that holds precedence is the
complement, and then follows the AND and, finally, the OR
...
The left side of the expression is
(x + y)Ј
...
The right side of the expression is xЈyЈ, so the complement
of x and the complement of y are both evaluated first and the result is then ANDed
...


2
...
A
Boolean function described by an algebraic expression consists of binary variables, the
constants 0 and 1, and the logic operation symbols
...
As an example, consider the Boolean function
F1 = x + yЈz
The function F1 is equal to 1 if x is equal to 1 or if both yЈ and z are equal to 1
...
The complement operation dictates that when yЈ = 1, y = 0
...
A Boolean function expresses the logical relationship between binary variables and is evaluated by determining the binary value of
the expression for all possible values of the variables
...
The number of rows in the
truth table is 2n, where n is the number of variables in the function
...
Table 2
...
There are eight possible binary combinations for assigning bits to the three variables x, y, and z
...
The table shows that
the function is equal to 1 when x = 1 or when yz = 01 and is equal to 0 otherwise
...
The logic‐circuit
diagram (also called a schematic) for F1 is shown in Fig
...
1
...
There is an AND gate for the term yЈz and an OR gate
Table 2
...
5
x

Boolean Functions

47

F1

y
z

FIGURE 2
...
In logic‐circuit diagrams, the variables of the function are taken
as the inputs of the circuit and the binary variable F1 is taken as the output of the circuit
...

Rather than listing each combination of inputs and outputs, it indicates how to compute
the logic value of each output from the logic values of the inputs
...

However, when the function is in algebraic form, it can be expressed in a variety of ways,
all of which have equivalent logic
...
Conversely, the interconnection of gates will dictate the logic expression
...
Designers are motivated to reduce the complexity and number of gates because
their effort can significantly reduce the cost of a circuit
...
 2
...
Input variables x and y are complemented with inverters to obtain xЈ and
yЈ
...
The
OR gate forms the logical OR of the three terms
...
2
...
This set of conditions produces
four 1’s and four 0’s for F2
...
2
...
It is obvious that the circuit in (b) is simpler than the one in (a), yet both
implement the same function
...
The simplified expression is equal to 1 when xz = 01 or
when xy = 10
...
Since both expressions

48

Chapter 2

Boolean Algebra and Logic Gates

x

y

F2

z

(a) F2 ϭ xЈyЈz ϩ xЈyz ϩ xyЈ

x
y
F2
z
(b) F2 ϭ xyЈ ϩ xЈz

FIGURE 2
...
Therefore, the two circuits have the
same outputs for all possible binary combinations of inputs of the three variables
...
In general,
there are many equivalent representations of a logic function
...


Algebraic Manipulation
When a Boolean expression is implemented with logic gates, each term requires a gate
and each variable within the term designates an input to the gate
...
The
function of Fig
...
2(a) has three terms and eight literals, and the one in Fig
...
2(b) has
two terms and four literals
...
The manipulation of Boolean algebra consists mostly of reducing an expression for the purpose of
obtaining a simpler circuit
...
For complex Boolean functions and many

Section 2
...
The concepts introduced in this chapter provide the framework for those tools
...
The examples that follow illustrate the algebraic manipulation of Boolean algebra
to acquaint the reader with this important design task
...
1 
Simplify the following Boolean functions to a minimum number of literals
...
x(xЈ + y) = xxЈ + xy = 0 + xy = xy
...
x + xЈy = (x + xЈ)(x + y) = 1(x + y) = x + y
...
(x + y)(x + yЈ) = x + xy + xyЈ + yyЈ = x(1 + y + yЈ) = x
...
xy + xЈz + yz = xy + xЈz + yz(x + xЈ)
= xy + xЈz + xyz + xЈyz
= xy(1 + z) + xЈz(1 + y)
= xy + xЈz
...
(x + y)(xЈ + z)(y + z) = (x + y)(xЈ + z), by duality from function 4
...
An easier way to simplify function 3 is by means of postulate 4(b) from
Table 2
...
The fourth function illustrates the fact that
an increase in the number of literals sometimes leads to a simpler final expression
...
Functions 4 and 5 are together known as the consensus theorem
...
The complement of a function may be derived algebraically
through DeMorgan’s theorems, listed in Table 2
...
DeMorgan’s theorems can be extended to three or more variables
...
1:
(A + B + C)Ј = (A + x)Ј
= AЈxЈ

let B + C = x
by theorem 5(a) (DeMorgan)

= AЈ(B + C)Ј substitute B + C = x
= AЈ(BЈCЈ)

by theorem 5(a) (DeMorgan)

= AЈBЈCЈ

by theorem 4(b) (associative)

50

Chapter 2

Boolean Algebra and Logic Gates

DeMorgan’s theorems for any number of variables resemble the two‐variable case in
form and can be derived by successive substitutions similar to the method used in the
preceding derivation
...


EXAMPLE 2
...
By
applying DeMorgan’s theorems as many times as necessary, the complements are
obtained as follows:
F1= = (xЈyzЈ + xЈyЈz)Ј = (xЈyzЈ)Ј(xЈyЈz)Ј = (x + yЈ + z)(x + y + zЈ)
=
F2 = [x(yЈzЈ + yz)]Ј = xЈ + (yЈzЈ + yz)Ј = xЈ + (yЈzЈ)Ј(yz)Ј
= xЈ + (y + z)(yЈ + zЈ)
= xЈ + yzЈ + yЈz
■
A simpler procedure for deriving the complement of a function is to take the dual of
the function and complement each literal
...
Remember that the dual of a function is obtained from
the interchange of AND and OR operators and 1’s and 0’s
...
3
Find the complement of the functions F1 and F2 of Example 2
...

1
...

The dual of F1 is (xЈ + y + zЈ)(xЈ + yЈ + z)
...

2
...

The dual of F2 is x + (yЈ + zЈ)(y + z)
...

■

Section 2
...
6

Canonical and Standard Forms

51

C A N O N I C A L A N D S TA N D A R D F O R M S

Minterms and Maxterms
A binary variable may appear either in its normal form (x) or in its complement form (xЈ)
...
Since each
variable may appear in either form, there are four possible combinations: xЈyЈ, xЈy, xyЈ,
and xy
...
In a
similar manner, n variables can be combined to form 2n minterms
...
3 for three
variables
...
Each
minterm is obtained from an AND term of the n variables, with each variable being
primed if the corresponding bit of the binary number is a 0 and unprimed if a 1
...

In a similar fashion, n variables forming an OR term, with each variable being primed
or unprimed, provide 2n possible combinations, called maxterms, or standard sums
...
3
...
It is important to note that (1) each maxterm is obtained from an OR term of the n variables, with
each variable being unprimed if the corresponding bit is a 0 and primed if a 1, and (2)
each maxterm is the complement of its corresponding minterm and vice versa
...
For example, the function f1 in Table 2
...
Since each one of these minterms results in f1 = 1, we have
f1 = xЈyЈz + xyЈzЈ + xyz = m1 + m4 + m7
Table 2
...
4
Functions of Three Variables
x

y

z

Function f1

Function f2

0

0

0

0

0

0

0

1

1

0

0

1

0

0

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Similarly, it may be easily verified that
f2 = xЈyz + xyЈz + xyzЈ + xyz = m3 + m5 + m6 + m7
These examples demonstrate an important property of Boolean algebra: Any Boolean
function can be expressed as a sum of minterms (with “sum” meaning the ORing of terms)
...
It may be read from the truth
table by forming a minterm for each combination that produces a 0 in the function and
then ORing those terms
...
The procedure for obtaining the product of maxterms directly from the truth
table is as follows: Form a maxterm for each combination of the variables that produces
a 0 in the function, and then form the AND of all those maxterms
...


Sum of Minterms
Previously, we stated that, for n binary variables, one can obtain 2n distinct minterms and
that any Boolean function can be expressed as a sum of minterms
...
6

Canonical and Standard Forms

53

truth table
...
It is sometimes convenient to express a Boolean function in its sum‐of‐minterms
form
...
Each term is then inspected to see if it contains all the
variables
...
The next example clarifies this procedure
...
4
Express the Boolean function F = A + BЈC as a sum of minterms
...
The first term A is missing two variables; therefore,
A = A(B + BЈ) = AB + ABЈ
This function is still missing one variable, so
A = AB(C + CЈ) + ABЈ(C + CЈ)
= ABC + ABCЈ + ABЈC + ABЈCЈ
The second term BЈC is missing one variable; hence,
BЈC = BЈC(A + AЈ) = ABЈC + AЈBЈC
Combining all terms, we have
F = A + BЈC
= ABC + ABCЈ + ABЈC + ABЈCЈ + AЈBЈC
But ABЈC appears twice, and according to theorem 1 (x + x = x), it is possible to
remove one of those occurrences
...
The letters in parentheses following F form
a list of the variables in the order taken when the minterm is converted to an AND term
...
Consider the Boolean function given in Example 2
...
5 can be derived directly from the algebraic expression by listing the eight binary combinations under variables A, B, and C and inserting

54

Chapter 2

Boolean Algebra and Logic Gates
Table 2
...
From the truth table,
we can then read the five minterms of the function to be 1, 4, 5, 6, and 7
...
To express a Boolean function as a product of maxterms, it must first be
brought into a form of OR terms
...
Then any missing variable x in each OR term is ORed with
xxЈ
...


EXAMPLE 2
...
First, convert
the function into OR terms by using the distributive law:
F = xy + xЈz = (xy + xЈ)(xy + z)
= (x + xЈ)(y + xЈ)(x + z)(y + z)
= (xЈ + y)(x + z)(y + z)
The function has three variables: x, y, and z
...
6

Canonical and Standard Forms

55

A convenient way to express this function is as follows:
F(x, y, z) = ⌸(0, 2, 4, 5)
The product symbol, ⌸, denotes the ANDing of maxterms; the numbers are the indices
of the maxterms of the function
...
This is because the original function is expressed
by those minterms which make the function equal to 1, whereas its complement is a 1 for
those minterms for which the function is a 0
...
3
...

The last example demonstrates the conversion between a function expressed in sum‐
of‐minterms form and its equivalent in product‐of‐maxterms form
...
We now state a general conversion procedure: To convert from one canonical
form to another, interchange the symbols ⌺ and ⌸ and list those numbers missing from
the original form
...

A Boolean function can be converted from an algebraic expression to a product of
maxterms by means of a truth table and the canonical conversion procedure
...
6
...
The minterms of the function are read from the truth table to be 1, 3, 6, and 7
...
6
Truth Table for F ‫ ؍‬xy ؉ xЈz
x

y

z

F

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1
0
0
1
1

Minterms

Maxterms

Since there is a total of eight minterms or maxterms in a function of three variables, we
determine the missing terms to be 0, 2, 4, and 5
...
5
...
These forms are very seldom the ones with the
least number of literals, because each minterm or maxterm must contain, by definition,
all the variables, either complemented or uncomplemented
...
In this configuration,
the terms that form the function may contain one, two, or any number of literals
...

The sum of products is a Boolean expression containing AND terms, called product
terms, with one or more literals each
...
An
example of a function expressed as a sum of products is
F1 = yЈ + xy + xЈyzЈ
The expression has three product terms, with one, two, and three literals
...

The logic diagram of a sum‐of‐products expression consists of a group of AND gates
followed by a single OR gate
...
2
...
Each
product term requires an AND gate, except for a term with a single literal
...
It is assumed that the input variables are directly available in their complements, so inverters are not included in the diagram
...


Section 2
...
3
Two‐level implementation
A
B

A
B
C
D
E

F3

C
D

F3

C
E
(a) AB ϩ C(D ϩ E)

(b) AB ϩ CD ϩ CE

FIGURE 2
...

Each term may have any number of literals
...
An example of a function expressed as a product of sums is
F2 = x(yЈ + z)(xЈ + y + zЈ)
This expression has three sum terms, with one, two, and three literals
...
The use of the words product and sum stems from the similarity of the
AND operation to the arithmetic product (multiplication) and the similarity of the OR
operation to the arithmetic sum (addition)
...
2
...
This standard type of expression
results in a two‐level structure of gates
...
For example, the function
F3 = AB + C(D + E)
is neither in sum‐of‐products nor in product‐of‐sums form
...
2
...
There
are three levels of gating in this circuit
...
2
...
In general, a two‐level
implementation is preferred because it produces the least amount of delay through the
gates when the signal propagates from the inputs to the output
...


2
...
Previously we stated that
there are 22n functions for n binary variables
...
Therefore, the AND and OR functions
are only 2 of a total of 16 possible functions formed with two binary variables
...

The truth tables for the 16 functions formed with two binary variables are listed in
Table 2
...

tion for the two variables, x and y
...
The 16 functions can be expressed
algebraically by means of Boolean functions, as is shown in the first column of Table 2
...

The Boolean expressions listed are simplified to their minimum number of literals
...
Such operator symbols are listed in the second column of
Table 2
...
However, of all the new symbols shown, only the exclusive‐OR symbol, ᮍ,
is in common use by digital designers
...
8 is listed with an accompanying name and a comment that explains the function in some way
...
Two functions that produce a constant 0 or 1
...
Four functions with unary operations: complement and transfer
...
Ten functions with binary operators that define eight different operations: AND,
OR, NAND, NOR, exclusive‐OR, equivalence, inhibition, and implication
...
7
Truth Tables for the 16 Functions of Two Binary Variables
x

y

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

0
0
1
1

0
1
0
1

0
0
0
0

0
0
0
1

0
0
1
0

0
0
1
1

0
1
0
0

0
1
0
1

0
1
1
0

0
1
1
1

1
0
0
0

1
0
0
1

F10 F11 F12 F13 F14 F15
1
0
1
0

1
0
1
1

1
1
0
0

1
1
0
1

1
1
1
0

1
1
1
1

1
The symbol ˆ is also used to indicate the exclusive or operator, e
...
, xˆy
...
g
...


Section 2
...
8
Boolean Expressions for the 16 Functions of Two Variables
Boolean Functions
F0
F1
F2
F3
F4
F5

=
=
=
=
=
=

0
xy
xyЈ
x
xЈy
y

Operator
Symbol
x#y
x/y
y/x

F7 = x + y

xᮍy
x + y

F8 = (x + y)Ј

xTy

F9 = xy + xЈyЈ

(x ᮍ y)Ј
yЈ
xʚy

F6 = xyЈ + xЈy

F10
F11
F12
F13

=
=
=
=

yЈ
x + yЈ
xЈ
xЈ + y

F14 = (xy)Ј
F15 = 1

xЈ
xʛy
xcy

Name

Comments

Null
AND
Inhibition
Transfer
Inhibition
Transfer

Binary constant 0
x and y
x, but not y
x
y, but not x
y

Exclusive‐OR

x or y, but not both

OR
NOR

x or y
Not‐OR

Equivalence

x equals y

Complement
Implication
Complement
Implication

Not y
If y, then x
Not x
If x, then y

NAND

Not‐AND

Identity

Binary constant 1

Constants for binary functions can be equal to only 1 or 0
...
A function that is equal to an
input variable has been given the name transfer, because the variable x or y is transferred
through the gate that forms the function without changing its value
...
The AND and OR operators have been mentioned in conjunction
with Boolean algebra
...

The NOR function is the complement of the OR function, and its name is an
abbreviation of not‐OR
...
The exclusive‐OR, abbreviated XOR, is similar to OR, but
excludes the combination of both x and y being equal to 1; it holds only when x and y
differ in value
...
) Equivalence is a function that is 1 when the two binary variables are equal (i
...
, when both
are 0 or both are 1)
...
This can be easily verified by inspecting Table 2
...
For this reason, the equivalence function is called
exclusive‐NOR, abbreviated XNOR
...
2, has two binary operators, which we have
called AND and OR, and a unary operator, NOT (complement)
...
There is nothing unique about this procedure
...
There are, nevertheless, good reasons for
introducing Boolean algebra in the way it has been introduced
...

Moreover, the Huntington postulates reflect the dual nature of the algebra, emphasizing
the symmetry of + and # with respect to each other
...
8

D I G I TA L L O G I C G AT E S
Since Boolean functions are expressed in terms of AND, OR, and NOT operations, it is
easier to implement a Boolean function with these type of gates
...
Factors to be
weighed in considering the construction of other types of logic gates are (1) the feasibility and economy of producing the gate with physical components, (2) the possibility of
extending the gate to more than two inputs, (3) the basic properties of the binary operator, such as commutativity and associativity, and (4) the ability of the gate to implement
Boolean functions alone or in conjunction with other gates
...
8, two are equal to a constant and four are
repeated
...

Two—inhibition and implication—are not commutative or associative and thus are
impractical to use as standard logic gates
...

The graphic symbols and truth tables of the eight gates are shown in Fig
...
5
...
The AND, OR, and inverter circuits were defined in Fig
...
6
...
The small circle in the output of the graphic symbol of an inverter
(referred to as a bubble) designates the logic complement
...
A buffer produces the transfer function, but does not produce
a logic operation, since the binary value of the output is equal to the binary value of the
input
...

The NAND function is the complement of the AND function, as indicated by a
graphic symbol that consists of an AND graphic symbol followed by a small circle
...
NAND and NOR gates are used extensively as standard logic
gates and are in fact far more popular than the AND and OR gates
...


Section 2
...
5
Digital logic gates

x
y

x
y

x
y

F

F

F

F

F ϭ (xy)Ј

F ϭ (x ϩ y)Ј

F ϭ xyЈ ϩ xЈy
ϭxy

F ϭ xy ϩ xЈyЈ
ϭ (x  y)Ј

0
0
1
1

0
1
0
1

1
1
1
0

y

F

0
0
1
1

0
1
0
1

1
0
0
0

y

F

0
0
1
1

0
1
0
1

0
1
1
0

x

NOR

y

F

x

NAND

y

x

x

y

F

0
0
1
1

0
1
0
1

1
0
0
1

61

62

Chapter 2

Boolean Algebra and Logic Gates

The exclusive‐OR gate has a graphic symbol similar to that of the OR gate, except
for the additional curved line on the input side
...


Extension to Multiple Inputs
The gates shown in Fig
...
5—except for the inverter and buffer—can be extended to
have more than two inputs
...
The AND and OR operations,
defined in Boolean algebra, possess these two properties
...

The NAND and NOR functions are commutative, and their gates can be extended
to have more than two inputs, provided that the definition of the operation is modified
slightly
...
e
...
2
...
Thus, by definition, we have
x T y T z = (x + y + z)Ј
x c y c z = (xyz)Ј
The graphic symbols for the three‐input gates are shown in Fig
...
7
...
To demonstrate this principle, consider the circuit of Fig
...
7(c)
...
It also shows that
an expression in sum‐of‐products form can be implemented with NAND gates
...
7
...
However, multiple‐input exclusive‐OR gates
are uncommon from the hardware standpoint
...
Moreover, the definition of the function must
be modified when extended to more than two variables
...
e
...
The construction

Section 2
...
6
Demonstrating the nonassociativity of the NOR operator: (x T y) T z ϶ x T (y T z)
x
y
z

(x ϩ y ϩ z)Ј
(a) 3-input NOR gate

x
y
z

(xyz)Ј
(b) 3-input NAND gate

A
B
C
F ϭ [(ABC)Ј и (DE)Ј]Ј ϭ ABC ϩ DE
D
E
(c) Cascaded NAND gates

FIGURE 2
...
2
...
This function is normally
implemented by cascading two‐input gates, as shown in (a)
...
The truth table in (c) clearly
indicates that the output F is equal to 1 if only one input is equal to 1 or if all three inputs
are equal to 1 (i
...
, when the total number of 1’s in the input variables is odd)
...
9
...
One signal value represents logic 1 and the other logic 0
...
8
Three‐input exclusive‐OR gate

Logic
value

Signal
value

Logic
value

Signal
value

1

H

0

H

L

1

0
(a) Positive logic

L
(b) Negative logic

FIGURE 2
...
2
...
The higher signal level is designated by
H and the lower signal level by L
...
Choosing the low‐level L to represent logic 1 defines a negative
logic system
...
It is not the actual values of the signals
that determine the type of logic, but rather the assignment of logic values to the relative
amplitudes of the two signal levels
...
It is up
to the user to decide on a positive or negative logic polarity
...
2
...
The truth table for this gate is listed in Fig
...
10(a)
...
The truth table
of Fig
...
10(c) assumes a positive logic assignment, with H = 1 and L = 0
...
The graphic symbol for a positive
logic AND gate is shown in Fig
...
10(d)
...
The result is the truth table of Fig
...
10(e)
...
The graphic symbol for the negative‐
logic OR gate is shown in Fig
...
10(f)
...
8
x

y
L
H
L
H

L
L
L
H

65

z

L
L
H
H

Digital Logic Gates

x
y

(a) Truth table
with H and L

x

y
0
1
0
1

0
0
0
1

z

(b) Gate block diagram

z

0
0
1
1

Digital
gate

(c) Truth table for
positive logic

x

y
1
0
1
0

1
1
1
0

z

(d) Positive logic AND gate

z

1
1
0
0

x
y

(e) Truth table for
negative logic

x
y

z
(f) Negative logic OR gate

FIGURE 2
...
Thus, the same physical gate can operate either
as a positive‐logic AND gate or as a negative‐logic OR gate
...
Since this operation produces the dual of a function, the change of all terminals from one polarity to the other results in taking the dual of the function
...
In addition, one must not forget to include the polarity‐indicator
triangle in the graphic symbols when negative logic is assumed
...


66

2
...
The complex
chemical and physical processes used to form a semiconductor circuit are not a subject
of this book
...
The chip is mounted in a ceramic or plastic container, and connections are welded
to external pins to form the integrated circuit
...
Each IC has a numeric
designation printed on the surface of the package for identification
...


Levels of Integration
Digital ICs are often categorized according to the complexity of their circuits, as measured by the number of logic gates in a single package
...

Small‐scale integration (SSI) devices contain several independent gates in a single
package
...
The number of gates is usually fewer than 10 and is limited by the number of
pins available in the IC
...
They usually perform specific elementary digital operations
...

Large‐scale integration (LSI) devices contain thousands of gates in a single package
...
Some LSI components are presented in Chapter 7
...
Examples are large memory arrays and complex microcomputer chips
...


Digital Logic Families
Digital integrated circuits are classified not only by their complexity or logical operation,
but also by the specific circuit technology to which they belong
...
Each logic family has its own basic electronic
circuit upon which more complex digital circuits and components are developed
...
The electronic

Section 2
...
Many different logic families of digital integrated circuits have been
introduced commercially
...


TTL is a logic family that has been in use for 50 years and is considered to be standard
...
MOS is suitable
for circuits that need high component density, and CMOS is preferable in systems
requiring low power consumption, such as digital cameras, personal media players, and
other handheld portable devices
...
The most important parameters distinguishing logic families are listed
below; CMOS integrated circuits are discussed briefly in the appendix
...
A standard load is usually defined as the
amount of current needed by an input of another similar gate in the same family
...

Power dissipation is the power consumed by the gate that must be available from the
power supply
...
For example, if the input of an inverter switches from 0 to 1, the output
will switch from 1 to 0, but after a time determined by the propagation delay of the
device
...

Noise margin is the maximum external noise voltage added to an input signal that
does not cause an undesirable change in the circuit output
...
Prior to exposure, the wafers are coated
with a photoresistive material that either hardens or softens when exposed to light
...
The exposed
regions are then implanted with dopant atoms to create a semiconductor material having the electrical properties of transistors and the logical properties of gates
...
e
...

The design of digital systems with VLSI circuits containing millions of transistors and
gates is an enormous and formidable task
...
Electronic design automation (EDA) covers all phases of the design of integrated circuits
...
g
...
There
are a variety of options available for creating the physical realization of a digital circuit
in silicon
...
With each of these devices comes a set of CAD tools that provide
the necessary software to facilitate the hardware fabrication of the unit
...

Some CAD systems include an editing program for creating and modifying schematic
diagrams on a computer screen
...
With the aid of menus, keyboard commands, and a mouse, a schematic editor can
draw circuit diagrams of digital circuits on the computer screen
...
The schematic entry software creates and manages a database
containing the information produced with the schematic
...
e
...
Verification is performed by applying inputs to the
circuit and using a logic simulator to determine and display the outputs in text or waveform format
...
Such a language resembles a computer programming
language, but is specifically oriented to describing digital hardware
...
Moreover, the HDL description of a circuit’s functionality
can be abstract, without reference to specific hardware, thereby freeing a designer to
devote attention to higher level functional detail (e
...
, under certain conditions the
circuit must detect a particular pattern of 1’s and 0’s in a serial bit stream of data) rather
than transistor‐level detail
...
In tandem
with the emergence of HDL‐based design languages, tools have been developed to
automatically and optimally synthesize the logic described by an HDL model of a
circuit
...
Two HDLs—Verilog and VHDL—have been approved as
standards by the Institute of Electronics and Electrical Engineers (IEEE) and are in
use by design teams worldwide
...
10, and
because of its importance, we include several exercises and design problems based on
Verilog throughout the book
...
)
2
...
2

Simplify the following Boolean expressions to a minimum number of literals:
(a) * xy + xyЈ
(b) * (x + y) (x + yЈ)
(c) * xyz + xЈy + xyzЈ
(d) * (A + B)Ј (AЈ + BЈ)Ј
(e) (a + b + cЈ)(aЈ bЈ + c)
(f) aЈbc + abcЈ + abc + aЈbcЈ

2
...
4

Reduce the following Boolean expressions to the indicated number of literals:
(a) * AЈCЈ + ABC + ACЈ
to three literals
(b) * (xЈyЈ + z)Ј + z + xy + wz
to three literals
(c) * AЈB(DЈ + CЈD) + B(A + AЈCD)
to one literal
(d) * (AЈ + C) (AЈ + CЈ) (A + B + CЈD)
to four literals
(e) ABC'D + A'BD + ABCD
to two literals

2
...
2
...
6

Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2
...


2
...
4
...
8

Find the complement of F = wx + yz; then show that FFЈ = 0 and F + FЈ = 1
...
9

Find the complement of the following expressions:
(a) * xyЈ + xЈy
(b) (a + c) (a + bЈ) (aЈ + b + cЈ)
(c) z + zЈ(vЈw + xy)

2
...

(b) The Boolean function G = F1F2 contains only the minterms that are common to F1
and F2
...
11 List the truth table of the function:
(a) * F = xy + xyЈ + yЈz

(b) F = bc + aЈcЈ

2
...
Given two eight‐bit strings A = 10110001
and B = 10101100, evaluate the eight‐bit result after the following logical operations:
(a)* AND
(b) OR
(c)* XOR
(d)* NOT A
(e) NOT B

70

Chapter 2

Boolean Algebra and Logic Gates

2
...
14 Implement the Boolean function
F = xy + xЈyЈ + yЈz
(a)
(b) *
(c)
(d)
(e)

With AND, OR, and inverter gates
With OR and inverter gates
With AND and inverter gates
With NAND and inverter gates
With NOR and inverter gates

2
...
16 The logical sum of all minterms of a Boolean function of n variables is 1
...

(b) Suggest a procedure for a general proof
...
17 Obtain the truth table of the following functions, and express each function in sum‐of‐minterms and product‐of‐maxterms form:
(a) * (b + cd)(c + bd)
(b) (cd + bЈc + bdЈ)(b + d)
(c) (cЈ + d)(b + cЈ)
(d) bdЈ + acdЈ + abЈc + aЈcЈ
2
...

Draw the logic diagram, using the original Boolean expression
...

Obtain the truth table of the function from the simplified expression and show that
it is the same as the one in part (a)
...


Problems

71

2
...
20 Express the complement of the following functions in sum‐of‐minterms form:
(a) F(A,B ,C, D) = g (2, 4, 7 10, 12, 14)
,
(b) F(x, y, z) = w (3, 5, 7)
2
...
22* Convert each of the following expressions into sum of products and product of sums:
(a) (u + xw)(x + uЈv)
(b) xЈ + x(x + yЈ)(y + zЈ)
2
...
24 Show that the dual of the exclusive‐OR is equal to its complement
...
25 By substituting the Boolean expression equivalent of the binary operations as defined in
Table 2
...

(b) The exclusive‐OR operation is commutative and associative
...
26 Show that a positive logic NAND gate is a negative logic NOR gate and vice versa
...
27 Write the Boolean equations and draw the logic diagram of the circuit whose outputs are
defined by the following truth table:

Table P2
...
28 Write Boolean expressions and construct the truth tables describing the outputs of the
circuits described by the logic diagrams in Fig
...
28
...
29 Determine whether the following Boolean equation is true or false
...
28
2
...
31 Write the following Boolean expression in product of sums form:
aЈb + aЈcЈ + abc

REFERENCES
1
...

3
...


5
...

7
...
1854
...
New York: Dover
...
L
...
Logic Design of Digital Systems, 3rd ed
...

Huntington, E
...
Sets of independent postulates for the algebra of logic
...
Am
...

Soc
...

IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, Language Reference Manual (LRM), IEEE Std
...

IEEE Standard VHDL Language Reference Manual (LRM), IEEE Std
...

Mano, M
...
and C
...
Kime
...
Logic and Computer Design Fundamentals, 2nd ed
...

Shannon, C
...
A symbolic analysis of relay and switching circuits
...
AIEE, 57 (1938):
713–723
...
1

INTRODUCTION
Gate-level minimization is the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit
...

Fortunately, computer-based logic synthesis tools can minimize a large set of Boolean
equations efficiently and quickly
...
This chapter serves
as a foundation for your understanding of that important topic and will enable you to
execute a manual design of simple circuits, preparing you for skilled use of modern
design tools
...


3
...
Although the truth table representation of a function is unique, when it is expressed
algebraically it can appear in many different, but equivalent, forms
...
4
...
The map method presented here provides a simple, straightforward
procedure for minimizing Boolean functions
...
The map method is also known as the Karnaugh map or K-map
...
Since any Boolean function can be expressed as a
sum of minterms, it follows that a Boolean function is recognized graphically in the map
from the area enclosed by those squares whose minterms are included in the function
...
By recognizing various patterns, the user can derive alternative algebraic
expressions for the same function, from which the simplest can be selected
...
It will be assumed that the simplest algebraic
expression is an algebraic expression with a minimum number of terms and with the
smallest possible number of literals in each term
...
We will see subsequently that the simplest expression is not unique: It is sometimes
possible to find two or more expressions that satisfy the minimization criteria
...


Two-Variable K-Map
The two-variable map is shown in Fig
...
1(a)
...
The map is redrawn in
(b) to show the relationship between the squares and the two variables x and y
...
Variable x
appears primed in row 0 and unprimed in row 1
...

If we mark the squares whose minterms belong to a given function, the two-variable
map becomes another useful way to represent any one of the 16 Boolean functions of
two variables
...
3
...
Since xy is equal to
m3, a 1 is placed inside the square that belongs to m3
...
3
...
These squares
are found from the minterms of the function:
m1 + m2 + m3 = xЈy + xyЈ + xy = x + y
y
x

y

0
m0

m0

m1

m2

m3

0

xЈyЈ
m2

(a)

FIGURE 3
...
2
y
0
m0

x

1

y

m1

0

1

m0

0
m3

1

1
m2

1

x

y

m1

0
m2

x

75

y

y
x

The Map Method

1

m3

1

1

x
(b) x ϩ y

(a) xy

FIGURE 3
...
In each example, the minterms at which the function is asserted are
marked with a 1
...
3
...
There are eight minterms for three binary
variables; therefore, the map consists of eight squares
...
6)
...
The map drawn in part (b) is marked with numbers in each row and
each column to show the relationship between the squares and the three variables
...
When these two
numbers are concatenated, they give the binary number 101, whose decimal equivalent
is 5
...
Note that there are four squares in which each variable is equal to 1
and four in which each is equal to 0
...
3
Three-variable K-map

(b)

10
m2

xЈyzЈ
m6

xyzЈ

76

Chapter 3

Gate-Level Minimization

squares and primed in the latter
...

To understand the usefulness of the map in simplifying Boolean functions, we must
recognize the basic property possessed by adjacent squares: Any two adjacent squares
in the map differ by only one variable, which is primed in one square and unprimed in
the other
...
Variable y is primed in
m5 and unprimed in m7, whereas the other two variables are the same in both squares
...
To clarify this concept, consider the sum of two adjacent squares such as m5 and m7:
m5 + m7 = xyЈz + xyz = xz(yЈ + y) = xz
Here, the two squares differ by the variable y, which can be removed when the sum of
the two minterms is formed
...
The next four examples explain the procedure for minimizing
a Boolean function with a K-map
...
1
Simplify the Boolean function
F (x, y, z) = ⌺(2, 3, 4, 5)
First, a 1 is marked in each minterm square that represents the function
...
3
...

The next step is to find possible adjacent squares
...
The upper right rectangle represents the area
enclosed by xЈy
...
Similarly, the lower
left rectangle represents the product term xyЈ
...


x

y

yz
00
m0

01
m1

m3

0
1

xyЈ

10
m2

1
m4

x

xЈy

11

m5

1

m7

1
m6

1
z

FIGURE 3
...
1, F (x, y, z) = ⌺(2, 3, 4, 5) = xЈy + xyЈ

Section 3
...
The logical sum of these two product terms gives the simplified
expression
F = xЈy + xyЈ
■
In certain cases, two squares in the map are considered to be adjacent even though
they do not touch each other
...
3
...
This difference can be readily verified
algebraically:
m0 + m2 = xЈyЈzЈ + xЈyzЈ = xЈzЈ(yЈ + y) = xЈzЈ
m4 + m6 = xyЈzЈ + xyzЈ = xzЈ + ( yЈ + y) = xzЈ
Consequently, we must modify the definition of adjacent squares to include this and
other similar cases
...


EXAMPLE 3
...
3
...
There are four squares marked with 1’s,
one for each minterm of the function
...
The remaining two squares with 1’s are also adjacent by the new definition
...
The simplified function then becomes
F = yz + xzЈ

x

y

yz
00
m0

01

11

m1

m3

0

xyЈzЈ

1

yz

1
m4

x

10
m2

m5

m7

m6

1

1

1

z

xyzЈ

Note: xyЈzЈ ϩ xyzЈ ϭ xzЈ

FIGURE 3
...
2, F (x, y, z) = ⌺(3, 4, 6, 7) = yz + xzЈ

■

78

Chapter 3

Gate-Level Minimization

Consider now any combination of four adjacent squares in the three-variable map
...
As an example, the logical sum of the four adjacent
minterms 0, 2, 4, and 6 reduces to the single literal term zЈ:
m0 + m2 + m4 + m6 = xЈyЈzЈ + xЈyzЈ + xyЈzЈ + xyzЈ
= xЈzЈ(yЈ + y) + xzЈ(yЈ + y)
= xЈzЈ + xzЈ = zЈ(xЈ + x) = zЈ
The number of adjacent squares that may be combined must always represent a
number that is a power of two, such as 1, 2, 4, and 8
...

One square represents one minterm, giving a term with three literals
...

Four adjacent squares represent a term with one literal
...


EXAMPLE 3
...
3
...
First, we combine the four adjacent squares in the
first and last columns to give the single literal term zЈ
...
This is not only permissible, but rather desirable, because the two adjacent squares
give the two-literal term xyЈ and the single square represents the three-literal minterm
xyЈz
...
6
Map for Example 3
...
2

The Map Method

79

If a function is not expressed in sum-of-minterms form, it is possible to use the map to
obtain the minterms of the function and then simplify the function to an expression with a
minimum number of terms
...
Each product term can be plotted in the map in one, two,
or more squares
...


EXAMPLE 3
...

(b) Find the minimal sum-of-products expression
...
Three product terms in the expression have two literals
and are represented in a three-variable map by two squares each
...
3
...
Note that, in marking
1’s in the squares, it is possible to find a 1 already placed there from a preceding term
...
Square
011 is common with the first term, AЈC, though, so only one 1 is marked in it
...
The function has
a total of five minterms, as indicated by the five 1’s in the map of Fig
...
7
...
The function can be expressed in
sum-of-minterms form as
F (A, B, C ) = ⌺(1, 2, 3, 5, 7)
The sum-of-products expression, as originally given, has too many terms
...
7
Map of Example 3
...
3

Chapter 3

Gate-Level Minimization

F O U R - VA R I A B L E K - M A P
The map for Boolean functions of four binary variables (w, x, y, z) is shown in Fig
...
8
...
3
...
In Fig
...
8(b),
the map is redrawn to show the relationship between the squares and the four variables
...
The minterm corresponding to
each square can be obtained from the concatenation of the row number with the column
number
...

Thus, the square in the third row and second column represents minterm m13
...
Adjacent squares are defined to be squares
next to each other
...
For example, m0 and m2 form adjacent squares, as do m3 and m11
...

Two adjacent squares represent a term with three literals
...

Eight adjacent squares represent a term with one literal
...

No other combination of squares can simplify the function
...


wx

y

yz
00
m0

01

11

m1

m3

10
m2

m0

m1

m3

m2

00 wЈxЈyЈzЈ wЈxЈyЈz wЈxЈyz wЈxЈyzЈ

m4

m5

m7

m6

01 wЈxyЈzЈ wЈxyЈz

m4

m12

m12

m13

m15

m14

11 wxyЈzЈ
w

m8

m9

m11

m10

m8

m5

m7

wЈxyz

m13

m15

wxyz

wxyЈz
m9

m11

10 wxЈyЈzЈ wxЈyЈz

wxЈyz
z

(a)

FIGURE 3
...
3

Four-Variable K-Map

81

EXAMPLE 3
...
The minterms
listed in the sum are marked by 1’s in the map of Fig
...
9
...
The remaining three 1’s on the
right cannot be combined to give a simplified term; they must be combined as two or
four adjacent squares
...
In this example, the top two 1’s on the right are combined
with the top two 1’s on the left to give the term wЈzЈ
...
We are now left with a square marked by 1 in the third
row and fourth column (square 1110)
...
These squares make up the two middle rows and the two end
columns, giving the term xzЈ
...
9
Map for Example 3
...
6
Simplify the Boolean function
F = AЈBЈCЈ + BЈCDЈ + AЈBCDЈ + ABЈCЈ
The area in the map covered by this function consists of the squares marked with 1’s in
Fig
...
10
...
10
Map for Example 3
...
Each term with three literals is represented in the map by two squares
...
The function can be simplified in the map by taking the 1’s in the four corners
to give the term BЈDЈ This is possible because these four squares are adjacent when the

...
The two left-hand 1’s in the top row are combined with the two
1’s in the bottom row to give the term BЈCЈ The remaining 1 may be combined in a two
...
The simplified function is
F = BЈDЈ + BЈCЈ + AЈCDЈ
■

Prime Implicants
In choosing adjacent squares in a map, we must ensure that (1) all the minterms of the
function are covered when we combine the squares, (2) the number of terms in the
expression is minimized, and (3) there are no redundant terms (i
...
, minterms already
covered by other terms)
...
The procedure for combining squares in the map may be made
more systematic if we understand the meaning of two special types of terms
...
If a minterm in a square is covered by only one prime
implicant, that prime implicant is said to be essential
...
3

Four-Variable K-Map

83

The prime implicants of a function can be obtained from the map by combining all
possible maximum numbers of squares
...
Two adjacent 1’s form a prime
implicant, provided that they are not within a group of four adjacent squares
...
The essential prime implicants are found by looking at each square
marked with a 1 and checking the number of prime implicants that cover it
...

Consider the following four-variable Boolean function:
F( A, B, C, D) = ⌺(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
The minterms of the function are marked with 1’s in the maps of Fig
...
11
...
3
...
One term is essential because there is only one
way to include minterm m0 within four adjacent squares
...
Similarly, there is only one way that minterm m5 can be combined with four
adjacent squares, and this gives the second term BD
...
The three minterms that were omitted from the partial map
(m3, m9, and m11) must be considered next
...
11(b) shows all possible ways that the three minterms can be covered with
prime implicants
...
Minterm m9 can be covered with either AD or ABЈ
...
The simplified expression is obtained
from the logical sum of the two essential prime implicants and any two prime implicants
C
AB

CD

00

m0

m1

m4

m5

m12

m13

m8

10

00

m9

m6

m15

B

1

m5

m8

m13

m6

m15

m14

1

m9

1

1

1

1

10

1

10
m2

m7

1
m12

A

m3

1

11
m10

11

1

01

1
m11

01
m1

m4

AD
m14

C
00

m0

CD

1

1

CD

AЈBЈCDЈ

m2

m7

1

11
A

m3

AB

10
1

01

BD

11

1

00
AЈBЈCЈDЈ

01

m11

1

1

m10

1

ABЈCDЈ
ABЈCЈDЈ

D

D

Note: AЈBЈCЈDЈ ϩ AЈBЈCDЈ ϭ AЈBЈDЈ
ABЈCЈDЈ ϩ ABЈCDЈ ϭ ABЈDЈ
AЈBЈDЈ ϩ ABЈDЈ ϭ BЈDЈ
(a) Essential prime implicants
BD and BЈDЈ

FIGURE 3
...
There are four possible ways that the function can
be expressed with four product terms of two literals each:
F =
=
=
=

BD
BD
BD
BD

+
+
+
+

BЈDЈ
BЈDЈ
BЈDЈ
BЈDЈ

+
+
+
+

CD + AD
CD + ABЈ
BЈC + AD
BЈC + ABЈ

The previous example has demonstrated that the identification of the prime implicants in
the map helps in determining the alternatives that are available for obtaining a simplified
expression
...
The simplified expression is obtained
from the logical sum of all the essential prime implicants, plus other prime implicants
that may be needed to cover any remaining minterms not covered by the essential prime
implicants
...


Five-Variable Map
Maps for more than four variables are not as simple to use as maps for four or fewer
variables
...

When the number of variables becomes large, the number of squares becomes excessive
and the geometry for combining adjacent squares becomes more involved
...


3
...
With a minor modification, the product-of-sums
form can be obtained
...
The 1’s placed in the squares of the
map represent the minterms of the function
...
From this
observation, we see that the complement of a function is represented in the map by
the squares not marked by 1’s
...
e
...
The complement of FЈ gives us back the function F in product-of-sums form (a consequence of DeMorgan’s theorem)
...
The best way to show this is by example
...
4

Product-of-Sums Simplification

85

EXAMPLE 3
...
3
...
The
squares marked with 0’s represent the minterms not included in F and therefore denote
the complement of F
...
4), we obtain the simplified function in productof-sums form:
(b) F = (AЈ + BЈ) (CЈ + DЈ) (BЈ + D)
■
The gate-level implementation of the simplified expressions obtained in Example 3
...
3
...
The sum-of-products expression is implemented in (a) with a group of
AND gates, one for each AND term
...
The same function is implemented in (b) in its product-of-sums
C
AB

CD

00

m0

00
BCЈDЈ

m1

m4

m8

10

m7

m13

0

BCDЈ

m6

0
B

m14

0
m11

1

CD
1

0
m15

m9

1

10
m2

0

1

0

11

m3

m5

0
m12

11

1

1

01

A

01

0
m10

0

1

AB

D
Note: BCЈDЈ ϩ BCDЈ ϭ BDЈ

FIGURE 3
...
7, F (A, B, C, D) = ⌺(0,1, 2, 5, 8, 9,10) = BЈDЈ + BЈCЈ + AЈCЈD =
(AЈ + BЈ)(CЈ + DЈ)(BЈ + D)

86

Chapter 3

Gate-Level Minimization

BЈ

AЈ

DЈ

BЈ

CЈ

F
CЈ

F

DЈ

AЈ
D

D
(a) F ϭ BЈDЈ ϩ BЈCЈ ϩ AЈCЈD

(b) F ϭ (AЈ ϩ BЈ) (CЈ ϩ DЈ) (BЈ ϩ D)

FIGURE 3
...
7
Table 3
...
The outputs of the OR gates are
connected to the inputs of a single AND gate
...
The configuration pattern established in Fig
...
13 is the general form by which any Boolean function
is implemented when expressed in one of the standard forms
...
Either configuration forms two levels of gates
...
The two-level implementation may not be practical, depending on the number
of inputs to the gates
...
7 showed the procedure for obtaining the product-of-sums simplification when the function is originally expressed in the sum-of-minterms canonical form
...
Consider, for example, the truth table that defines the
function F in Table 3
...
In sum-of-minterms form, this function is expressed as
F (x, y, z) = ⌺(1, 3, 4, 6)

Section 3
...
14
Map for the function of Table 3
...
The map for this function is shown in Fig
...
14
...
The
remaining squares are marked by 0’s
...
Once the 1’s and 0’s are marked, the function can be
simplified in either one of the standard forms
...
6)
...
For example, the
function
F = (AЈ + BЈ + CЈ)(B + D)
can be entered into the map by first taking its complement, namely,
FЈ = ABC + BЈDЈ

88

Chapter 3

Gate-Level Minimization

and then marking 0’s in the squares representing the minterms of FЈ
...


3
...
The function is equal to 0 for the rest of
the minterms
...
In practice, in some applications the function
is not specified for certain combinations of the variables
...
Functions that have unspecified outputs for
some input combinations are called incompletely specified functions
...
For this reason, it is customary to call the unspecified minterms of a function
don’t-care conditions
...

A don’t-care minterm is a combination of variables whose logical value is not specified
...
Likewise, putting a 0 on the
square requires the function to be 0
...
Thus, an X inside a square in the map indicates that we don’t care
whether the value of 0 or 1 is assigned to F for the particular minterm
...
When simplifying the function, we can choose
to include each don’t-care minterm with either the 1’s or the 0’s, depending on which
combination gives the simplest expression
...
8
Simplify the Boolean function
F (w, x, y, z) = ⌺(1, 3, 7, 11, 15)
which has the don’t-care conditions
d (w, x, y, z) = ⌺(0, 2, 5)
The minterms of F are the variable combinations that make the function equal to 1
...
The map
simplification is shown in Fig
...
15
...
To get the simplified expression in sum-of-products form, we must include all five 1’s in the map, but we may or may
not include any of the X’s, depending on the way the function is simplified
...
The remaining minterm, m1, can be combined

Section 3
...
15
Example with don’t-care conditions

with minterm m3 to give the three-literal term wЈxЈz
...
In
Fig
...
15(a), don’t-care minterms 0 and 2 are included with the 1’s, resulting in the simplified function
F = yz + wЈxЈ
In Fig
...
15(b), don’t-care minterm 5 is included with the 1’s, and the simplified function is now
F = yz + wЈz
Either one of the preceding two expressions satisfies the conditions stated for this
example
...
The choice between 0
and 1 is made depending on the way the incompletely specified function is simplified
...
Consider the two simplified expressions obtained
in Example 3
...
The don’t-care minterms 0, 2, and 5 are treated differently in each expression
...
The second expression includes minterm 5 with the 1’s and leaves minterms 0
and 2 with the 0’s
...
Both cover the specified minterms of the function, but each covers different don’t-care minterms
...

It is also possible to obtain a simplified product-of-sums expression for the function
of Fig
...
15
...


3
...
NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families
...


NAND Circuits
The NAND gate is said to be a universal gate because any logic circuit can be implemented with it
...
This is indeed shown in Fig
...
16
...

The AND operation requires two NAND gates
...
The OR operation is achieved
through a NAND gate with additional inverters in each input
...
The conversion of an algebraic expression from AND, OR, and
complement to NAND can be done by simple circuit manipulation techniques that
change AND–OR diagrams to NAND diagrams
...
Two equivalent graphic symbols for the NAND gate are
shown in Fig
...
17
...
6

NAND and NOR Implementation

Inverter x

xЈ

x
AND y

91

xy

x
(xЈyЈ)Ј ϭ x ϩ y

OR
y

FIGURE 3
...
17
Two graphic symbols for a three-input NAND gate

of an AND graphic symbol followed by a small circle negation indicator referred to as
a bubble
...
The invert-OR symbol for the
NAND gate follows DeMorgan’s theorem and the convention that the negation indicator (bubble) denotes complementation
...
When both symbols are mixed in
the same diagram, the circuit is said to be in mixed notation
...
To see the relationship between a sum-of-products expression and its equivalent NAND implementation, consider the logic diagrams drawn in
Fig
...
18
...
3
...
In Fig
...
18(b), the
AND gates are replaced by NAND gates and the OR gate is replaced by a NAND gate
with an OR-invert graphic symbol
...
Removing the bubbles on the gates of (b) produces the circuit of (a)
...


92

Chapter 3

Gate-Level Minimization
A
B
F
C
D
(a)

A

A

B

B
F

F

C

C

D

D
(b)

(c)

FIGURE 3
...
3
...

In drawing NAND logic diagrams, the circuit shown in either Fig
...
18(b) or (c) is acceptable
...
3
...
The NAND implementation in Fig
...
18(c) can
be verified algebraically
...
9
Implement the following Boolean function with NAND gates:
F (x, y, z) = (1, 2, 3, 4, 5, 7)
The first step is to simplify the function into sum-of-products form
...
3
...
3
...
Note
that input z must have a one-input NAND gate (an inverter) to compensate for the
bubble in the second-level gate
...
 3
...
Here, all the NAND gates are drawn with the same graphic symbol
...

■

Section 3
...
19
Solution to Example 3
...
The procedure for obtaining the
logic diagram from a Boolean function is as follows:
1
...

2
...
The inputs to each NAND gate are the literals of the term
...

3
...

4
...
However, if the
single literal is complemented, it can be connected directly to an input of the secondlevel NAND gate
...

There are occasions, however, when the design of digital systems results in gating structures
with three or more levels
...
The
function can then be implemented with AND and OR gates
...
Consider, for example, the Boolean function
F = A (CD + B) + BCЈ

94

Chapter 3

Gate-Level Minimization

C
D
B
A

F

B
CЈ
(a) AND–OR gates

C
D
BЈ
A

F

B
CЈ
(b) NAND gates

FIGURE 3
...
The
AND–OR implementation is shown in Fig
...
20(a)
...
The first level has two AND gates
...
A logic diagram with a pattern of alternating levels of AND and OR gates can easily be converted into a NAND circuit
with the use of mixed notation, shown in Fig
...
20(b)
...

The NAND circuit performs the same logic as the AND–OR diagram as long as there are
two bubbles along the same line
...

The general procedure for converting a multilevel AND–OR diagram into an all-NAND
diagram using mixed notation is as follows:
1
...

2
...

3
...
For every bubble that is not compensated
by another small circle along the same line, insert an inverter (a one-input NAND
gate) or complement the input literal
...
6

NAND and NOR Implementation

95

A
BЈ
AЈ
B

F

C
DЈ
(a) AND–OR gates

A
BЈ
AЈ
B

F

CЈ
D
(b) NAND gates

FIGURE 3
...
3
...
The conversion to NAND with mixed notation is presented in Fig
...
21(b) of
the diagram
...
The bubble in the output NAND gate
complements the output value, so we need to insert an inverter gate at the output in
order to complement the signal again and get the original value back
...
Therefore, all procedures and
rules for NOR logic are the duals of the corresponding procedures and rules developed
for NAND logic
...
The implementation of the complement, OR, and AND operations
with NOR gates is shown in Fig
...
22
...
The OR operation requires two NOR
gates, and the AND operation is obtained with a NOR gate that has inverters in each input
...
3
...
The OR-invert
symbol defines the NOR operation as an OR followed by a complement
...
The two symbols
designate the same NOR operation and are logically identical because of DeMorgan’s
theorem
...
22
Logic operations with NOR gates
x
y
z

(x ϩ y ϩ z)Ј
(a) OR-invert

x
y
z

xЈyЈzЈ ϭ (x ϩ y ϩ z)Ј
(b) Invert-AND

FIGURE 3
...
Remember that the simplified product-of-sums expression
is obtained from the map by combining the 0’s and complementing
...
The transformation from
the OR–AND diagram to a NOR diagram is achieved by changing the OR gates to
NOR gates with OR-invert graphic symbols and the AND gate to a NOR gate with an
invert-AND graphic symbol
...
Figure 3
...
Variable E is complemented to compensate for the third bubble at the input
of the second-level gate
...
For the NOR case, we must convert
each OR gate to an OR-invert symbol and each AND gate to an invert-AND symbol
...

The transformation of the AND–OR diagram of Fig
...
21(a) into a NOR diagram is
shown in Fig
...
25
...
7

Other Two-Level Implementations

97

A
B
C
D

F

EЈ

FIGURE 3
...
25
Implementing F = (ABЈ + AЈB)(C + DЈ) with NOR gates

The equivalent AND–OR diagram can be recognized from the NOR diagram by removing all the bubbles
...


3
...

For this reason, NAND and NOR logic implementations are the most important from
a practical point of view
...
This type of logic is called wired logic
...
The wired-AND logic performed
with two NAND gates is depicted in Fig
...
26(a)
...
The
wired-AND gate is not a physical gate, but only a symbol to designate the function
obtained from the indicated wired connection
...
3
...


98

Chapter 3

Gate-Level Minimization

A
B

A
B
F ϭ [(A ϩ B) (C ϩ D)]Ј

F ϭ (AB ϩ CD)Ј
C
D

C
D

(a) Wired-AND in open-collector
TTL NAND gates
...
26
Wired logic
(a) Wired-AND logic with two NAND gates
(b) Wired-OR in emitter-coupled logic (ECL) gates

Similarly, the NOR outputs of ECL gates can be tied together to perform a wired-OR
function
...
3
...

A wired-logic gate does not produce a physical second-level gate, since it is just a wire
connection
...
3
...
The first level consists of NAND (or NOR) gates and the
second level has a single AND (or OR) gate
...


Nondegenerate Forms
It will be instructive from a theoretical point of view to find out how many two-level combinations of gates are possible
...
If we assign one type of gate for the first level and one type for the second level, we
find that there are 16 possible combinations of two-level forms
...
) Eight of these
combinations are said to be degenerate forms because they degenerate to a single operation
...
The output of the circuit is merely the AND function of all input variables
...
The eight nondegenerate forms are as follows:
AND–OR

OR–AND

NAND–NAND

NOR–NOR

NOR–OR

NAND–AND

OR–NAND

AND–NOR

Section 3
...

The second gate listed is a single gate placed in the second level
...

The AND–OR and OR–AND forms are the basic two-level forms discussed in
Section 3
...
The NAND–NAND and NOR–NOR forms were presented in Section 3
...

The remaining four forms are investigated in this section
...
Both perform the AND–OR–INVERT function, as shown in Fig
...
27
...
It implements the function
F = (AB + CD + E)Ј
By using the alternative graphic symbol for the NOR gate, we obtain the diagram of
Fig
...
27(b)
...
Now we move the bubble from
the input terminal of the second-level gate to the output terminals of the first-level gates
...

Alternatively, the inverter can be removed, provided that input E is complemented
...
3
...
3
...

An AND–OR implementation requires an expression in sum-of-products form
...
Therefore, if the
complement of the function is simplified into sum-of-products form (by combining the 0’s
in the map), it will be possible to implement FЈ with the AND–OR part of the function
...
27
AND–OR–INVERT circuits, F = (AB + CD + E )Ј

(c) NAND–AND

100

Chapter 3

Gate-Level Minimization

generate the output F of the function
...


OR–AND–INVERT Implementation
The OR–NAND and NOR–OR forms perform the OR–AND–INVERT function, as
shown in Fig
...
28
...
It implements the function
F = 3 (A + B)(C + D)E 4Ј
By using the alternative graphic symbol for the NAND gate, we obtain the diagram
of Fig
...
28(b)
...
3
...
The circuit of Fig
...
28(c) is a NOR–OR form and was shown in Fig
...
26 to implement the OR–AND–
INVERT function
...
If the complement of the function is simplified into that form, we can implement
FЈ with the OR–AND part of the function
...

,

Tabular Summary and Example
Table 3
...
Because of the INVERT part in each case, it is convenient to
use the simplification of FЈ (the complement) of the function
...
The four 2-level forms invert this function, giving an output that is the
complement of FЈ
...

A
B

A
B

A
B

C
D

F

E

C
D

F

F

E

E
(a) OR–NAND

C
D

(b) OR–NAND

FIGURE 3
...
7

Other Two-Level Implementations

101

Table 3
...


F

Product-of-sums
form by combining
1’s in the map and
then complementing
...


EXAMPLE 3
...
3
...
2
...
The AND–NOR and NAND–AND implementations are shown in Fig
...
29(b)
...
The
inverter can be removed if we apply the input variable zЈ instead of z
...
To obtain this expression, we first combine the
1’s in the map:
F = xЈyЈzЈ + xyzЈ
Then we take the complement of the function:
FЈ = (x + y + z)(xЈ + yЈ + z)

102

Chapter 3

Gate-Level Minimization

x

y

yz
00
m0

m4

x

m3

0

10
m2

0

m5

0

1

11

m1

1

0
xЈyЈzЈ

01

m7

0

m6

0

F = xЈyЈzЈ + xyzЈ
FЈ = xЈy + xyЈ + z

0
1

xyzЈ

z
(a) Map simplification in sum of products

xЈ

xЈ

y

y

x

x
F

yЈ

z

F

yЈ

z
NAND–AND

AND–NOR
(b) F ϭ (xЈy ϩ xyЈ ϩ z)Ј

x
y
z

x
y
z
F

xЈ
yЈ
z

F
xЈ
yЈ
z

OR–NAND

NOR–OR
(c) F ϭ [(x ϩ y ϩ z) (xЈ ϩ yЈ ϩ z)]Ј

FIGURE 3
...
From this expression, we can implement the
function in the OR–NAND and NOR–OR forms, as shown in Fig
...
29(c)
...
8

3
...
e
...
The exclusiveNOR, also known as equivalence, performs the following Boolean operation:
(x { y)Ј = xy + xЈyЈ
The exclusive-NOR is equal to 1 if both x and y are equal to 1 or if both are equal to 0
...
Also, it can be shown that the exclusive-OR operation is both commutative and associative; that is,
A{B = B{A
and
(A { B) { C = A { (B { C) = A { B { C
This means that the two inputs to an exclusive-OR gate can be interchanged without
affecting the operation
...
This would imply the possibility of using exclusive-OR gates with
three or more inputs
...
In fact, even a two-input function is usually constructed with other
types of gates
...
3
...
Figure 3
...
The first NAND
gate performs the operation (xy)Ј = (xЈ + yЈ)
...
30
Exclusive-OR implementations

Only a limited number of Boolean functions can be expressed in terms of exclusive-OR
operations
...
It is particularly useful in arithmetic operations and error detection and correction circuits
...
In particular, the three-variable case can be converted to a Boolean expression as follows:
A { B { C = (ABЈ + AЈB)CЈ + (AB + AЈBЈ)C
= ABЈCЈ + AЈBCЈ + ABC + AЈBЈC
= ⌺(1, 2, 4, 7)
The Boolean expression clearly indicates that the three-variable exclusive-OR function is
equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1
...
As a
consequence, the multiple-variable exclusive-OR operation is defined as an odd function
...
8

Exclusive-OR Function

105

The Boolean function derived from the three-variable exclusive-OR operation is
expressed as the logical sum of four minterms whose binary numerical values are 001, 010,
100, and 111
...
The remaining four
minterms not included in the function are 000, 011, 101, and 110, and they have an even
number of 1’s in their binary numerical values
...

The definition of an odd function can be clarified by plotting it in a map
...
31(a)
shows the map for the three-variable exclusive-OR function
...
The odd function is identified from
the four minterms whose binary values have an odd number of 1’s
...
As shown in Fig
...
31(b), the three-variable even
function is equal to 1 when an even number of its variables is equal to 1 (including the
condition that none of the variables is equal to 1)
...
3
...
The complement of an odd function is obtained by replacing the output gate with an exclusive-NOR gate, as shown in Fig
...
32(b)
...
By algebraic manipulation,
we can obtain the sum of minterms for this function:
A { B { C { D = (ABЈ + AЈB) { (CDЈ + CЈD)
= (ABЈ + AЈB)(CD + CЈDЈ) + (AB + AЈBЈ)(CDЈ + CЈD)
= ⌺(1, 2, 4, 7, 8, 11, 13, 14)

A

B

BC
00
m0

01

0

10

m5

00
m0

0

1
m7

1

B

BC

m2

1
m4

A 1

11
m3

m1

A

m6

1
C

(a) Odd function F ϭ A  B  C

11
m3

10
m2

1

1
m4

A 1

01
m1

m7

m5

1

m6

1

C
(b) Even function F ϭ (A  B  C)Ј

FIGURE 3
...
32
Logic diagram of odd and even functions

(b) 3-input even function

106

Chapter 3

AB

Gate-Level Minimization
C

CD
00
m0

01
m1

00
m4

m5

m7

m12

00

m15

m9

m14

B

1

m10

1

1
m5

m12

m7

m6

m13

1
m15

1
m8

10

10
m2

1

11
A

11
m3

1

01
1

m11

01
m1

m4

m6

1
m8

00
m0

1
m13

C

CD

m2

1

1

11
10

m3

AB

10

1

01

A

11

B

m14

1
m9

m11

1

m10

1

D

D

(a) Odd function F ϭ A  B  C  D

(b) Even function F ϭ (A  B  C  D)Ј

FIGURE 3
...
Half of the minterms
have binary numerical values with an odd number of 1’s; the other half of the minterms
have binary numerical values with an even number of 1’s
...
The map of Fig
...
33(a) is a plot of
the four-variable exclusive-OR function
...
The complement of an odd function is an even function
...
3
...


Parity Generation and Checking
Exclusive-OR functions are very useful in systems requiring error detection and correction codes
...
6, a parity bit is used for the purpose of
detecting errors during the transmission of binary information
...
The
message, including the parity bit, is transmitted and then checked at the receiving end
for errors
...
The circuit that generates the parity bit in the transmitter is called
a parity generator
...

As an example, consider a three-bit message to be transmitted together with an
even-parity bit
...
3 shows the truth table for the parity generator
...
The parity
bit P is the output
...
From the truth table, we see that P constitutes an

Section 3
...
3
Even-Parity-Generator Truth Table
Three-Bit Message

Parity Bit

x

y

z

P

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

x
x

y
C

P

y

z
z

P

(a) 3-bit even parity generator

(b) 4-bit even parity checker

FIGURE 3
...
Therefore, P can be expressed as a three-variable exclusive-OR
function:
P = x{y{z
The logic diagram for the parity generator is shown in Fig
...
34(a)
...
Since the information was transmitted with even parity, the
four bits received must have an even number of 1’s
...
The output of the parity checker, denoted by
C, will be equal to 1 if an error occurs—that is, if the four bits received have an odd
number of 1’s
...
4 is the truth table for the even-parity checker
...
The table corresponds to the map of Fig
...
33(a), which

108

Chapter 3

Gate-Level Minimization
Table 3
...
The parity checker can be implemented with exclusiveOR gates:
C = x{y{z{P
The logic diagram of the parity checker is shown in Fig
...
34(b)
...
3
...
This is
because z { 0 = z, causing the value of z to pass through the gate unchanged
...

It is obvious from the foregoing example that parity generation and checking circuits
always have an output function that includes half of the minterms whose numerical values
have either an odd or even number of 1’s
...
A function with an even number of 1’s is the complement of an
odd function
...


3
...

For anything else (i
...
, a practical circuit), designers use computer-based design tools
...
9

Hardware Description Language

109

leverage the creativity and the effort of a designer and reduce the risk of producing a
flawed design
...

A hardware description language (HDL) is a computer-based language that describes
the hardware of digital systems in a textual form
...
It can be used to represent logic diagrams,
truth tables, Boolean expressions, and complex abstractions of the behavior of a digital
system
...

For example, an HDL description of an AND gate describes how the logic value of the
gate’s output is determined by the logic values of its inputs
...
The language content can be stored,
retrieved, edited, and transmitted easily and processed by computer software in
an efficient manner
...

Design entry creates an HDL-based description of the functionality that is to be
implemented in hardware
...
The HDL model may also represent a partition of a larger
circuit into smaller interconnected and interacting functional units
...
A simulator interprets the HDL description and either produces readable output,
such as a time-ordered sequence of input and output signal values, or displays waveforms of the signals
...
Simulation detects functional errors in a design without
having to physically create and operate the circuit
...
The stimulus (i
...
, the logic values of the inputs to a circuit) that tests the functionality of the design
is called a test bench
...
An alternative and more complex approach relies on
formal mathematical methods to prove that a circuit is functionally correct
...

Logic synthesis is the process of deriving a list of physical components and their
interconnections (called a netlist) from the model of a digital system described in an
HDL
...
Logic synthesis is
similar to compiling a program in a conventional high-level language
...
The database specifies how to fabricate a physical integrated circuit that implements in silicon the functionality described by statements
made in an HDL
...
The design of today’s large, complex circuits is made possible by
logic synthesis software
...
Because each logic gate in a circuit has a propagation delay, a signal
transition at the input of a circuit cannot immediately cause a change in the logic value
of the output of a circuit
...
Timing verification checks each signal path to verify that it is
not compromised by propagation delay
...

In VLSI circuit design, fault simulation compares the behavior of an ideal circuit with
the behavior of a circuit that contains a process-induced flaw
...
A circuit with a fault will not exhibit the same functionality as a fault-free circuit
...
These test patterns will be used to
test fabricated devices to ensure that only good devices are shipped to the customer
...

Companies that design integrated circuits use proprietary and public HDLs
...
VHDL is a Department of Defense–mandated language
...
)
Verilog began as a proprietary HDL of Cadence Design Systems, but Cadence transferred control of Verilog to a consortium of companies and universities known as Open
Verilog International (OVI) as a step leading to its adoption as an IEEE standard
...
Because Verilog is an easier language than
VHDL to describe, learn, and use, we have chosen it for this book
...
Our emphasis
will be on the modeling, verification, and synthesis (both manual and automated) of
Verilog models of circuits having specified behavior
...
We will address only those features of Verilog, including the latest standard, that support our discussion of HDL-based design methodology
for integrated circuits
...
9

Hardware Description Language

111

Module Declaration
The language reference manual for the Verilog HDL presents a syntax that describes
precisely the constructs that can be used in the language
...
Keywords
are predefined lowercase identifiers that define the language constructs
...
For clarity,
keywords will be displayed in boldface in the text in all examples of code and wherever it is appropriate to call attention to their use
...
Multiline comments begin with /* and terminate
with */
...
Verilog is case sensitive, which means that uppercase and lowercase letters are
distinguishable (e
...
, not is not the same as NOT)
...
endmodule
...
It is declared by the keyword module and
must always be terminated by the keyword endmodule
...
Each type of description can be developed in
Verilog
...

The HDL description of the circuit of Fig
...
35 is shown in HDL Example 3
...
The
first line of text is a comment (optional) providing useful information to the reader
...
The
keyword module is followed by a name and a list of ports
...
Identifiers are names given to modules, variables (e
...
, a
signal), and other elements of the language so that they can be referenced in the design
...
Identifiers are composed of alphanumeric characters and the underscore (_), and are case sensitive
...


A
B

C

G1

G2

FIGURE 3
...
1 (Combinational Logic Modeled with Primitives)
// Verilog model of circuit of Figure 3
...
IEEE 1364–1995 Syntax
module Simple_Circuit (A, B, C, D, E);
output
D, E;
input
A, B, C;
wire
w1;
and
not
or
endmodule

G1 (w1, A, B); // Optional gate instance name
G2 (E, C);
G3 (D, w1, E);

The port list of a module is the interface between the module and its environment
...
The logic values of
the inputs to a circuit are determined by the environment; the logic values of the outputs
are determined within the circuit and result from the action of the inputs on the circuit
...
The statement is terminated with a semicolon (;)
...
Next, the keywords input and output specify which of the ports are
inputs and which are outputs
...
The circuit in
this example has one internal connection, at terminal w1, and is declared with the keyword wire
...
The elements of the list
are referred to as instantiations of a gate, each of which is referred to as a gate instance
...
) followed by
the gate output and inputs separated by commas and enclosed within parentheses
...
For example, the
OR gate of the schematic is represented by the or primitive, is named G3, and has output D and inputs w1 and E
...
) The module description ends
with the keyword endmodule
...

It is important to understand the distinction between the terms declaration and instantiation
...
Its declaration specifies the input–output behavior
of the hardware that it represents
...
Primitives
are used (i
...
, instantiated), just as gates are used to populate a printed circuit board
...
Note that Simple_Circuit is not a computational model like those developed in
an ordinary programming language: The sequential ordering of the statements instantiating gates in the model has no significance and does not specify a sequence of computations
...
Simple_Circuit describes what primitives
form a circuit and how they are connected
...
9

Hardware Description Language

113

Table 3
...

Thus, an HDL-based model can be used to simulate the circuit that it represents
...
When an HDL model of a circuit is simulated, it is sometimes necessary to specify the amount of delay from the input to the output of its gates
...
The numbers associated with time delays in Verilog are dimensionless
...
(Compiler directives start with the (Ժ) back quote, or grave accent, symbol
...
An example of a timescale directive is
Ժtimescale 1ns/100ps
The first number specifies the unit of measurement for time delays
...
1 ns
...
 Our examples will use only the default time unit
...
2 repeats the description of the simple circuit of Example 3
...
The and, or, and not gates have a time
delay of 30, 20, and 10 ns, respectively
...
5 (calculated
by hand or generated by a simulator)
...
The output of the AND gate at w1 changes from 0 to 1 after a 30-ns
delay
...
In both cases, the change in the output of the OR gate results
from a change in its inputs 20 ns earlier
...


114

Chapter 3

Gate-Level Minimization

HDL Example 3
...
An HDL description that provides
the stimulus to a design is called a test bench
...
12
...
HDL Example 3
...
(Note the distinguishing name Simple_Circuit_prop_
delay
...
Note that the test bench (t_Simple_
Circuit_prop_delay) has no input or output ports, because it does not interact with its
environment
...
Within the test bench, the inputs to the circuit are declared with keyword
reg and the outputs are declared with the keyword wire
...
Every instantiation of a module
must include a unique instance name
...
3 (Test Bench)
// Test bench for Simple_Circuit_prop_delay
module t_Simple_Circuit_prop_delay;
wire
D, E;
reg
A, B, C;
Simple_Circuit_prop_delay M1 (A, B, C, D, E); // Instance name required
initial
begin
A = 1'b0; B = 1'b0; C = 1'b0;
#100 A = 1'b1; B = 1'b1; C = 1'b1;
end
initial #200 $finish;
endmodule

Section 3
...
0 ns

58
...
0 ns

115

174
...
36
Simulation output of HDL Example 3
...
(The interaction between the signal generators of the stimulus module and the instantiated circuit module is illustrated in Fig
...
36
...
The waveforms of the input signals are abstractly modeled
(generated) by Verilog statements specifying waveform values and transitions
...
The initial statements are commonly used to describe
waveforms in a test bench
...
The action
specified by the statements begins when the simulation is launched, and the statements
are executed in sequence, left to right, from top to bottom, by a simulator in order to
provide the input to the circuit
...
(A, B, and C are each set to 1Јb0,
which signifies one binary digit with a value of 0
...
After another 100 ns, the simulation terminates at time 200 ns
...
If a
statement is preceded by a delay value (e
...
, #100), the simulator postpones executing the
statement until the specified time delay has elapsed
...
36
...
The inputs A, B, and C change from 0 to 1 after 100
ns
...
Output E goes from 1 to 0 at 110 ns
...
5
...
To distinguish arithmetic operators from logical operators, Verilog uses the
symbols (&), (/), and (&) for AND, OR, and NOT (complement), respectively
...
3
...
4 describes a circuit that is specified with the following two Boolean
expressions:
E = A + BC + BЈD
F = BЈC + BCЈDЈ
The equations specify how the logic values E and F are determined by the values of
A, B, C, and D
...
4 (Combinational Logic Modeled with Boolean Equations)
// Verilog model: Circuit with Boolean expressions
module Circuit_Boolean_CA (E, F A, B, C, D);
,
output
E, F;
input
A, B, C, D;
assign E ϭ A || (B && C) || ((!B) && D);
assign F ϭ ((!B) && C) || (B && (!C) && (!D));
endmodule

The circuit has two outputs E and F and four inputs A, B, C, and D
...
The values of E and F during simulation are
determined dynamically by the values of A, B, C, and D
...
When this happens, the simulator updates the values of E and F
...
The
mechanism acts just like combinational logic, has a gate-level equivalent circuit, and is
referred to as implicit combinational logic
...
A third
alternative is to describe combinational logic with a truth table
...
, are defined by
the system and are referred to as system primitives
...
) The user can create additional primitives by defining them in
tabular form
...

One way of specifying a digital circuit in tabular form is by means of a truth table
...
endmodule
...
endprimitive
...


Section 3
...
5 defines a UDP with a truth table
...

• There can be only one output, and it must be listed first in the port list and declared
with keyword output
...
The order in which they are listed in the input
declaration must conform to the order in which they are given values in the table that
follows
...

• The values of the inputs are listed in order, ending with a colon (:)
...

• The declaration of a UDP ends with the keyword endprimitive
...
5 (User-Defined Primitive)
// Verilog model: User-defined Primitive
primitive UDP_02467 (D, A, B, C);
output D;
input A, B, C;
//Truth table for D 5 f (A, B, C) 5 ⌺(0, 2, 4, 6, 7);
table
//
A
B
C
:
D
// Column header comment
0
0
0
:
1;
0
0
1
:
0;
0
1
0
:
1;
0
1
1
:
0;
1
0
0
:
1;
1
0
1
:
0;
1
1
0
:
1;
1
1
1
:
1;
endtable
endprimitive
// Instantiate primitive
// Verilog model: Circuit instantiation of Circuit_UDP_02467
module Circuit_with_UDP_02467 (e, f, a, b, c, d);
output
e, f;
input
a, b, c, d
UDP_02467
and
endmodule

(e, a, b, c);
(f, e, d);

// Option gate instance name omitted

118

Chapter 3

Gate-Level Minimization
A
B

UDP_02467

E

C
F

D

FIGURE 3
...
The system recognizes the variables by the order in which they are listed
in the input declaration
...
For example,
the declaration
Circuit _with _UDP_ 02467 (E, F, A, B, C, D);
will produce a circuit that implements the hardware shown in Figure 3
...

Although Verilog HDL uses this kind of description for UDPs only, other HDLs and
computer-aided design (CAD) systems use other procedures to specify digital circuits
in tabular form
...
None of Verilog’s predefined primitives describes sequential
logic
...
So the
columns are organized as inputs : state : next state
...
A more detailed presentation
of Verilog HDL can be found in the next chapter
...
12 to continue with this subject
...
)
3
...
2

Simplify the following Boolean functions, using three-variable maps:
(a)* F (x, y, z) = ⌺(0, 1, 5, 7)
(b)* F (x, y, z) = ⌺(1, 2, 3, 6, 7)

(c) F 1x, y, z2 = ⌺10, 1, 2, 3, 52

(d) F 1x, y, z2 = ⌺11, 2, 3, 72

(c) F 1x, y, z2 = ⌺12, 3, 4, 52
3
...
4

119

Simplify the following Boolean functions, using Karnaugh maps:
(a)* F (x, y, z) = ⌺(2, 3, 6, 7)
(c)* F (A, B, C, D) = ⌺(3, 7, 11, 13, 14, 15)

(d)* F (w, x, y, z) = ⌺(2, 3, 12, 13, 14, 15)

(e) F (w, x, y, z) = ⌺ (11, 12, 13, 14, 15)
3
...
6

Simplify the following Boolean expressions, using four-variable maps:
(a)* AЈBЈ CЈ DЈ + ACЈDЈ + BЈ CDЈ + AЈ BCD + BCЈ D
(b)* xЈz + wЈ xyЈ + w(xЈy + xyЈ)
(c) AЈBЈCЈD + ABЈD + AЈBCЈ + ABCD + ABЈC
(d) AЈBЈCЈDЈ + BCЈD + AЈCЈD + AЈBCD + ACDЈ

3
...
8

Find the minterms of the following Boolean expressions by first plotting each function in
a map:
(a)* xy + yz + xyЈ z
(b)* CЈD + ABCЈ + ABDЈ + AЈBЈD
(c) wyz + wЈxЈ + wxzЈ
(d) AЈB + AЈCD + BЈCD + BCЈDЈ

3
...
10 Simplify the following Boolean functions by first finding the essential prime implicants:
(a) F 1w, x, y, z2 = ⌺ 10, 2, 5, 7, 8, 10, 12, 13, 14, 152
(b) F (A, B, C, D) = ⌺(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c)* F (A, B, C, D) = ⌺(1, 3, 4, 5, 10, 11, 12, 13, 14, 15)
(d) F 1w, x, y, z2 = ⌺ 10, 1, 4, 5, 6, 7, 9, 11, 14, 152
(e) F 1A, B, C, D2 = ⌺ 10, 1, 3, 7, 8, 9, 10, 13, 152
(f)

F 1w, x, y, z2 = ⌺ 10, 1, 2, 4, 5, 6, 7, 10, 152

3
...

F 1x, y, z2 = ⌺ 10, 1, 2, 5, 8, 10, 132

120

Chapter 3

Gate-Level Minimization

3
...
13 Simplify the following expressions to (1) sum-of-products and (2) products-of-sums:
(a)*
(b)
(c)
(d)

xЈ zЈ + yЈ zЈ + yzЈ + xy
ACDЈ + CЈD + ABЈ + ABCD
1AЈ + B + DЈ2 1AЈ + BЈ + CЈ2 1AЈ + BЈ + C2 1BЈ + C + DЈ2
BCDЈ + ABCЈ + ACD

3
...
15 Simplify the following Boolean function F, together with the don’t-care conditions d, and
then express the simplified function in sum-of-minterms form:
(a) F 1x, y, z2 = ⌺10, 1, 4, 5, 62

(b)* F (A, B, C, D) = ⌺(0, 6, 8, 13, 14)

d1x, y, z2 = ⌺12, 3, 72

d (A, B, C, D) = ⌺(2, 4, 10)

(c) F 1A, B, C, D2 = ⌺15, 6, 7, 12, 14, 15,2 (d) F 1A, B, C, D2 = ⌺14, 12, 7, 2, 10,2
d1A, B, C, D2 = ⌺13, 9, 11, 152

d1A, B, C, D2 = ⌺10, 6, 82

3
...
17* Draw a NAND logic diagram that implements the complement of the following function:
F 1A, B, C, D2 = ⌺ 10, 1, 2, 3, 6, 10, 11, 142
3
...
19 Simplify the following functions, and implement them with two-level NOR gate circuits:
(a)* F = wxЈ + yЈ zЈ + wЈ yzЈ
(b) F 1w, x, y, z2 = ⌺ 10, 3, 12, 152
(c)

F (x, y, z) = [(x + y)(x = z)]Ј

3
...
21 Draw the multiple-level NAND circuit for the following expression:
w 1x + y + z2 + xyz
3
...
4
...

3
...


Problems

121

3
...
25 List the eight degenerate two-level forms and show that they reduce to a single operation
...

3
...
27 Show that the dual of the exclusive-OR is also its complement
...
28 Derive the circuits for a three-bit parity generator and four-bit parity checker using an odd
parity bit
...
29 Implement the following four Boolean expressions with three half adders:
D
E
F
G

=
=
=
=

A{B{C
AЈ BC + ABЈ C
ABCЈ + (AЈ + BЈ) C
ABC

3
...
31 Write a Verilog gate-level description of the circuit shown in
(a) Fig
...
20(a)
(b) Fig
...
20(b)
(c) Fig
...
21(a)
(d) Fig
...
21(b)
(e) Fig
...
24
(f) Fig
...
25
3
...
3
...
3
...
3
...
3
...
3
...
3
...
33 The exclusive-OR circuit of Fig
...
30(a) has gates with a delay of 3 ns for an inverter, a 6 ns
delay for an AND gate, and a 8 ns delay for an OR gate
...

(a) Determine the signals at the output of each gate from t = 0 to t = 50 ns
...

(c) Write a stimulus module (i
...
, a test bench similar to HDL Example 3
...

3
...


122

Chapter 3

Gate-Level Minimization

3
...
36 Draw the logic diagram of the digital circuit specified by the following Verilog description:
(a) module Circuit_A (A, B, C, D, F);
input
A, B, C, D;
output
F;
wire
w, x, y, z, a, d;
or
(x, B, C, d);
and
(y, a ,C);
and
(w, z ,B);
and
(z, y, A);
or
(F x, w);
,
not
(a, A);
not
(d, D);
endmodule
(b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1);
output
F1, F2, F3;
input
A0, A1, B0, B1;
nor
(F1, F2, F3);
or
(F2, w1, w2, w3);
and
(F3, w4, w5);
and
(w1, w6, B1);
or
(w2, w6, w7, B0);
and
(w3, w7, B0, B1);
not
(w6, A1);
not
(w7, A0);
xor
(w4, A1, B1);
xnor
(w5, A0, B0);
endmodule
(c) module Circuit_C (y1, y2, y3, a, b);
output y1, y2, y3;
input a, b;
assign y1 = a || b;
and (y2, a, b);
assign y3 = a && b;
endmodule

References

123

3
...

(a) Write a truth table for a four-bit majority function
...

3
...
P3
...


A
t, ns
10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

B
t, ns

C
t, ns
D
t, ns

FIGURE P3
...
38
3
...
g
...
(Hint: Begin by developing a truth table for s and c
...

2
...

4
...

6
...
1997 A Verilog HDL Primer
...


...
D
...
Modeling, Synthesis and Rapid Prototyping with the Verilog HDL
...

Hill, F
...
, and G
...
Peterson
...
Introduction to Switching Theory and Logical Design,
3rd ed
...

IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std
...
1995
...

Karnaugh, M
...
Transactions
of AIEE, Communication and Electronics
...
1953): 593–99
...
1978
...
New York: McGraw-Hill
...

8
...


Gate-Level Minimization

Mano, M
...
and C
...
Kime
...
Logic and Computer Design Fundamentals, 3rd ed
...

McCluskey, E
...
1986
...
Englewood Cliffs, NJ: Prentice-Hall
...
1996
...
Mountain View,
CA: SunSoft Press (a Prentice Hall title)
...
1

INTRODUCTION
Logic circuits for digital systems may be combinational or sequential
...
A combinational circuit performs an operation that can
be specified logically by a set of Boolean functions
...
Their outputs are a function of the
inputs and the state of the storage elements
...
Sequential circuits are the building
blocks of digital systems and are discussed in Chapters 5 and 8
...
2

C O M B I N AT I O N A L C I R C U I T S
A combinational circuit consists of an interconnection of logic gates
...
A block diagram of a combinational circuit is shown in Fig
...
1
...
Each input
and output variable exists physically as an analog signal whose values are interpreted
to be a binary signal that represents logic 1 and logic 0
...
) In many applications, the source and
125

126

Chapter 4

Combinational Logic

n inputs

и
и
и

Combinational
circuit

и
и
и

m outputs

FIGURE 4
...
If the registers are included with the combinational
gates, then the total circuit must be considered to be a sequential circuit
...
For each
possible input combination, there is one possible value for each output variable
...
A combinational circuit also can be described by
m Boolean functions, one for each output variable
...

In Chapter 1, we learned about binary numbers and binary codes that represent discrete
quantities of information
...
The signals can be manipulated in digital logic gates to
perform required functions
...
In Chapter 3, we learned how to simplify Boolean
functions to achieve economical (simpler) gate implementations
...
The solution of some typical
examples will provide a useful catalog of elementary functions that are important for the
understanding of digital systems
...

There are several combinational circuits that are employed extensively in the design
of digital systems
...
They perform specific digital functions commonly needed in the
design of digital systems
...
These components are available in integrated circuits as medium-scale
integration (MSI) circuits
...

The standard cell functions are interconnected within the VLSI circuit in the same way
that they are used in multiple-IC MSI design
...
3

A N A LY S I S P R O C E D U R E
The analysis of a combinational circuit requires that we determine the function that the
circuit implements
...


Section 4
...
The analysis can be performed manually by finding the Boolean
functions or truth table or by using a computer simulation program
...
The diagram of a combinational circuit has logic gates with no
feedback paths or memory elements
...
Feedback paths in a digital circuit define a sequential circuit and must be
analyzed by special methods and will not be considered here
...
If the function of the circuit is
under investigation, then it is necessary to interpret the operation of the circuit from the
derived Boolean functions or truth table
...

To obtain the output Boolean functions from a logic diagram, we proceed as follows:
1
...
Determine the Boolean functions for each gate output
...
Label the gates that are a function of input variables and previously labeled gates
with other arbitrary symbols
...

3
...

4
...

The analysis of the combinational circuit of Fig
...
2 illustrates the proposed procedure
...
The outputs of various gates are labeled with intermediate symbols
...
Output
F2 can easily be derived from the input variables
...
2
Logic diagram for analysis example

If we want to pursue the investigation and determine the information transformation
task achieved by this circuit, we can draw the circuit from the derived Boolean expressions and try to recognize a familiar operation
...
5
...

The derivation of the truth table for a circuit is a straightforward process once the
output Boolean functions are known
...
Determine the number of input variables in the circuit
...

2
...

3
...

4
...


Section 4
...
1
Truth Table for the Logic Diagram of Fig
...
2
A

B

C

F2

FЈ
2

T1

T2

T3

F1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

1
1
1
0
1
0
0
0

0
1
1
1
1
1
1
1

0
0
0
0
0
0
0
1

0
1
1
0
1
0
0
0

0
1
1
0
1
0
0
1

This process is illustrated with the circuit of Fig
...
2
...
1, we form the
eight possible combinations for the three input variables
...
The truth table for FЈ is the comple2
ment of F2
...
The values for T3 are derived from T1 and FЈ :T3 is equal
2
to 1 when both T1 and FЈ are equal to 1, and T3 is equal to 0 otherwise
...

Inspection of the truth table combinations for A, B, C, F1, and F2 shows that it is
identical to the truth table of the full adder given in Section 4
...

Another way of analyzing a combinational circuit is by means of logic simulation
...
But simulation has a very
practical application in verifying that the functionality of a circuit actually matches its
specification
...
12, we demonstrate the logic simulation and verification of
the circuit of Fig
...
2, using Verilog HDL
...
4

DESIGN PROCEDURE
The design of combinational circuits starts from the specification of the design objective
and culminates in a logic circuit diagram or a set of Boolean functions from which the
logic diagram can be obtained
...
From the specifications of the circuit, determine the required number of inputs
and outputs and assign a symbol to each
...
Derive the truth table that defines the required relationship between inputs and
outputs
...
Obtain the simplified Boolean functions for each output as a function of the input
variables
...
Draw the logic diagram and verify the correctness of the design (manually or by
simulation)
...
The input columns are obtained from the 2n binary numbers for the n input
variables
...
The output functions specified in the truth table give the exact definition of the
combinational circuit
...

The output binary functions listed in the truth table are simplified by any available
method, such as algebraic manipulation, the map method, or a computer-based simplification program
...
In a particular application, certain criteria will serve as a guide in
the process of choosing an implementation
...
e
...
Since the importance of each constraint is dictated
by the particular application, it is difficult to make a general statement about what
constitutes an acceptable implementation
...
Then the simplification proceeds with further steps to meet
other performance criteria
...
It is sometimes necessary
to use the output of one system as the input to another
...

Thus, a code converter is a circuit that makes the two systems compatible even though
each uses a different binary code
...
A combinational circuit performs
this transformation by means of logic gates
...

The bit combinations assigned to the BCD and excess-3 codes are listed in Table 1
...
7)
...
4

Design Procedure

131

Table 4
...
We designate the four input binary
variables by the symbols A, B, C, and D, and the four output variables by w, x, y, and
z
...
2
...
7
...
The six bit combinations not listed for the input
variables are don’t-care combinations
...
Therefore, we are
at liberty to assign to the output variables either a 1 or a 0, whichever gives a simpler
circuit
...
4
...
Each one of the four maps represents one of the four outputs of the circuit
as a function of the four input variables
...
The 1’s are obtained
from the truth table by going over the output columns one at a time
...
The six
don’t-care minterms 10 through 15 are marked with an X
...

(See Chapter 3
...
There are various other possibilities for a logic diagram
that implements this circuit
...
  4
...
This manipulation, shown next, illustrates the flexibility obtained with multiple-output systems when

132

Chapter 4

Combinational Logic
C

CD
00
AB
m0

00

11
m3

10

m4

1
m7

m12

m13

X
m8

m9

10

m15

X

m11

1

B

X

X

m7

m6

1

m12

A

m10

m5

1

11

X

m13

m8

m15

X

X
m9

m11

m10

00

AB
m0

01
m1

00
m4

m12

m13

X

1

m9

m11

1

X

m5

01

11
m3

10
m2

00

m6

X

01
m1

m4

1

m15

00
m0

1

X
m8

AB

m2

m7

C

CD

10

1

11
10

m3

m5

01

A

11

1

X

D
y ϭ CD ϩ CЈDЈ
C

CD

X

X

D
z ϭ DЈ

B

m14

X

1

10

10
m2

1

m4

m14

X

11
m3

1

01

m6

01
m1

00

1

m5

1

11

00
m0

m2

1

01

A

01
m1

C

CD
AB

m14

B

m12

X
m10

X

D
x ϭ BЈC ϩ BЈD ϩ BCЈDЈ

11
A

m13

X
m8

10

m7

m6

1
X
m9

1

m15

X

B

m14

X
m11

1

1

1

X
m10

X

D
w ϭ A ϩ BCϩ BD

FIGURE 4
...
4
...
Note that the OR
gate whose output is C + D has been used to implement partially each of three outputs
...
The implementation of Fig
...
4 requires four AND
gates, four OR gates, and one inverter
...
5

Binary Adder–Subtractor

DЈ

D
C

133
z

CD
y

(C ϩD)Ј
C ϩD
B
x

A

w

FIGURE 4
...
Thus, the three-level logic
circuit requires fewer gates, all of which in turn require no more than two inputs
...
5

BINARY ADDER–SUBTRACTOR
Digital computers perform a variety of information-processing tasks
...
The most basic arithmetic
operation is the addition of two binary digits
...
The
first three operations produce a sum of one digit, but when both augend and addend
bits are equal to 1, the binary sum consists of two digits
...
When the augend and addend numbers contain more significant
digits, the carry obtained from the addition of two bits is added to the next higher order
pair of significant bits
...
One that performs the addition of three bits (two significant bits and
a previous carry) is a full adder
...


134

Chapter 4

Combinational Logic

A binary adder–subtractor is a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary numbers
...
The half adder design is carried out first, from
which we develop the full adder
...
The subtraction circuit is included in a complementing
circuit
...
The input variables designate the augend and addend
bits; the output variables produce the sum and carry
...
The truth table for the half
adder is listed in Table 4
...
The C output is 1 only when both inputs are 1
...

The simplified Boolean functions for the two outputs can be obtained directly from
the truth table
...
4
...
It can be also implemented with an exclusive-OR and an AND gate as shown
in Fig
...
5(b)
...

Table 4
...
5
Implementation of half adder

C
(b) S ϭ x  y
C ϭ xy

Section 4
...
After
the least significant bit, addition at each position adds not only the respective bits of the
words, but must also consider a possible carry bit from addition at the previous position
...
It
consists of three inputs and two outputs
...
The third input, z, represents the carry from
the previous lower significant position
...
The two outputs are designated by the symbols S for sum and C for carry
...
The binary
variable C gives the output carry formed by adding the input carry and the bits of the
words
...
4
...
The output variables
are determined from the arithmetic sum of the input bits
...
The S output is equal to 1 when only one input is equal to 1 or when all three
inputs are equal to 1
...

The input and output bits of the combinational circuit have different interpretations
at various stages of the problem
...
On the other hand, the same binary values are considered as variables of
Boolean functions when expressed in the truth table or when the circuit is implemented
with logic gates
...
4
...
The
simplified expressions are
S = xЈyЈz + xЈyzЈ + xyЈzЈ + xyz
C = xy + xz + yz
The logic diagram for the full adder implemented in sum-of-products form is shown
in Fig
...
7
...
4
Full Adder
x

y

z

C

S

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

136

Chapter 4

Combinational Logic
y

yz
x

00
m0

01

0

m3

10

m5

00
m0

m7

01

11

m1

m3

0

1

1

y

yz

m2

1
m4

x 1

11

m1

x

m6

1
m4

x

1

10
m2

m5

1

m7

1

m6

1

z

z

(a) S ϭ xЈyЈz ϩ xЈyzЈ ϩ xyЈzЈ ϩ xyz

1

(b) C ϭ xy ϩ xz ϩ yz

FIGURE 4
...
7
Implementation of full adder in sum-of-products form

in Fig
...
8
...
It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of the next full adder in the chain
...
5
x
y

xy

Binary Adder–Subtractor

(x  y)  z

xy

137

S

(x  y) z

(x  y) z ϩ xy

C

z

FIGURE 4
...
In the former case, the input carry to the least significant position
is fixed at 0
...
9 shows the interconnection of four full-adder (FA) circuits to
provide a four-bit binary ripple carry adder
...
The carries are connected in a chain through the full adders
...
The S outputs generate the required sum bits
...

To demonstrate with a specific example, consider the two binary numbers A = 1011
and B = 0011
...
The input carry C0 in the least significant position
must be 0
...
This value is transferred into the input carry of the full adder that adds the bits
one higher significant position to the left
...
All the carries must be generated for the correct sum bits to appear at
the outputs
...
It can be used in
many applications involving arithmetic operations
...
9
Four-bit adder

by the classical method would require a truth table with 29 = 512 entries, since there
are nine inputs to the circuit
...


Carry Propagation
The addition of two binary numbers in parallel implies that all the bits of the augend
and addend are available for computation at the same time
...
The total propagation time is equal to the propagation
delay of a typical gate, times the number of gate levels in the circuit
...
Since each bit of the sum output depends on the value of the input carry, the
value of Si at any given stage in the adder will be in its steady-state final value only after
the input carry to that stage has been propagated
...
4
...
Inputs A3 and B3 are available as soon as input signals are applied to the adder
...
Similarly, C2 has to wait for C1 and so on down to C0
...

The number of gate levels for the carry propagation can be found from the circuit
of the full adder
...
4
...

The input and output variables use the subscript i to denote a typical stage of the adder
...
These two signals are common to all half adders and depend on
only the input augend and addend bits
...
If there are four full adders in the adder, the output carry C4 would have
2 * 4 = 8 gate levels from C0 to C4
...


Section 4
...
10
Full adder with P and G shown

The carry propagation time is an important attribute of the adder because it limits
the speed with which two numbers are added
...
Since all other arithmetic operations
are implemented by successive additions, the time consumed during the addition process
is critical
...
However, physical circuits have a limit to their
capability
...
There are several techniques for reducing the
carry propagation time in a parallel adder
...

Consider the circuit of the full adder shown in Fig
...
10
...
Pi is called a carry propagate, because it determines
whether a carry into stage i will propagate into stage i + 1 (i
...
, whether an assertion of
Ci will propagate to an assertion of Ci + 1)
...
The three Boolean functions for C1, C2, and C3 are implemented in the carry lookahead generator shown in Fig
...
11
...
This gain in speed of operation is achieved
at the expense of additional complexity (hardware)
...
 4
...

Each sum output requires two exclusive-OR gates
...
The carries
are propagated through the carry lookahead generator (similar to that in Fig
...
11) and
applied as inputs to the second exclusive-OR gate
...
11
Logic diagram of carry lookahead generator

C1

Section 4
...
12
Four-bit adder with carry lookahead

a delay through two levels of gates
...
The two-level circuit for the output carry C4 is not shown
...


Binary Subtractor
The subtraction of unsigned binary numbers can be done most conveniently by means
of complements, as discussed in Section 1
...
Remember that the subtraction A - B can
be done by taking the 2’s complement of B and adding it to A
...
The 1’s complement can be implemented with inverters, and a 1 can be added to
the sum through the input carry
...
13
Four-bit adder–subtractor (with overflow detection)

The circuit for subtracting A - B consists of an adder with inverters placed between
each data input B and the corresponding input of the full adder
...
The operation thus performed becomes A,
plus the 1’s complement of B, plus 1
...

For unsigned numbers, that gives A - B if A Ú B or the 2’s complement of 1B - A2
if A 6 B
...

(See Section 1
...
)
The addition and subtraction operations can be combined into one circuit with one
common binary adder by including an exclusive-OR gate with each full adder
...
4
...
The mode input M controls the operation
...

Each exclusive-OR gate receives input M and one of the inputs of B
...
The full adders receive the value of B, the input carry is 0, and the
circuit performs A plus B
...
The B inputs
are all complemented and a 1 is added through the input carry
...
(The exclusive-OR with output V is for
detecting an overflow
...
Therefore, computers need only one common hardware circuit to handle both types
of arithmetic
...


Section 4
...
This is true for binary or decimal numbers, signed or unsigned
...
Overflow is a problem in digital computers because the number of bits that
hold the number is finite and a result that contains n + 1 bits cannot be accommodated
by an n-bit word
...

The detection of an overflow after the addition of two binary numbers depends on
whether the numbers are considered to be signed or unsigned
...
In the case of signed numbers, two details are important: the leftmost bit
always represents the sign, and negative numbers are in 2’s-complement form
...

An overflow cannot occur after an addition if one number is positive and the other
is negative, since adding a positive number to a negative number produces a result
whose magnitude is smaller than the larger of the two original numbers
...
To see how this
can happen, consider the following example: Two signed binary numbers, +70 and +80,
are stored in two eight-bit registers
...
Since the sum of the two numbers is +150,
it exceeds the capacity of an eight-bit register
...
The two
additions in binary are shown next, together with the last two carries:
carries:
+70
+80

0 1
0 1000110
0 1010000

carries:
-70
-80

1 0
1 0111010
1 0110000

+150

1 0010110

-150

0 1101010

Note that the eight-bit result that should have been positive has a negative sign bit (i
...
,
the eighth bit) and the eight-bit result that should have been negative has a positive sign
bit
...
But since the answer cannot be
accommodated within eight bits, we say that an overflow has occurred
...
If these two carries are not equal, an overflow
has occurred
...
If the two carries are applied to an exclusive-OR gate, an overflow is detected
when the output of the gate is equal to 1
...

This takes care of the condition when the maximum negative number is complemented
...
4
...
If the
two binary numbers are considered to be unsigned, then the C bit detects a carry after
addition or a borrow after subtraction
...
If V = 0 after an addition or subtraction, then no overflow
occurred and the n-bit result is correct
...
The 1n + 12 th bit is the actual sign and has been shifted out of
position
...
6

DECIMAL ADDER
Computers or calculators that perform arithmetic operations directly in the decimal
number system represent decimal numbers in binary coded form
...
For binary addition, it is sufficient to consider a
pair of significant bits together with a previous carry
...
There is a wide
variety of possible decimal adder circuits, depending upon the code used to represent the decimal digits
...
(See
Section 1
...
)

BCD Adder
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage
...
Suppose we apply two BCD digits to a four-bit binary adder
...
These binary numbers
are listed in Table 4
...
K is the carry,
and the subscripts under the letter Z represent the weights 8, 4, 2, and 1 that can be
assigned to the four bits in the BCD code
...
The output sum
of two decimal digits must be represented in BCD and should appear in the form
listed in the columns under “BCD Sum
...

In examining the contents of the table, it becomes apparent that when the binary sum
is equal to or less than 1001, the corresponding BCD number is identical, and therefore
no conversion is needed
...
The addition of binary 6 (0110) to the binary sum converts it to
the correct BCD representation and also produces an output carry as required
...
6

Decimal Adder

145

Table 4
...
It is obvious that a correction is needed when the binary sum has
an output carry K = 1
...
To distinguish them from binary 1000 and 1001,
which also have a 1 in position Z8, we specify further that either Z4 or Z2 must have
a 1
...

A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown
in Fig
...
14
...
When the output carry is equal to 0, nothing is added to the binary sum
...
The output carry generated from the bottom

146

Chapter 4

Combinational Logic
Addend

Carry
out

K

Augend

4-bit binary adder
Z8

Z4

Z2

Carry
in

Z1

Output
carry

0

4-bit binary adder

S8

S4

S2

S1

FIGURE 4
...
A decimal parallel adder that adds n decimal digits needs n BCD adder stages
...


4
...
The multiplicand is multiplied by each bit of the multiplier, starting
from the least significant bit
...
Successive partial products are shifted one position to the left
...

To see how a binary multiplier can be implemented with a combinational circuit,
consider the multiplication of two 2-bit numbers as shown in Fig
...
15
...
7
B1

B0

A1

B1

B0

A0B0

A1B1
C3

A0

147

A0

A0B1

Binary Multiplier

A1B0

C2

C1

C0

A1

B1

B0

HA

HA

C3 C2

C1

C0

FIGURE 4
...
The
first partial product is formed by multiplying B1B0 by A0
...
This is identical to an AND operation
...
The second partial product is formed by multiplying B1B0 by A1 and shifting one position to the left
...
Usually, there are more bits in the partial products
and it is necessary to use full adders to produce the sum of the partial products
...

A combinational circuit binary multiplier with more bits can be constructed in a
similar fashion
...
The binary output in each level of AND
gates is added with the partial product of the previous level to form a new partial product
...
For J multiplier bits and K multiplicand bits, we
need 1J * K2 AND gates and 1J - 12 K-bit adders to produce a product of (J + K)
bits
...
Let the multiplicand be
represented by B3B2B1B0 and the multiplier by A2A1A0
...
The logic
diagram of the multiplier is shown in Fig
...
16
...
16
Four-bit by three-bit binary multiplier

4
...
A magnitude comparator is a
combinational circuit that compares two numbers A and B and determines their relative
magnitudes
...

On the one hand, the circuit for comparing two n-bit numbers has 22n entries in the
truth table and becomes too cumbersome, even with n = 3
...
8

Magnitude Comparator

149

may suspect, a comparator circuit possesses a certain amount of regularity
...
We illustrate this method here by deriving an algorithm for
the design of a four-bit magnitude comparator
...
Consider two numbers, A and B, with four digits
each
...
The two numbers are
equal if all pairs of significant digits are equal: A3 = B3, A2 = B2, A1 = B1, and
A0 = B0
...
e
...

The equality of the two numbers A and B is displayed in a combinational circuit by
an output binary variable that we designate by the symbol 1A = B2
...

For equality to exist, all xi variables must be equal to 1, a condition that dictates an AND
operation of all variables:
1A = B2 = x3x2x1x0
The binary variable 1A = B2 is equal to 1 only if all pairs of digits of the two numbers
are equal
...
If the two digits
of a pair are equal, we compare the next lower significant pair of digits
...
If the corresponding digit of A is 1
and that of B is 0, we conclude that A 7 B
...
The sequential comparison can be expressed logically by the
two Boolean functions
1A 7 B2 = A3BЈ + x3 A2BЈ + x3x2A1BЈ + x3x2x1A0BЈ
3
2
1
0
1A 6 B2 = AЈ B3 + x3AЈ B2 + x3x2AЈ BЈ + x3x2x1AЈn0BЈ
3
2
1 1
0
The symbols 1A 7 B2 and 1A 6 B2 are binary output variables that are equal to 1
when A 7 B and A 6 B, respectively
...
The unequal outputs can use
the same gates that are needed to generate the equal output
...
4
...
The four x outputs are generated

150

Chapter 4

Combinational Logic

A3
x3
B3

A2
x2
B2

(A Ͻ B)
A1
x1
B1

A0
x0

(A Ͼ B)

B0

(A ϭ B)

FIGURE 4
...
The other two outputs use the x variables to generate the Boolean
functions listed previously
...

The procedure for obtaining magnitude comparator circuits for binary numbers with
more than four bits is obvious from this example
...
9

DECODERS
Discrete quantities of information are represented in digital systems by binary codes
...
A decoder is a combinational circuit that converts binary information from

Section 4
...
If the n-bit coded information has
unused combinations, the decoder may have fewer than 2n outputs
...
Their
purpose is to generate the 2n (or fewer) minterms of n input variables
...
The name decoder is also used in conjunction with
other code converters, such as a BCD-to-seven-segment decoder
...
4
...
The three
inputs are decoded into eight outputs, each representing one of the minterms of the
three input variables
...
A particular application of
this decoder is binary-to-octal conversion
...

However, a three-to-eight-line decoder can be used for decoding any three-bit code to
provide eight outputs, one for each element of the code
...
18
Three-to-eight-line decoder

152

Chapter 4

Combinational Logic

Table 4
...
6
...
The output whose value is equal to 1 represents the minterm
equivalent of the binary number currently available in the input lines
...
Since a NAND gate produces the
AND operation with an inverted output, it becomes more economical to generate the
decoder minterms in their complemented form
...
A two-to-four-line decoder with an
enable input constructed with NAND gates is shown in Fig
...
19
...
The decoder is enabled
when E is equal to 0 (i
...
, active-low enable)
...
19
Two-to-four-line decoder with enable input

(b) Truth table

Section 4
...
The output
whose value is equal to 0 represents the minterm selected by inputs A and B
...
When
the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are
selected
...
The enable input may be activated with a 0 or with a 1 signal
...

A decoder with enable input can function as a demultiplexer—a circuit that receives
information from a single line and directs it to one of 2n possible output lines
...

The decoder of Fig
...
19 can function as a one-to-four-line demultiplexer when E is
taken as a data input line and A and B are taken as the selection inputs
...
This feature can be verified from the truth table of the circuit
...
Because decoder and demultiplexer
operations are obtained from the same circuit, a decoder with an enable input is
referred to as a decoder–demultiplexer
...
Figure 4
...
When w ϭ 0, the top decoder is enabled and the other is disabled
...
When w ϭ 1, the enable conditions are reversed: The bottom decoder
outputs generate minterms 1000 to 1111, while the outputs of the top decoder are all
0’s
...
20
4 * 16 decoder constructed with two 3 * 8 decoders

D8 to D15

154

Chapter 4

Combinational Logic

combinational logic components
...


Combinational Logic Implementation
A decoder provides the 2n minterms of n input variables
...
Since any Boolean function
can be expressed in sum-of-minterms form, a decoder that generates the minterms of
the function, together with an external OR gate that forms their logical sum, provides
a hardware implementation of the function
...

The procedure for implementing a combinational circuit by means of a decoder and
OR gates requires that the Boolean function for the circuit be expressed as a sum of
minterms
...
The inputs to each OR gate are selected from the decoder outputs according to
the list of minterms of each function
...

From the truth table of the full adder (see Table 4
...
The implementation is shown in Fig
...
21
...
The OR gate for output S forms the logical sum of minterms 1,
2, 4, and 7
...


0
1
x

22

y

21

z

0

2

S

2
3ϫ8
decoder

3
4
5
6
7

FIGURE 4
...
10

Encoders

155

A function with a long list of minterms requires an OR gate with a large number of
inputs
...
If the number of minterms in the function is greater than 2n >2,
then FЈ can be expressed with fewer minterms
...
The output of the NOR gate complements this
sum and generates the normal output F
...
4
...
This is
because a two-level NAND gate circuit implements a sum-of-minterms function and is
equivalent to a two-level AND–OR circuit
...
10

ENCODERS
An encoder is a digital circuit that performs the inverse operation of a decoder
...
The output lines, as an aggregate,
generate the binary code corresponding to the input value
...
7
...
It is assumed that only one input has a value of 1 at any given time
...
Output z is equal to 1 when the input octal digit is 1, 3, 5,
or 7
...
These
conditions can be expressed by the following Boolean output functions:
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
The encoder can be implemented with three OR gates
...
7
Truth Table of an Octal-to-Binary Encoder
Inputs

Outputs

D0

D1

D2

D3

D4

D5

D6

D7

x

y

z

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

156

Chapter 4

Combinational Logic

The encoder defined in Table 4
...
If two inputs are active simultaneously, the output produces an undefined combination
...
The output 111 does not
represent either binary 3 or binary 6
...
If we establish a
higher priority for inputs with higher subscript numbers, and if both D3 and D6 are 1 at
the same time, the output will be 110 because D6 has higher priority than D3
...

The discrepancy can be resolved by providing one more output to indicate whether at
least one input is equal to 1
...
The operation
of the priority encoder is such that if two or more inputs are equal to 1 at the same time,
the input having the highest priority will take precedence
...
8
...
If all inputs are 0, there is no valid input and V is equal to 0
...
Note that whereas X’s in output columns represent don’t-care conditions, the
X’s in the input columns are useful for representing a truth table in condensed form
...
For example, X100 represents the two minterms 0100 and 1100
...
8, the higher the subscript number, the higher the priority of
the input
...
D2 has the next priority
level
...
The output for D1 is generated only if higher priority
inputs are 0, and so on down the priority levels
...
8
Truth Table of a Priority Encoder
Inputs

Outputs

D0

D1

D2

D3

x

y

V

0
1
X
X
X

0
0
1
X
X

0
0
0
1
X

0
0
0
0
1

X
0
0
1
1

X
0
1
0
1

0
1
1
1
1

Section 4
...
22
Maps for a priority encoder

The maps for simplifying outputs x and y are shown in Fig
...
22
...
8
...
For example, the fourth row in the table, with inputs XX10, represents the four
minterms 0010, 0110, 1010, and 1110
...
The condition for output V is an OR function of
all the input variables
...
4
...
23
Four-input priority encoder

V

158

4
...
The selection of a particular input
line is controlled by a set of selection lines
...

A two-to-one-line multiplexer connects one of two 1-bit sources to a common destination, as shown in Fig
...
24
...
When S = 0, the upper AND gate is enabled and I0 has a path to
the output
...

The multiplexer acts like an electronic switch that selects one of two sources
...
4
...
It suggests visually how a selected one of multiple data sources is directed
into a single destination
...

A four-to-one-line multiplexer is shown in Fig
...
25
...
Selection lines S1 and S0 are decoded
to select a particular AND gate
...
The function table lists the input that is
passed to the output for each combination of the binary selection values
...
The AND gate associated
with input I2 has two of its inputs equal to 1 and the third input connected to I2
...
The output of the OR gate is now equal to the value of I2, providing a path
from the selected input to the output
...

The AND gates and inverters in the multiplexer resemble a decoder circuit, and indeed,
they decode the selection input lines
...
The outputs
of the AND gates are applied to a single OR gate
...
24
Two-to-one-line multiplexer

(b) Block diagram

Y

Section 4
...
25
Four-to-one-line multiplexer

the number 2n of its data input lines and the single output line
...
As in decoders, multiplexers may have an enable input to
control the operation of the unit
...

Multiplexer circuits can be combined with common selection inputs to provide
multiple-bit selection logic
...
4
...
The circuit has four multiplexers, each capable of selecting one of two input
lines
...
Similarly,
output Y1 may have the value of A1 or B1, and so on
...
The enable input E must be active (i
...
, asserted)
for normal operation
...
As shown
in the function table, the unit is enabled when E = 0
...
If, by contrast, S = 1, the four B inputs are applied to the
outputs
...


Boolean Function Implementation
In Section 4
...
An examination of the logic diagram of a multiplexer
reveals that it is essentially a decoder that includes the OR gate within the unit
...
26
Quadruple two-to-one-line multiplexer

minterms of a function are generated in a multiplexer by the circuit associated with the
selection inputs
...

We will now show a more efficient method for implementing a Boolean function of
n variables with a multiplexer that has n - 1 selection inputs
...
The remaining
single variable of the function is used for the data inputs
...
11

Multiplexers

161

by z, each data input of the multiplexer will be z, zЈ, 1, or 0
...
4
...
The two variables x and y are applied to the selection lines in that
order; x is connected to the S1 input and y to the S0 input
...
When xy = 00, output F is
equal to z because F = 0 when z = 0 and F = 1 when z = 1
...
The operation of the multiplexer is such that when xy = 00,
data input 0 has a path to the output, and that makes F equal to z
...
This particular example shows all four possibilities that
can be obtained for the data inputs
...
To begin with, Boolean function is listed in a truth table
...
For each combination of the selection variables, we evaluate the output as a function of the last
variable
...
These
values are then applied to the data inputs in the proper order
...
4
...
Note that the first variable A must be connected to selection input S2 so that
A, B, and C correspond to selection inputs S2, S1, and S0, respectively
...
27
Implementing a Boolean function with a multiplexer

F

162

Chapter 4

Combinational Logic

A

B

C

D F

0
0

0
0

0
0

0
1

0
1

FϭD

0
0

0
0

1
1

0
1

0
1

FϭD

0
0

1
1

0
0

0
1

1
0

F ϭ DЈ

0
0

1
1

1
1

0
1

0
0

Fϭ0

1
1

0
0

0
0

0
1

0
0

Fϭ0

1
1

0
0

1
1

0
1

0
1

FϭD

1
1

1
1

0
0

0
1

1
1

Fϭ1

1
1

1
1

1
1

0
1

1
1

Fϭ1

8 ϫ 1 MUX
C

S0

B
A

S1

D

0
1
2

0

S2

F

3
4
5

1

6
7

FIGURE 4
...
The corresponding
data line number is determined from the binary combination of ABC
...
The binary constants 0 and 1 correspond to two fixed signal values
...
g
...


Three-State Gates
A multiplexer can be constructed with three-state gates—digital circuits that exhibit
three states
...
The third state is a high-impedance state in which (1) the logic behaves like
an open circuit, which means that the output appears to be disconnected, (2) the circuit
has no logic significance, and (3) the circuit connected to the output of the three-state
gate is not affected by the inputs to the gate
...
However, the one most commonly used is the
buffer gate
...
4
...
It is distinguished
from a normal buffer by an input control line entering the bottom of the symbol
...
When the control input is equal to 1, the output is enabled and the gate behaves
like a conventional buffer, with the output equal to the normal input
...
11

Multiplexers

163

Output Y ϭ A if C ϭ 1
High-impedance if C ϭ 0

Normal input A
Control input C

FIGURE 4
...
The high-impedance state of a three-state gate provides
a special feature not available in other gates
...

The construction of multiplexers with three-state buffers is demonstrated in Fig
...
30
...
30(a) shows the construction of a two-to-one-line multiplexer with 2 three-state
buffers and an inverter
...
(Note that this type of connection cannot be made with gates that do not have
three-state outputs
...
Output Y is then equal to input A
...

The construction of a four-to-one-line multiplexer is shown in Fig
...
30(b)
...
The
control inputs to the buffers determine which one of the four normal inputs I0 through
I0

Y

I1

I2

A

Y

I3

0
Select

B

Enable

Select

S1
S0
EN

2ϫ4
decoder

1
2
3

(a) 2-to-1-line mux

FIGURE 4
...
No more than one buffer may be in the active
state at any given time
...
One way to ensure that no more than one control input is active at any
given time is to use a decoder, as shown in the diagram
...
When the enable input is active, one of the threestate buffers will be active, depending on the binary value in the select inputs of the
decoder
...


4
...
10
...
Sequential circuits are presented in
Chapter 5
...
The logic of a module can be described in any one (or a
combination) of the following modeling styles:
• Gate-level modeling using instantiations of predefined and user-defined primitive
gates
...

• Behavioral modeling using procedural assignment statements with the keyword
always
...
Dataflow modeling is used mostly for describing the
Boolean equations of combinational logic
...
Combinational logic can be designed with truth tables, Boolean equations, and
schematics; Verilog has a construct corresponding to each of these “classical” approaches
to design: user-defined primitives, continuous assignments, and primitives, as shown in
Fig
...
31
...
It is sometimes
used in the simulation of MOS transistor circuit models, but not in logic synthesis
...


Gate-Level Modeling
Gate-level modeling was introduced in Section 3
...
In this type
of representation, a circuit is specified by its logic gates and their interconnections
...
The Verilog HDL

Section 4
...
31
Relationship of Verilog constructs to truth tables, Boolean equations, and schematics

includes 12 basic gates as predefined primitives
...
The other eight are the same as the ones listed in Section 2
...
They are
all declared with the lowercase keywords and, nand, or, nor, xor, xnor, not, and buf
...
They can have any number of scalar inputs
(e
...
, a three-input and primitive)
...

A single input can drive multiple output lines distinguished by their identifiers
...
The
logic of each gate is based on a four-valued system
...
In addition to
the two logic values of 0 and 1, there are two other values: unknown and high impedance
...
An unknown value is
assigned during simulation when the logic value of a signal is ambiguous—for instance,
if it cannot be determined whether its value is 0 or 1 (e
...
, a flip-flop without a reset
condition)
...
The four-valued logic truth
tables for the and, or, xor, and not primitives are shown in Table 4
...
The truth table for
the other four gates is the same, except that the outputs are complemented
...
Otherwise, if one input is x or z, the output is x
...

When a primitive gate is listed in a module, we say that it is instantiated in the module
...
Thus, a module that uses a gate in its description is said to

166

Chapter 4

Combinational Logic
Table 4
...
Think of instantiation as the HDL counterpart of placing and
connecting parts on a circuit board
...
Both examples use identifiers
having multiple bit widths, called vectors
...
The following Verilog statements
specify two vectors:
output [0: 3] D;
wire

[7: 0] SUM;

The first statement declares an output vector D with four bits, 0 through 3
...
(Note: The first (leftmost) number (array index) listed is always the most significant bit of the vector
...
It is also
possible to address parts (contiguous bits) of vectors
...

HDL Example 4
...

(See  Fig
...
19
...
The
four outputs are specified with the vector D
...
Three not gates produce the complement of the inputs, and four nand gates provide
the outputs for D
...
This example describes the decoder of Fig
...
19 and
follows the procedures established in Section 3
...
Note that the keywords not and nand
are written only once and do not have to be repeated for each gate, but commas must
be inserted at the end of each of the gates in the series, except for the last statement,
which must be terminated with a semicolon
...
12

HDL Models of Combinational Circuits

167

HDL Example 4
...
4
...

module decoder_2x4_gates (D, A, B, enable);
output
[0: 3]
D;
input
A, B;
input
enable;
wire
A_not,B_not, enable_not;
not
G1 (A_not, A),
G2 (B_not, B),
G3 (enable_not, enable);
nand
G4 (D[0], A_not, B_not, enable_not),
G5 (D[1], A_not, B, enable_not),
G6 (D[2], A, B_not, enable_not),
G7 (D[3], A, B, enable_not);
endmodule

Two or more modules can be combined to build a hierarchical description of a design
...
In a
top-down design, the top-level block is defined and then the subblocks necessary to
build the top-level block are identified
...
Take, for example, the
binary adder of Fig
...
9
...
In a top-down
design, the four-bit adder is defined first, and then the two adders are described
...

A bottom-up hierarchical description of a four-bit adder is shown in HDL
Example 4
...
The half adder is defined by instantiating primitive gates
...
The third
module describes the four-bit adder by instantiating and connecting four full adders
...
An alternative name that is meaningful,
but does not require a leading underscore, is adder_4_bit
...
For example, the half adder HA1 inside the full adder module is
instantiated with ports S1, C1, x, and y
...


168

Chapter 4

Combinational Logic

HDL Example 4
...
4
...
4
...
4
...
2 illustrates Verilog 2001, 2005 syntax, which eliminates extra typing
of identifiers declaring the mode (e
...
, output), type (reg), and declaration of a vector range
(e
...
, [3: 0]) of a port
...


Section 4
...
In other words, a module definition cannot be
inserted into the text between the module and endmodule keywords of another module
...
Instantiating modules within other modules creates a hierarchical
decomposition of a design
...
Note also that instance names
must be specified when defined modules are instantiated (such as FA0 for the first full
adder in the third module), but using a name is optional when instantiating primitive
gates
...
The top
level, or parent module, of the design hierarchy is the module ripple_carry_4_bit_adder
...
C0 is an input of the cell forming the
least significant bit of the chain, and C4 is the output of the cell forming the most
significant bit
...
11, a three-state gate has a control input that can place the
gate into a high-impedance state
...

There are four types of three-state gates, as shown in Fig
...
32
...
The output goes to a high-impedance state z when
control = 0
...
The two notif gates operate in a similar manner, except
that the output is the complement of the input when the gate is not in a high-impedance
state
...
32
Three-state gates

out

notif0

170

Chapter 4

Combinational Logic

The gate name can be that of any 1 of the 4 three-state gates
...
Two examples of gate instantiation are
bufif1
notif0

(OUT, A, control);
(Y, B, enable);

In the first example, input A is transferred to OUT when control = 1
...
In the second example, output Y = z when enable = 1 and output
Y = BЈ when enable = 0
...
To identify such a connection, Verilog HDL uses the keyword tri (for tristate) to
indicate that the output has multiple drivers
...
4
...

The HDL description must use a tri data type for the output:
// Mux with three-state output
module mux_tri (m_out, A, B, select);
output m_out;
input A, B, select;
tri
m_out;
bufif1 (m_out, A, select);
bufif0 (m_out, B, select);
endmodule
The 2 three-state buffers have the same output
...

Keywords wire and tri are examples of a set of data types called nets, which represent
connections between hardware elements
...
The word
net is not a keyword, but represents a class of data types, such as wire, wor, wand, tri,
supply1, and supply0
...
In fact, if an identifier
is used, but not declared, the language specifies that it will be interpreted (by default) as
a wire
...
The wand models the wired-AND configuration (open-collector
technology; see Fig
...
26)
...
They are used to hardwire an input of a device to either 1 or 0
...
33
Two-to-one-line multiplexer with three-state buffers

m_out

Section 4
...
Verilog HDL provides about 30 different operators
...
10 lists some of these operators, their symbols, and the operation that they perform
...
1 in Section 8
...
) It is necessary to distinguish between arithmetic and logic
operations, so different symbols are used for each
...
There are special symbols for bitwise logical OR (disjunction), NOT, and
XOR
...
The bitwise operators
operate bit by bit on a pair of vector operands to produce a vector result
...
For example,
two operands with two bits each can be concatenated to form an operand with four bits
...
6
...
g
...
g
...
If the
operands are scalar the results will be identical; if the operands are vectors the result
will not necessarily match
...
A binary
value is considered to be logically true if it is not 0
...

Dataflow modeling uses continuous assignments and the keyword assign
...
The data type family net is
used in Verilog HDL to represent a physical connection between circuit elements
...
10
Some Verilog HDL Operators
Symbol
ϩ
Ϫ
&
Խ
^
∼
ϭϭ
Ͼ
Ͻ
{}
?:

Operation
binary addition
binary subtraction
bitwise AND
bitwise OR
bitwise XOR
bitwise NOT
equality
greater than
less than
concatenation
conditional

Symbol

Operation

&&
||

logical AND
logical OR

!

logical NOT

172

Chapter 4

Combinational Logic

is declared explicitly by a net keyword (e
...
, wire) or by declaring an identifier to be an
input port
...
If the net is connected to an output of a gate, the net is said to be driven by
the gate, and the logic value of the net is determined by the logic values of the inputs to
the gate and the truth table of the gate
...
As an example, assuming that the variables were declared, a two-to-one-line multiplexer with scalar data inputs A and B, select input S, and output Y is described with
the continuous assignment
assign Y ϭ (A && S) || (B && S)
The relationship between Y, A, B, and S is declared by the keyword assign, followed by
the target output Y and an equals sign
...
In hardware terms, this assignment would be equivalent to connecting the output
of the OR gate to wire Y
...
The dataflow description of a two-to-four-line decoder with active-low output
enable and inverted output is shown in HDL Example 4
...
The circuit is defined with
four continuous assignment statements using Boolean expressions, one for each output
...
4
...
The plus symbol (ϩ) specifies the binary addition of the four bits of A with the
four bits of B and the one bit of C_in
...
Concatenation of operands is expressed
within braces and a comma separating the operands
...


HDL Example 4
...
4
...
Note: The figure uses symbol E, but the
// Verilog model uses enable to clearly indicate functionality
...
12

HDL Models of Combinational Circuits

173

HDL Example 4
...
To show how dataflow descriptions facilitate digital design, consider the 4-bit magnitude comparator described in HDL Example 4
...
The module
specifies two 4-bit inputs A and B and three outputs
...
Note that equality (identity) is symbolized
with two equals signs (ϭ ϭ) to distinguish the operation from that of the assignment
operator (ϭ)
...
4
...

HDL Example 4
...
This operator takes three
operands:
condition ? true-expression : false-expression;
The condition is evaluated
...
If the result is

174

Chapter 4

Combinational Logic

logic 0, the false expression is evaluated
...
HDL Example 4
...
The continuous assignment
assign OUT ϭ select ? A : B;
specifies the condition that OUT ϭ A if select ϭ 1, else OUT ϭ B if select ϭ 0
...
6 (Dataflow: Two-to-One Multiplexer)
// Dataflow description of two-to-one-line multiplexer
module mux_2x1_df(m_out, A, B, select);
output
m_out;
input
A, B;
input
select;
assign m_out ϭ (select)? A : B;
endmodule

Behavioral Modeling
Behavioral modeling represents digital circuits at a functional and algorithmic level
...
Here, we give two simple combinational circuit examples to introduce the
subject
...
6, after the study
of sequential circuits
...
The event control expression specifies when the statements will execute
...
Contrary to the wire data type,
whereby the target output of an assignment may be continuously updated, a reg data
type retains its value until a new value is assigned
...
7 shows the behavioral description of a two-to-one-line multiplexer
...
6
...
The procedural assignment statements inside the always block are executed every time there is a change in
any of the variables listed after the @ symbol
...
) In this case, these variables are the input variables A, B,
and select
...
Note that the keyword
or, instead of the bitwise logical OR operator “|” is used between variables
...
The
if statement can be written without the equality symbol:
if (select) OUT ϭ A;
The statement implies that select is checked for logic 1
...
12

HDL Models of Combinational Circuits

175

HDL Example 4
...
8 describes the function of a four-to-one-line multiplexer
...
The always
statement, in this example, has a sequential block enclosed between the keywords case
and endcase
...
The case statement is a multiway conditional branch construct
...
The statement associated with the first case item that
matches the case expression is executed
...
Since select is a two-bit number, it can be equal to 00, 01, 10, or 11
...

The list is called a sensitivity list (Verilog 2001, 2005) and is equivalent to the event
control expression (Verilog 1995) formed by “ORing” the signals
...

HDL Example 4
...
The size of the number is written first and then its value
...
Numbers are stored as a bit pattern in
memory, but they can be referenced in decimal, octal, or hexadecimal formats with the
letters dЈ oЈ and hЈ respectively
...
If the base of the number is not specified,
its interpretation defaults to decimal
...
The integer data type (keyword integer) is stored in a 32-bit representation
...
g
...
It has no other effect
...
The first will treat
as don’t-cares any bits of the case expression or the case item that have logic value x or
z
...

The list of case items need not be complete
...
Unlisted case
items, i
...
, bit patterns that are not explicitly decoded can be treated by using the default
keyword as the last item in the list of case items
...
This feature is useful, for example, when there are more
possible state codes in a sequential machine than are actually used
...

The examples of behavioral descriptions of combinational circuits shown here are
simple ones
...
6
...
Test
benches can be quite complex and lengthy and may take longer to develop than the
design that is tested
...
Care must be taken to write stimuli that will test a circuit thoroughly,
exercising all of the operating features that are specified
...
The examples are presented to demonstrate some basic features of
HDL stimulus modules
...

In addition to employing the always statement, test benches use the initial statement
to provide a stimulus to the circuit being tested
...
Actually, always is a Verilog language construct specifying how the associated
statement is to execute (subject to the event control expression)
...
12

HDL Models of Combinational Circuits

177

executes repeatedly in a loop
...
For example, consider the initial
block
initial
begin
A ϭ 0; B ϭ 0;
#10 A ϭ 1;
#20 A ϭ 0; B ϭ 1;
end

The block is enclosed between the keywords begin and end
...
Ten time units later, A is changed to 1
...
Inputs specified by a three-bit truth table can be generated with
the initial block:
initial
begin
D ϭ 3’b000;
repeat (7)
#10 D ϭ D ϩ 3’b001;
end
When the simulator runs, the three-bit vector D is initialized to 000 at time ϭ 0
...
The result is a sequence of binary numbers from 000 to 111
...

// Instantiate the design module under test
...

// Generate stimulus, using initial and always statements
...

endmodule
A test module is written like any other module, but it typically has no inputs or outputs
...
The outputs of the design module that are
displayed for testing are declared in the stimulus module as local wire data type
...

Figure  4
...
The stimulus module generates inputs for the
design module by declaring local identifiers t_A and t_B as reg type and checks the
output of the design unit with the wire identifier t_C
...
The simulator associates the (actual) local
identifiers within the test bench, t_A, t_B, and t_C, with the formal identifiers of the

178

Chapter 4

Combinational Logic
module t_circuit;
reg t_A, t_B;
wire t_C;
parameter stop_time ϭ 1000 ;

module circuit ( C , A, B )
input
output

circuit M ( t_C, t_A, t_B );
// Stimulus generators for
// t_A and t_B go here
initial # stop_time $finish;
endmodule

A, B;
C;

// Description goes here
endmodule

FIGURE 4
...
The association shown here is based on position in the port list, which
is adequate for the examples that we will consider
...

The response to the stimulus generated by the initial and al ways blocks will
appear in text format as standard output and as waveforms (timing diagrams) in
simulators having graphical output capability
...
These are built-in system functions that are recognized
by keywords that begin with the symbol $
...

The syntax for $display, $write, and $monitor is of the form
Task-name ( format specification, argumentlist);
The format specification uses the symbol % to specify the radix of the numbers that are
displayed and may have a string enclosed in quotes (Љ)
...
For example, the statement
$display ("%d %b %b", C, A, B);
specifies the display of C in decimal and of A and B in binary
...
12

HDL Models of Combinational Circuits

179

are separated by a comma, and that the argument list has commas between the
variables
...
The format
specifiers %0d, %b, and %b specify the base for $time, A, and B, respectively
...
This provides a display
of the significant digits without the leading spaces that %d will include
...
)
An example of a stimulus module is shown in HDL Example 4
...
The circuit to be
tested is the two-to-one-line multiplexer described in Example 4
...
The module
t_mux_2x1_df has no ports
...
The mux is instantiated with the local variables
...

The output response is checked with the $monitor system task
...
The result
of the simulation is listed under the simulation log in the example
...

HDL Example 4
...
6
module mux_2x1_df (m_out, A, B, select);
output
m_out;
input
A, B;
input
select;
assign m_out ϭ (select)? A : B;
endmodule
Simulation log:
select ϭ 1 A ϭ 0 B ϭ 1 OUT ϭ 0 time ϭ 0
select ϭ 1 A ϭ 1 B ϭ 0 OUT ϭ 1 time ϭ 10
select ϭ 0 A ϭ 1 B ϭ 0 OUT ϭ 0 time ϭ 20
select ϭ 0 A ϭ 0 B ϭ 1 OUT ϭ 1 time ϭ 30

Logic simulation is a fast and accurate method of verifying that a model of a
combinational circuit is correct
...
In functional verification, we study the circuit logical operation independently of timing considerations
...
In timing verification, we study the circuit’s operation by
including the effect of delays through the gates
...
An example of a circuit with gate delays was presented in Section 3
...
3
...
A  $monitor system task displays the output caused by the given stimulus
...

The analysis of combinational circuits was covered in Section 4
...
A multilevel
circuit of a full adder was analyzed, and its truth table was derived by inspection
...
10
...
The description of the circuit follows the
interconnections between the gates according to the schematic diagram of Fig
...
2
...
The inputs for simulating
the circuit are specified with a three-bit reg vector D
...
The outputs of the circuit F1 and F2 are declared
as wire
...
This procedure

Section 4
...
4
...
The repeat loop provides the seven binary numbers after 000 for the truth table
...
The truth table listed shows that the circuit is
a full adder
...
10 (Gate-Level Circuit)
// Gate-level description of circuit of Fig
...
2
module Circuit_of_Fig_4_2 (A, B, C, F1, F2);
input A, B, C;
output F1, F2;
wire T1, T2, T3, F2_b, E1, E2, E3;
or g1 (T1, A, B, C);
and g2 (T2, A, B, C);
and g3 (E1, A, B);
and g4 (E2, A, C);
and g5 (E3, B, C);
or g6 (F2, E1, E2, E3);
not g7 (F2_b, F2);
and g8 (T3, T1, F2_b);
or g9 (F1, T2, T3);
endmodule
// Stimulus to analyze the circuit
module test_circuit;
reg [2: 0] D;
wire F1, F2;
Circuit_of_Fig_4_2 (D[2], D[1], D[0], F1, F2);
initial
begin
D ϭ 3’b000;
repeat (7) #10 D ϭ D 1 1’b1;
end
initial
$monitor (Љ ABC ϭ %b F1 ϭ %b F2 ϭ%b Љ, D, F1, F2);
endmodule
Simulation log: ABC ϭ 000 F1 ϭ 0 F2 ϭ0
ABC ϭ 001 F1 ϭ 1 F2 ϭ0 ABC ϭ 010 F1 ϭ 1 F2 ϭ0
ABC ϭ 011 F1 ϭ 0 F2 ϭ1 ABC ϭ 100 F1 ϭ 1 F2 ϭ0
ABC ϭ 101 F1 ϭ 0 F2 ϭ1 ABC ϭ 110 F1 ϭ 0 F2 ϭ1
ABC ϭ 111 F1 ϭ 1 F2 ϭ1

182

Chapter 4

Combinational Logic

PROBLEMS
(Answers to problems marked with * appear at the end of the text
...
)
4
...
P4
...
(HDL—see Problem 4
...
)
A
B
C

T3
T1
F1
T2

D

T4

F2

FIGURE P4
...
Evaluate the outputs F1 and F2
as a function of the four inputs
...
Then list
the binary values for T1 through T4 and outputs F1 and F2 in the table
...

4
...
P4
...

A
F

B
C
G
D

FIGURE P4
...
3

4
...
4
...
11),
(a) Write the Boolean functions for the four outputs in terms of the input variables
...

(a)* The output is 1 when the binary value of the inputs is less than 3
...

(b) The output is 1 when the binary value of the inputs is an even number
...
5

Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C
...
When
the binary input is 4, 5, 6, or 7 the binary output is two less than the input
...
6

A majority circuit is a combinational circuit whose output is equal to 1 if the input variables
have more 1’s than 0’s
...

(a)* Design a 3-input majority circuit by finding the circuit’s truth table, Boolean equation,
and a logic diagram
...


4
...
6) to a bit fourbinary number
...

(b) Using a case statement, write and verify a Verilog model of the circuit
...
8

Design a code converter that converts a decimal digit from
(a)* The 8, 4, –2, –1 code to BCD (see Table 1
...
(HDL—see Problem 4
...
)
(b) The 8, 4, –2, –1 code to Gray code
...
9

An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit
in BCD to an appropriate code for the selection of segments in an indicator used to display
the decimal digit in a familiar form
...
P4
...
The numeric display
chosen to represent the decimal digit is shown in Fig
...
9(b)
...
The six invalid combinations should result in a blank display
...
51
...
9
4
...
(The output generates the 2’s
complement of the input binary number
...
Can you predict what the output functions are for a five-bit 2’s complementer?
4
...
52),
(a) Design a full-subtractor circuit incrementer
...
)
(b)* Design a four-bit combinational decrementer (a circuit that subtracts 1 from a fourbit binary number)
...
12 Design a half-subtractor circuit with inputs x and y and outputs Diff and Bout
...

(a) Design a full-subtractor circuit with three inputs x, y, Bin and two outputs Diff and
Bout
...


184

Chapter 4

Combinational Logic

4
...
4
...

M

A

B

(a)

0

0111

0110

(b)

0

1000

1001

(c)

1

1100

1000

(d)

1

0101

1010

(e)

1

0000

0001

In each case, determine the values of the four SUM outputs, the carry C, and overflow V
...
37 and 4
...
)
4
...
What is the total propagation delay time in the
four-bit adder of Fig
...
12?
4
...
4
...

4
...
Show that the output carry and output sum of a full adder becomes
Ci + 1 = (CЈ GЈ + PЈ)Ј
i
i
i
Si = (PiGЈ) { Ci
i
The logic diagram of the first stage of a four-bit parallel adder as implemented in IC type
74283 is shown in Fig
...
16
...

C1

B0
S0
A0
C0

FIGURE P4
...
17 Show that the output carry in a full adder circuit can be expressed in the AND-ORINVERT form
Ci + 1 = Gi + PiCi = (GiЈPiЈ + GiЈCiЈ)Ј
IC type 74182 is a lookahead carry generator circuit that generates the carries with ANDOR-INVERT gates (see Section 3
...
The circuit assumes that the input terminals have
the complements of the G’s, the P’s, and of C1
...
(Hint: Use the equation-substitution method
to derive the carries in terms of CiЈ)
4
...
(HDL—see Problem 4
...
)
(b) Gray-code digit
...
54(b)
...
19 Construct a BCD adder–subtractor circuit
...
4
...
18
...
(HDL—see Problem 4
...
)
4
...
4
...

(b) Write and verify a Verilog dataflow model of the circuit
...
21 Design a combinational circuit that compares two 4-bit numbers to check if they are equal
...

4
...
(HDL—see Problem 4
...
)
4
...
Include an enable input
...
36, 4
...
)
4
...

4
...
Use block diagrams for the components
...
63
...
26 Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable
...
64
...
27 A combinational circuit is specified by the following three Boolean functions:
F1 1A, B, C2 = ⌺11, 4, 62
F2 1A, B, C2 = ⌺13, 52
F3 1A, B, C2 = ⌺12, 4, 6, 72
Implement the circuit with a decoder constructed with NAND gates (similar to Fig
...
19)
and NAND or AND gates connected to the decoder outputs
...
Minimize the number of inputs in the external gates
...
28 Using a decoder and external gates, design the combinational circui defined by the
following three Boolean functions:
(a) F1 = xЈyzЈ + xz

(b) F1 = 1yЈ + x2z

F2 = xyЈzЈ + xЈy

F2 = yЈzЈ + xЈy + yzЈ

F3 = xЈyЈzЈ + xy

F3 = 1x + y2z

186

Chapter 4

Combinational Logic

4
...
8, but with input D0 having
the highest priority and input D3 the lowest priority
...
30 Specify the truth table of an octal-to-binary priority encoder
...
The input with the highest subscript number has the highest priority
...
65
...
31 Construct a 16 ϫ 1 multiplexer with two 8 ϫ 1 and one 2 ϫ 1 multiplexers
...
(HDL—see Problem 4
...
)
4
...
46):
(a)

F 1A, B, C, D2 = ⌺ 10, 2, 5, 8, 10, 142

(b) F 1A, B, C, D2 = ⌸ 12, 6, 112
4
...

4
...
The data inputs I0 through I7 are as follows:
(a)* I1ϭ I2ϭ I7ϭ 0; I3ϭ I5ϭ 1; I0ϭ I4ϭ D; and I6ϭ D’
...

Determine the Boolean function that the multiplexer implements
...
35 Implement the following Boolean function with a 4 ϫ 1 multiplexer and external gates
...
The input requirements for the four data
lines will be a function of variables C and D
...
These functions may have to be implemented with external gates
...
47

...
36 Write the HDL gate-level description of the priority encoder circuit shown in Fig
...
23
...
45
...
37 Write the HDL gate-level hierarchical description of a four-bit adder–subtractor for unsigned binary numbers
...
4
...
You can
instantiate the four-bit full adder described in HDL Example 4
...
(HDL—see Problems
4
...
40
...
38 Write the HDL dataflow description of a quadruple 2-to-1-line multiplexer with enable
(see Fig
...
26)
...
39* Write an HDL behavioral description of a four-bit comparator with a six-bit output Y 3 5:0 4
...
”
4
...
(See Problems 4
...
37

...
41 Repeat problem 4
...


Problems

187

4
...
4
...
22)
...
4
...

(c)* Write an HDL behavioral description of a BCD-to-excess-3 converter
...
Check all three circuits
...
43 Explain the function of the circuit specified by the following HDL description:
module Prob4_43 (A, B, S, E, Q);
input [1:0] A, B;
input
S, E;
output [1:0] Q;
assign Q ϭ E ? (S ? A : B) : 'bz;
endmodule
4
...
The circuit has a three-bit select bus (Sel), sixteen-bit input datapaths
(A[15:0] and B[15:0]), an eight-bit output datapath (y[15:0]), and performs the arithmetic
and logic operations listed below
...
45 Write an HDL behavioral description of a four-input priority encoder
...
Assume that input D[3] has
the highest priority (see Problem 4
...

4
...
32
...
47 Write a Verilog dataflow description of the logic circuit described by the Boolean function
in Problem 4
...

4
...
44 so that it has three-state
output controlled by an enable input, En
...

4
...
P4
...

(b) Compare your results with those obtained for Problem 4
...

4
...
8(a)
...
8(b)
...
51 Develop and simulate a behavioral model of the ABCD-to-seven-segment decoder
described in Problem 4
...

4
...
11(a)
...
11(b)
...
53 Develop and simulate a structural model of the decimal adder shown in Fig
...
14
...
54 Develop and simulate a behavioral model of a circuit that generates the 9’s complement of
(a) a BCD digit (see Problem 4
...

(b) a Gray-code digit (see Problem 4
...
)
4
...
19
...

4
...
The variable to which the assignment is made is to equal 1 if the
numbers match and 0 otherwise
...
57* Develop and verify a behavioral model of the four-bit priority encoder described in
Problem 4
...

4
...
Write a Verilog model of a circuit whose
32-bit output is formed by shifting its 32-bit input three positions to the left and filling the
vacant positions with 0 (shift logical left)
...
59 Write a Verilog model of a BCD-to-decimal decoder using the unused combinations of
the BCD code as don’t-care conditions (see Problem 4
...

4
...
3
...

4
...
3
...

4
...
25
...
63 Write and verify a gate-level hierarchical model of the circuit described in Problem 4
...

4
...
30
...
65 Write a hierarchical gate-level model of the multiplexer described in Problem 4
...


REFERENCES
1
...

3
...


Bhasker, J
...
Allentown, PA: Star Galaxy Press
...

Bhasker, J
...
Verilog HDL Synthesis
...

Ciletti, M
...
1999
...
Upper
Saddle River, NJ: Prentice Hall
...
L
...
Logic Design of Digital Systems, 3rd ed
...


Web Search Topics
5
...

7
...

9
...

11
...

13
...
D
...
Upper Saddle River, NJ: Prentice Hall
...

Hayes, J
...
1993
...
Reading, MA: Addison-Wesley
...
H
...
Contemporary Logic Design
...

Mano, M
...
and C
...
Kime
...
Logic and Computer Design Fundamentals, 4th ed
...

Nelson, V
...
, H
...
Nagle, J
...
Irwin, and B
...
Carroll
...
Digital Logic Circuit
Analysis and Design
...

Palnitkar, S
...
Verilog HDL: A Guide to Digital Design and Synthesis
...

Roth, C
...
2009
...
St
...

Thomas, D
...
and P
...
Moorby
...
The Verilog Hardware Description Language,
5th ed
...

Wakerly, J
...
2005
...
Upper Saddle River,
NJ: Prentice Hall
...
1

INTRODUCTION
Hand-held devices, cell phones, navigation receivers, personal computers, digital cameras,
personal media players, and virtually all electronic consumer products have the ability to
send, receive, store, retrieve, and process information represented in a binary format
...
e
...
This chapter examines the
operation and control of these devices and their use in circuits and enables you to better
understand what is happening in these devices when you interact with them
...
e
...
Sequential circuits, however, act as storage elements and have memory
...
Our treatment
will distinguish sequential logic from combinational logic
...
2

SEQUENTIAL CIRCUITS
A block diagram of a sequential circuit is shown in Fig
...
1
...
The storage
elements are devices capable of storing binary information
...
The sequential circuit receives binary information from external inputs that,
together with the present state of the storage elements, determine the binary value of
the outputs
...
2

Sequential Circuits

Inputs
Combinational
circuit

191

Outputs
Memory
elements

FIGURE 5
...
The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements
...
Thus, a sequential circuit is specified by a time sequence of inputs,
outputs, and internal states
...

There are two main types of sequential circuits, and their classification is a function of
the timing of their signals
...
The behavior
of an asynchronous sequential circuit depends upon the input signals at any instant of time
and the order in which the inputs change
...
The storage capability of a time-delay
device varies with the time it takes for the signal to propagate through the device
...
In gate-type asynchronous
systems, the storage elements consist of logic gates whose propagation delay provides the
required storage
...
Because of the feedback among logic gates, an asynchronous
sequential circuit may become unstable at times
...
These circuits will not be covered in this text
...
Synchronization is achieved by a timing device called a
clock generator, which provides a clock signal having the form of a periodic train of clock
pulses
...
The clock
pulses are distributed throughout the system in such a way that storage elements are
affected only with the arrival of each pulse
...
For example, a circuit that is to add and store two binary numbers would
compute their sum from the values of the numbers and store the sum at the occurrence
of a clock pulse
...
They are called synchronous circuits because the activity within the
circuit and the resulting updating of stored values is synchronized to the occurrence of

192

Chapter 5

Synchronous Sequential Logic
Inputs

Outputs
Combinational
circuit
Flip-flops
Clock pulses

(a) Block diagram

(b) Timing diagram of clock pulses

FIGURE 5
...
The design of synchronous circuits is feasible because they seldom manifest
instability problems and their timing is easily broken down into independent discrete
steps, each of which can be considered separately
...
A flip-flop is a binary storage device capable of storing one bit of information
...
A sequential circuit may use many
flip-flops to store as many bits as necessary
...
5
...
The outputs are formed by a combinational logic
function of the inputs to the circuit or the values stored in the flip-flops (or both)
...
The new
value is stored (i
...
, the flip-flop is updated) when a pulse of the clock signal occurs
...
Consequently, the speed at
which the combinational logic circuits operate is critical
...
5
...
Propagation delays play an important role in
determining the minimum interval between clock pulses that will allow the circuit to
operate correctly
...
When
a clock pulse is not active, the feedback loop between the value stored in the flip-flop
and the value formed at the input to the flip-flop is effectively broken because the flipflop outputs cannot change even if the outputs of the combinational circuit driving their
inputs change in value
...


Section 5
...
3

Storage Elements: Latches

193

S T O R A G E E L E M E N T S : L AT C H E S
A storage element in a digital circuit can maintain a binary state indefinitely (as long
as power is delivered to the circuit), until directed by an input signal to switch states
...
Storage
elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops
...
The two types of storage elements
are related because latches are the basic circuits from which all flip-flops are constructed
...
Because they are the building blocks of flip-flops,
however, we will consider the fundamental storage mechanism used in latches before
considering flip-flops in the next section
...
The SR latch constructed with two
cross-coupled NOR gates is shown in Fig
...
3
...
When output
Q = 1 and QЈ = 0, the latch is said to be in the set state
...
Outputs Q and QЈ are normally the complement of each other
...
If both inputs are then switched
to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state
...

Under normal conditions, both inputs of the latch remain at 0 unless the state has to be
changed
...
The S input must go back to 0 before any other changes take place, in order to avoid
the occurrence of an undefined next state that results from the forbidden input condition
...
5
...
3
SR latch with NOR gates

QЈ

Q QЈ

1
0
0
0
1

1
1
0
0
0

0
0
1
0
1

0
0 (after S ϭ 1, R ϭ 0)
1
1 (after S ϭ 0, R ϭ 1)
0 (forbidden)

(b) Function table

194

Chapter 5

Synchronous Sequential Logic

1
0

S (set)

S R
Q

1
0

R (reset)
(a) Logic diagram

QЈ

1
1
0
1
0

0
1
1
1
0

Q QЈ
0
0
1
1
1

1
1 (after S ϭ 1, R ϭ 0)
0
0 (after S ϭ 0, R ϭ 1)
1 (forbidden)

(b) Function table

FIGURE 5
...
The first condition (S = 1, R = 0) is the action that must be taken by input
S to bring the circuit to the set state
...
After both inputs return to 0, it is then possible to shift to the reset state by
momentary applying a 1 to the R input
...
Thus, when both inputs S and R are equal to 0, the latch
can be in either the set or the reset state, depending on which input was most recently a 1
...
This
action produces an undefined next state, because the state that results from the input
transitions depends on the order in which they return to 0
...
In normal operation, this condition
is avoided by making sure that 1’s are not applied to both inputs simultaneously
...
5
...
It operates with
both inputs normally at 1, unless the state of the latch has to be changed
...
When the S
input goes back to 1, the circuit remains in the set state
...
This action causes
the circuit to go to the reset state and stay there even after both inputs return to 1
...

In comparing the NAND with the NOR latch, note that the input signals for the
NAND require the complement of those values used for the NOR latch
...
The primes (or, sometimes, bars over the letters) designate the fact that the inputs
must be in their complement form to activate the circuit
...
An SR latch with a control input is
shown in Fig
...
5
...
The
control input En acts as an enable signal for the other two inputs
...
This is the quiescent
condition for the SR latch
...
The set state is reached with S = 1, R = 0, and En = 1

Section 5
...
5
SR latch with control input

(active-high enabled)
...
In either case, when En returns to 0, the circuit remains in its current state
...
Moreover, when En = 1 and both the S
and R inputs are equal to 0, the state of the circuit does not change
...

An indeterminate condition occurs when all three inputs are equal to 1
...
When
the enable input goes back to 0, one cannot conclusively determine the next state, because
it depends on whether the S or R input goes to 0 first
...
Nevertheless, the SR latch
is an important circuit because other useful latches and flip-flops are constructed from it
...
This is
done in the D latch, shown in Fig
...
6
...
6
D latch

0 X
1 0
1 1

Next state of Q
No change
Q ϭ 0; reset state
Q ϭ 1; set state

(b) Function table

196

Chapter 5

Synchronous Sequential Logic

S

S

D

R

R

En

SR

SR

D

FIGURE 5
...
The D input goes directly to the S input, and its complement is applied
to the R input
...

The D input is sampled when En = 1
...
If D = 0, output Q goes to 0, placing the circuit in the reset
state
...
It is suited for use as a temporary storage for binary information between a unit
and its environment
...
The output follows
changes in the data input as long as the enable input is asserted
...
When the enable input signal is de-asserted, the binary information that
was present at the data input at the time the transition occurred is retained (i
...
, stored)
at the Q output until the enable input is asserted again
...
Then, depending on the physical circuit, the external enabling
signal will be a value of 0 (active low) or 1 (active high)
...
5
...

by a rectangular block with inputs on the left and outputs on the right
...
The graphic symbol for the SR latch has inputs S and R indicated inside the block
...
The graphic symbol for
the D latch has inputs D and En indicated inside the block
...
4

STORAGE ELEMENTS: FLIP-FLOPS
The state of a latch or flip-flop is switched by a change in the control input
...
The D
latch with pulses in its control input is essentially a flip-flop that is triggered every time the
pulse goes to the logic-1 level
...


Section 5
...
5
...
Consequently, the inputs of the flip-flops are derived in part from the outputs of the same and
other flip-flops
...
The state transitions of the latches start as soon as the clock pulse changes to the
logic-1 level
...

This output is connected to the inputs of the latches through the combinational circuit
...
The
result is an unpredictable situation, since the state of the latches may keep changing for
as long as the clock pulse stays at the active level
...

Flip-flop circuits are constructed in such a way as to make them operate properly
when they are part of a sequential circuit that employs a common clock
...
As shown in
Fig
...
8(a), a positive level response in the enable input allows changes in the output
when the D input changes while the clock pulse stays at logic 1
...
This can be accomplished by eliminating the feedback path that is inherent in the operation of the sequential circuit using latches
...
As shown in Fig
...
8, the positive transition is defined as the positive
edge and the negative transition as the negative edge
...
One way is to employ two latches in a special configuration that isolates the output of the flip-flop and prevents it from being affected
while the input to the flip-flop is changing
...
8
Clock response in latch and flip-flop

198

Chapter 5

Synchronous Sequential Logic

triggers only during a signal transition (from 0 to 1 or from 1 to 0) of the synchronizing
signal (clock) and is disabled during the rest of the clock pulse
...


Edge-Triggered D Flip-Flop
The construction of a D flip-flop with two D latches and an inverter is shown in Fig
...
9
...
The circuit samples the D
input and changes its output Q only at the negative edge of the synchronizing or controlling clock (designated as Clk)
...
The
slave latch is enabled, and its output Q is equal to the master output Y
...
When the input pulse changes to the logic-1 level, the data
from the external D input are transferred to the master
...
Any
change in the input changes the master output at Y, but cannot affect the slave output
...
At the same time, the slave is enabled and the value of Y is transferred to the
output of the flip-flop at Q
...

The behavior of the master–slave flip-flop just described dictates that (1) the output
may change only once, (2) a change in the output is triggered by the negative edge of
the clock, and (3) the change may occur only during the clock’s negative level
...
It is also possible to design the
circuit so that the flip-flop output changes on the positive edge of the clock
...
Such a flip-flop is
triggered with a negative pulse, so that the negative edge of the clock affects the master
and the positive edge affects the slave and the output terminal
...
5
...
Two latches respond to the external D (data) and Clk (clock) inputs
...
The S and R inputs of the output latch

D

D
En

Clk

FIGURE 5
...
4

Storage Elements: Flip-Flops

199

S
Q
Clk
R

QЈ

D

FIGURE 5
...
This causes the output to remain in
its present state
...
If D = 0 when Clk becomes 1, R
changes to 0
...
If there is
a change in the D input while Clk = 1, terminal R remains at 0 because Q is 0
...
When the
clock returns to 0, R goes to 1, placing the output latch in the quiescent condition without changing the output
...

This causes the circuit to go to the set state, making Q = 1
...

In sum, when the input clock in the positive-edge-triggered flip-flop makes a positive
transition, the value of D is transferred to Q
...
e
...
Hence, this type of flip-flop responds to
the transition from 0 to 1 and nothing else
...
There is a minimum time
called the setup time during which the D input must be maintained at a constant value prior
to the occurrence of the clock transition
...
The propagation delay time of the flip-flop is defined as the interval
between the trigger edge and the stabilization of the output to a new state
...


200

Chapter 5

Synchronous Sequential Logic
D

D

Clk

Clk

(a) Positive-edge

(a) Negative-edge

FIGURE 5
...
5
...
It is similar to the symbol used for the D latch, except for the arrowhead-like symbol in front of
the letter Clk, designating a dynamic input
...
A bubble outside the block
adjacent to the dynamic indicator designates a negative edge for triggering the circuit
...


Other Flip-Flops
Very large-scale integration circuits contain several thousands of gates within one package
...
Each flip-flop is constructed from an interconnection of gates
...
Other types of flip-flops can be
constructed by using the D flip-flop and external logic
...

There are three operations that can be performed with a flip-flop: Set it to 1, reset it
to 0, or complement its output
...
Synchronized by a clock signal, the JK flip-flop has two inputs and performs all
three operations
...
5
...
The J input sets the flip-flop to 1, the K input resets it to
0, and when both inputs are enabled, the output is complemented
...

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0
...
When both
J = K = 0 and D = Q, the clock edge leaves the output unchanged
...
5
...
It is similar to the graphic symbol of the
D flip-flop, except that now the inputs are marked J and K
...
This is shown in Fig
...
13(a)
...
4

Storage Elements: Flip-Flops

201

J
D

Q

J
Clk

K
Clk

Clk

QЈ

K

(b) Graphic symbol

(a) Circuit diagram

FIGURE 5
...
13
T flip-flop

T = 0 (J = K = 0), a clock edge does not change the output
...
The complementing flip-flop is useful for designing binary counters
...
5
...
The expression for the D input is
D = T { Q = TQЈ + TЈQ
When T = 0, D = Q and there is no change in the output
...
The graphic symbol for this flip-flop has a T symbol in the input
...
The characteristic tables of three types of flip-flops are presented
in Table 5
...
They define the next state (i
...
, the state that results from a clock transition)

202

Chapter 5

Synchronous Sequential Logic
Table 5
...
Q(t) refers to the present state (i
...
, the
state present prior to the application of a clock edge)
...
Note that the clock edge input is not included in the characteristic
table, but is implied to occur between times t and t + 1
...

The characteristic table for the JK flip-flop shows that the next state is equal to the
present state when inputs J and K are both equal to 0
...
When K = 1
and J = 0, the clock resets the flip-flop and Q(t + 1) = 0
...
When both J and K are equal to 1, the next state changes
to the complement of the present state, a transition that can be expressed as
Q(t + 1) = QЈ(t)
...
This can be expressed as Q(t + 1) = D
...
Note that the D flip-flop does not have a “no-change”
condition
...

Either method effectively circulates the output of the flip-flop when the state of the
flip-flop must remain unchanged
...


Section 5
...
For the D flip-flop, we have the
characteristic equation
Q(t + 1) = D
which states that the next state of the output will be equal to the value of input D in the
present state
...
5
...
We obtain
Q(t + 1) = JQЈ + KЈQ
where Q is the value of the flip-flop output prior to the application of a clock edge
...
5
...
The input that sets the flip-flop to 1 is called
preset or direct set
...

When power is turned on in a digital system, the state of the flip-flops is unknown
...

A positive-edge-triggered D flip-flop with active-low asynchronous reset is shown
in Fig
...
14
...
5
...
When the reset input is 0,
it forces output QЈ to stay at 1, which, in turn, clears output Q to 0, thus resetting the
flip-flop
...

The graphic symbol for the D flip-flop with a direct reset has an additional input
marked with R
...
Flip-flops with a direct set use the symbol S for the asynchronous set input
...
When R = 0, the output
is reset to 0
...
Normal clock operation can proceed only after the reset input goes to logic 1
...
The value in D is transferred to Q with every positive-edge clock signal,
provided that R = 1
...
14
D flip-flop with asynchronous reset

5
...
The
behavior of a clocked sequential circuit is determined from the inputs, the outputs, and
the state of its flip-flops
...
The analysis of a sequential circuit consists of obtaining a table or
a diagram for the time sequence of inputs, outputs, and internal states
...
5

Analysis of Clocked Sequential Circuits

205

to write Boolean expressions that describe the behavior of the sequential circuit
...

A logic diagram is recognized as a clocked sequential circuit if it includes flip-flops
with clock inputs
...
In this section, we introduce an algebraic representation for specifying the next-state condition in terms of the present state and inputs
...
Another algebraic representation is introduced for specifying the logic
diagram of sequential circuits
...


State Equations
The behavior of a clocked sequential circuit can be described algebraically by means of
state equations
...
Consider the sequential circuit shown
in Fig
...
15
...
15
Example of sequential circuit

206

Chapter 5

Synchronous Sequential Logic

0 is detected in a stream of 1s
...
Since the D input of a flip-flop determines the value of the next state (i
...
, the
state reached after the clock transition), it is possible to write a set of state equations
for the circuit:
A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = AЈ(t)x(t)
A state equation is an algebraic expression that specifies the condition for a flip-flop
state transition
...
The right side of the equation is a Boolean expression that
specifies the present state and input conditions that make the next state equal to 1
...
Similarly, the present-state value of
the output can be expressed algebraically as
y(t) = [A(t) + B(t)]xЈ(t)
By removing the symbol (t) for the present state, we obtain the output Boolean equation:
y = (A + B)xЈ

State Table
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table (sometimes called a transition table)
...
5
...
2
...
The present-state section shows the states of flip-flops A and B at
any given time t
...

The next-state section shows the states of the flip-flops one clock cycle later, at time
t + 1
...

The derivation of a state table requires listing all possible binary combinations of
present states and inputs
...
The next-state values are then determined from the logic diagram or from the state
equations
...
5

Analysis of Clocked Sequential Circuits

207

Table 5
...
5
...
Similarly, the next state of flip-flop B is derived from the state equation
B(t + 1) = AЈx
and is equal to 1 when the present state of A is 0 and input x is equal to 1
...
In general, a sequential circuit with m flipflops and n inputs needs 2m + n rows in the state table
...
The next-state section
has m columns, one for each flip-flop
...
The output section has as many columns as there are
output variables
...

It is sometimes convenient to express the state table in a slightly different form having only three sections: present state, next state, and output
...
The state table of Table 5
...
3 in this second form
...
One form may be preferable to the other, depending on the application
...
In this type of diagram, a state is represented by a circle, and the
(clock-triggered) transitions between states are indicated by directed lines connecting

208

Chapter 5

Synchronous Sequential Logic
Table 5
...
16
State diagram of the circuit of Fig
...
15

the circles
...
5
...
5
...

The state diagram provides the same information as the state table and is obtained
directly from Table 5
...
3
...
The directed lines are labeled with two binary numbers separated
by a slash
...
(It is important
to remember that the bit value listed for the output along the directed line occurs during the present state and with the indicated input, and has nothing to do with the
transition to the next state
...
After the next clock cycle, the circuit goes to the next state, 01
...
This information is obtained from the state diagram along the two directed
lines emanating from the circle with state 01
...

The steps presented in this example are summarized below:
Circuit diagram S Equations – State table S State diagram

Section 5
...
An HDL model can be in the form of a
gate-level description or in the form of a behavioral description
...
That understanding comes with experience
...
Therefore, one does not have
to accumulate years of experience in order to become a productive designer of digital
circuits; nor does one have to acquire an extensive background in electrical engineering
...
The state table is easier to derive from a given logic diagram and the
state equation
...
The state diagram
gives a pictorial view of state transitions and is the form more suitable for human interpretation of the circuit’s operation
...
5
...
The first 0 input
after a string of 1’s gives an output of 1 and transfers the circuit back to the initial state,
00
...
It corresponds to the behavior of the circuit in Fig
...
15
...


Flip-Flop Input Equations
The logic diagram of a sequential circuit consists of flip-flops and gates
...
The knowledge of the type of flip-flops and a list of the Boolean expressions of the combinational circuit provide the information needed to draw the
logic diagram of the sequential circuit
...
The part of the circuit that generates the inputs to flip-flops is described
algebraically by a set of Boolean functions called flip-flop input equations (or, sometimes,
excitation equations)
...
For example, the following input equation specifies an OR gate with inputs x and
y connected to the D input of a flip-flop whose output is labeled with the symbol Q:
DQ = x + y
The sequential circuit of Fig
...
15 consists of two D flip-flops A and B, an input x, and
an output y
...
The symbol DA specifies a D flip-flop labeled A
...
The Boolean expressions associated with these two variables and the expression for output y specify the combinational circuit part of the
sequential circuit
...
They imply the type of flip-flop from the letter
symbol, and they fully specify the combinational circuit that drives the flip-flops
...
This is because of the characteristic equation that
equates the next state to the value of the D input: Q(t + 1) = DQ
...
The circuit we want to analyze is described by the
input equation
DA = A { x { y
The DA symbol implies a D flip-flop with output A
...
No output equations are given, which implies that the output comes from
the output of the flip-flop
...
5
...

The state table has one column for the present state of flip-flop A, two columns for
the two inputs, and one column for the next state of A
...
5
...
The next-state values are
obtained from the state equation
A(t + 1) = A { x { y
The expression specifies an odd function and is equal to 1 when only one variable is 1
or when all three variables are 1
...

The circuit has one flip-flop and two states
...
5
...
The present state and the output can be either
0 or 1, as indicated by the number inside the circles
...
The two inputs can
have four possible combinations for each state
...


Analysis with JK Flip-Flops
A state table consists of four sections: present state, inputs, next state, and outputs
...
The output section is determined from the output equations
...
For a D-type flip-flop, the state equation is the same as the input equation
...
5

Analysis of Clocked Sequential Circuits

211

Present
Next
state Inputs state
A

x
y

Clk

Clock
(a) Circuit diagram

A

0
0
0
0
1
1
1
1

A

D

x y
0
0
1
1
0
0
1
1

0
1
1
0
1
0
0
1

0
1
0
1
0
1
0
1

(b) State table

01, 10

00, 11
0

00, 11
1

01, 10
(c) State diagram

FIGURE 5
...
We will illustrate the procedure first by using the characteristic table and
again by using the characteristic equation
...
Determine the flip-flop input equations in terms of the present state and input
variables
...
List the binary values of each input equation
...
Use the corresponding flip-flop characteristic table to determine the next-state
values in the state table
...
5
...
The circuit has no outputs; therefore, the state table
does not need an output column
...
) The circuit can be specified by the flip-flop input equations
JA = B KA = BxЈ
JB = xЈ KB = AЈx + AxЈ = A ᮍ x
The state table of the sequential circuit is shown in Table 5
...
The present-state and
input columns list the eight binary combinations
...
18
Sequential circuit with JK flip-flop

columns labeled flip-flop inputs are not part of the state table, but they are needed for
the purpose of evaluating the next state as specified in step 2 of the procedure
...
The next state of each
flip-flop is evaluated from the corresponding J and K inputs and the characteristic table
of the JK flip-flop listed in Table 5
...
There are four cases to consider
...
4
State Table for Sequential Circuit with JK Flip-Flops
Present
State

Input

Next
State

Flip-Flop
Inputs

A

B

x

A

B

JA

KA

JB

KB

0

0

0

0

1

0

0

1

0

0

0

1

0

0

0

0

0

1

0

1

0

1

1

1

1

1

0

0

1

1

1

0

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

1

0

0

0

0

0

1

1

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

Section 5
...
When J = 0 and K = 1, the next state is 0
...
When J = K = 1, the next-state bit is the complement of the present-state bit
...
JA and KA are both equal to 0 and the present state of A is 1
...
In the same row of the table, JB and
KB are both equal to 1
...

The next-state values can also be obtained by evaluating the state equations from the
characteristic equation
...
Determine the flip-flop input equations in terms of the present state and input
variables
...
Substitute the input equations into the flip-flop characteristic equation to obtain
the state equations
...
Use the corresponding state equations to determine the next-state values in the
state table
...
5
...
The characteristic equations for the flip-flops are obtained by substituting
A or B for the name of the flip-flop, instead of Q:
A(t + 1) = JAЈ + KЈA
B(t + 1) = JBЈ + KЈB
Substituting the values of JA and KA from the input equations, we obtain the state equation for A:
A(t + 1) = BAЈ + (BxЈ)Ј A = AЈB + ABЈ + Ax
The state equation provides the bit values for the column headed “Next State” for A in
the state table
...
Note that the columns in Table 5
...

The state diagram of the sequential circuit is shown in Fig
...
19
...


Analysis with T Flip-Flops
The analysis of a sequential circuit with T flip-flops follows the same procedure outlined
for JK flip-flops
...
19
State diagram of the circuit of Fig
...
18

the characteristic table listed in Table 5
...
5
...
It has two flip-flops A and B, one
input x, and one output y and can be described algebraically by two input equations and
an output equation:
TA = Bx
TB = x
y = AB
The state table for the circuit is listed in Table 5
...
The values for y are obtained from
the output equation
...

The state diagram of the circuit is shown in Fig
...
20(b)
...

When x = 0, the circuit remains in the same state
...
Here, the output depends on the present state only and is independent of the input
...


Mealy and Moore Models of Finite State Machines
The most general model of a sequential circuit has inputs, outputs, and internal states
...
Both are shown in Fig
...
21
...
5
x

Analysis of Clocked Sequential Circuits

215

A

T

y

Clk
R

0

T

0
1

00/0

B

Clk
R

1

1

11/1

1
0

Clock

(b) State diagram

FIGURE 5
...
5
State Table for Sequential Circuit with T Flip-Flops
Present
State

Input

Next
State

10/0
0

reset

(a) Circuit diagram

01/0

Output

A

B

x

A

B

y

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

1

0

0

1

1

1

0

0

1

0

0

1

0

0

1

0

1

1

1

0

1

1

0

1

1

1

1

1

1

0

0

1

216

Chapter 5

Synchronous Sequential Logic
Mealy Machine

Inputs

Next State
Combinational
Logic

State
Register

Output
Combinational
Logic

Outputs
(Mealy-type)

Clock
(a)

Moore Machine
Inputs

Next State
Combinational
Logic

State
Register

Output
Combinational
Logic

Outputs
(Moore-type)

Clock
(b)

FIGURE 5
...
In the Mealy model, the output is a function of both the present state and
the input
...
A circuit
may have both types of outputs
...
The Mealy model of a sequential
circuit is referred to as a Mealy FSM or Mealy machine
...

The circuit presented previously in Fig
...
15 is an example of a Mealy machine
...
The corresponding
state diagram in Fig
...
16 shows both the input and output values, separated by a slash
along the directed lines between the states
...
5
...
Here, the output is a function of
the present state only
...
5
...
The outputs are the flip-flop states marked inside the circles
...
5
...
The output
depends only on flip-flop values, and that makes it a function of the present state only
...

In a Moore model, the outputs of the sequential circuit are synchronized with the
clock, because they depend only on flip-flop outputs that are synchronized with the
clock
...
6

Synthesizable HDL Models of Sequential Circuits

217

cycle
...
In order to synchronize a Mealy-type circuit, the inputs of the sequential circuit
must be synchronized with the clock and the outputs must be sampled immediately
before the clock edge
...
Thus,
the output of the Mealy machine is the value that is present immediately before the
active edge of the clock
...
6

SYNTHESIZABLE HDL MODELS
OF SEQUENTIAL CIRCUITS
The Verilog HDL was introduced in Section 3
...
Combinational circuits were described
in Section 4
...
Behavioral models are abstract representations of the functionality of digital hardware
...
Historically, the abstraction has been described by truth tables,
state  tables, and state diagrams
...

This representation has “added value,” i
...
, it is important for you to know how to use,
because it can be simulated to produce waveforms demonstrating the behavior of the
machine
...
Behavior declared by
the keyword initial is called single-pass behavior and specifies a single statement or
a block statement (i
...
, a list of statements enclosed by either a begin
...
join keyword pair)
...
In practice, designers use single-pass behavior primarily to prescribe
stimulus signals in a test bench—never to model the behavior of a circuit—because
synthesis tools do not accept descriptions that use the initial statement
...
Both types of behaviors begin executing when
the simulator launches at time t = 0
...
A module may contain an arbitrary number of initial or always behavioral statements
...
Here’s a word description of how
an always statement works for a simple model of a D flip-flop: Whenever the rising
edge of the clock occurs, if the reset input is asserted, the output q gets 0; otherwise
the output Q gets the value of the input D
...
We’ll see shortly how to write this
description in Verilog
...
It begins its execution at the start
of simulation and expires after all of its statements have completed execution
...
12, the initial statement is useful for generating input
signals to simulate a design
...
The following are two possible ways to provide a free-running clock that operates for a specified number of cycles:
initial
begin
clock = 1'b0;
repeat (30)
#10 clock = ~clock;
end

initial
begin
clock = 1'b0;
end
initial 300 $finish;
always #10 clock = ~clock;

In the first version, the initial block contains two statements enclosed within the begin
and end keywords
...
The second statement
specifies a loop that reexecutes 30 times to wait 10 time units and then complement the
value of clock
...
In
the second version, the first initial behavior has a single statement that sets clock to 0 at
time = 0, and it then expires (causes no further simulation activity)
...
The system task finish causes the
simulation to terminate unconditionally after 300 time units have elapsed
...

end keyword pair
...
The three behavioral
statements in the second example can be written in any order
...
Note that the single-pass behavior never finishes executing and so does
not expire
...

The activity associated with either type of behavioral statement can be controlled by
a delay operator that waits for a certain time or by an event control operator that waits
for certain conditions to become true or for specified events (changes in signals) to
occur
...
The delay control operator suspends execution of statements until
a specified time has elapsed
...
Another operator @ is called the event control operator and is used to
suspend activity until an event occurs
...
g
...
g
...
The general form of this type of statement is
always @ (event control expression) begin
// Procedural assignment statements that execute when the condition is met
end

Section 5
...
The variables in the left-hand side of the
procedural statements must be of the reg data type and must be declared as such
...

The event control expression (also called the sensitivity list) specifies the events that
must occur to initiate execution of the procedural statements associated with the always
block
...
After
the last statement executes, the behavior waits for the event control expression to be
satisfied
...
The sensitivity list can specify levelsensitive events, edge-sensitive events, or a combination of the two
...
Level-sensitive events occur in combinational circuits and in latches
...
In synchronous sequential circuits, changes in flip-flops
occur only in response to a transition of a clock pulse
...
Verilog HDL takes care of
these conditions by providing two keywords: posedge and negedge
...
The 2001 and
2005 revisions to the Verilog language allow a comma-separated list for the event control expression (or sensitivity list):
always @(posedge clock, negedge reset)

// Verilog 2001, 2005

A procedural assignment is an assignment of a logic value to a variable within an
initial or always statement
...
12 with dataflow modeling
...
The updating of a continuous assignment is triggered whenever
an event occurs in a variable included on the right-hand side of its expression
...
For example, the clock signal in
the preceding example was complemented only when the statement clock = ~clock
executed; the statement did not execute until 10 time units after the simulation began
...

There are two kinds of procedural assignments: blocking and nonblocking
...
Blocking assignments use the symbol (=)
as the assignment operator, and nonblocking assignments use (< =) as the operator
...
Nonblocking assignments are executed concurrently by evaluating the set of expressions on the right-hand side of the list of statements; they do not
make assignments to their left-hand sides until all of the expressions are evaluated
...
Consider
these two procedural blocking assignments:
B=A
C=B+1

The first statement transfers the value of A into B
...
At the completion of the assignments, C
contains the value of A + 1
...
The value of A is kept in one storage location and
the value of B + 1 in another
...
In this case, C will
contain the original value of B, plus 1
...
e
...
Use nonblocking assignments when modeling concurrent execution (e
...
, edge-sensitive behavior such as synchronous, concurrent register transfers)
and when modeling latched behavior
...
They model the concurrent
operations of physical hardware synchronized by a common clock
...
Following these rules for using the assignment operators will
prevent conditions that lead synthesis tools astray and create mismatches between
the  behavior of a model and the behavior of physical hardware that is produced by a
synthesis tool
...
1 through 5
...
The D latch is said to be transparent because it responds to a change in data input
with a change in the output as long as the enable input is asserted—viewing the output
is the same as viewing the input
...
1 It has two inputs, D and enable, and one output, Q
...
Hardware latches respond to input signal
levels, so the two inputs are listed without edge qualifiers in the sensitivity list following
the @ symbol in the always statement
...
6

Synthesizable HDL Models of Sequential Circuits

221

is true (logic 1)
...

A D-type flip-flop is the simplest example of a sequential machine
...
2 describes two positive-edge D flip-flops in two modules
...
Output Q must be declared
as a reg data type in addition to being listed as an output
...
The keyword posedge ensures that the
transfer of input D into Q is synchronized by the positive-edge transition of Clk
...

HDL Example 5
...
5
...
2  (D-Type Flip-Flop)
// D flip-flop without reset
module D_FF (Q, D, Clk);
output Q;
input D, Clk;
reg
Q;
always @ (posedge Clk)
Q <= D;
endmodule
// D flip-flop with asynchronous reset (V2001, V2005)
module DFF (output reg Q, input D, Clk, rst);
always @ (posedge Clk, negedge rst)
if (!rst) Q <= 1'b0;
// Same as: if (rst == 0)
else Q <= D;
endmodule

1

The statement (single or block) associated with if (Boolean expression) executes if the Boolean expression
is true
...
A specific form of an if statement is used to describe such a flip-flop so that
the model can be synthesized by a software tool
...
For modeling hardware, one of the events must be a clock event
...
The
designer knows which signal is the clock, but clock is not an identifier that software tools
automatically recognize as the synchronizing signal of a circuit
...
The rules are simple to follow: (1) Each if or else if
statement in the procedural assignment statements is to correspond to an asynchronous
event, (2) the last else statement corresponds to the clock event, and (3) the asynchronous events are tested first
...
2
...
As long as rst is 0, Q is cleared to 0
...
Only if rst = 1 can the posedge clock event synchronously transfer D into Q
...
It is strongly recommended that all models of
edge-sensitive behavior include a reset (or preset) input signal; otherwise, the initial
state of the flip-flops of the sequential circuit cannot be determined
...

HDL Example 5
...
The circuit is described with the characteristic equations of the flip-flops:
Q(t + 1) = Q { T
Q(t + 1) = JQЈ + KЈQ

for a T flip-flop
for a JK flip-flop

The first module, TFF, describes a T flip-flop by instantiating DFF
...
12
...
The instantiation with
the value of DT replacing D in module DFF produces the required T flip-flop
...


HDL Example 5
...
6

Synthesizable HDL Models of Sequential Circuits

223

// JK flip-flop from D flip-flop and gates (V2001, 2005)
module JKFF (output reg Q, input J, K, Clk, rst);
wire JK;
assign JK = (J & ~Q) Խ (~K & Q);
// Instantiate D flip-flop
DFF JK1 (Q, JK, Clk, rst);
endmodule
// D flip-flop (V2001, V2005)
module DFF (output reg Q, input D, Clk, rst);
always @ (posedge Clk, negedge rst)
if (!rst) Q <= 1'b0;
else Q <= D;
endmodule

HDL Example 5
...
Here, we describe
the flip-flop by using the characteristic table rather than the characteristic equation
...
The case expression ({J, K}) is evaluated and compared with the
values in the list of statements that follows
...
Since the concatenation of J and K produces a two-bit number, it can
be equal to 00, 01, 10, or 11
...
The four possible conditions specify the value of the next state of Q after the application of a positive-edge clock
...
4 (JK Flip-Flop)
// Functional description of JK flip-flop (V2001, 2005)
module JK_FF (input J, K, Clk, output reg Q, output Q_b);
assign Q_b = ~ Q ;
always @ (posedge Clk)
case ({J,K})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= !Q;
endcase
endmodule

State diagram-Based HDL Models
An HDL model of the operation of a sequential circuit can be based on the format of the
circuit’s state diagram
...
5 for the
zero-detector machine described by the sequential circuit in Fig
...
15 and its state diagram
shown in Fig
...
16
...


224

Chapter 5

Synchronous Sequential Logic

The state of the flip-flops is declared with identifiers state and next_state
...
The state’s
binary assignment is done with a parameter statement
...
) The four states S0 through S3 are assigned
binary 00 through 11
...
The
former uses only two bits to store the constant, whereas the latter results in a binary number with 32 (or 64) bits because an unsized number is interpreted and sized as an integer
...
5 (Mealy Machine: Zero Detector)
// Mealy FSM zero detector (See Fig
...
15 and Fig
...
16)
Verilog 2001, 2005 syntax
module Mealy_Zero_Detector (
output reg y_out,
input x_in, clock, reset
);
reg [1: 0]
state, next_state;
parameter
S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge clock, negedge reset) Verilog 2001, 2005 syntax
if (reset == 0) state <= S0;
else state <= next_state;
always @ (state, x_in)
// Form the next state
case (state)
S0:
if (x_in) next_state = S1; else next_state = S0;
S1:
if (x_in) next_state = S3; else next_state = S0;
S2:
if (~x_in) next_state = S0; else next_state = S2;
S3:
if (x_in) next_state = S2; else next_state = S0;
endcase
always @ (state, x_in)
case (state)
S0:
y_out = 0;
S1, S2, S3: y_out = ~x_in;
endcase
endmodule

// Form the Mealy output

module t_Mealy_Zero_Detector;
wire
t_y_out;
reg
t_x_in, t_clock, t_reset;
Mealy_Zero_Detector M0 (t_y_out, t_x_in, t_clock, t_reset);
initial #200 $finish;
initial begin t_clock = 0; forever #5 t_clock = ~t_clock; end
initial fork
t_reset = 0;
#2 t_reset = 1;
#87 t_reset = 0;
#89 t_reset = 1;

Section 5
...
5 detects a 0 following a sequence of 1s in a serial bit
stream
...
The first always statement resets the circuit to the initial
state S0 = 00 and specifies the synchronous clocked operation
...
This means that any
change in the value of next_state in the second always block can affect the value of state
only as a result of a posedge event of clock
...
The value
assigned to state by the nonblocking assignment is the value of next_state immediately
before the rising edge of clock
...
 5
...

The third always block specifies the output as a function of the present state and the
input
...
Note that the value of output y_out may change if the value
of input x_in changes while the circuit is in any given state
...
In addition, the second and third always blocks detect changes in x_in and
update next_state and y_out accordingly
...
5
...
Notice how t_y_out responds to changes in both the state and the input, and has
a glitch (a transient logic value)
...
The Mealy glitch
in t_y_out is due to the (intentional) dynamic behavior of t_x_in
...
22
Simulation output of Mealy_Zero_Detector

to a value of 0 immediately before the clock, and at the clock, the state makes a transition
from 0 to 1, which is consistent with Fig
...
16
...

The description of waveforms in the test bench uses the fork
...
Statements with the fork
...
2 It is usually
more convenient to use the fork
...
end block in
describing waveforms
...

How does our Verilog model Mealy_Zero_Detector correspond to hardware? The first
always block corresponds to a D flip-flop implementation of the state register in Fig
...
21;
the second always block is the combinational logic block describing the next state; the
third always block describes the output combinational logic of the zero-detecting Mealy
machine
...
The second and third always blocks describe combinational logic, which is level sensitive, so they use the blocking (=) assignment operator
...
join block completes execution when the last executing statement within it completes its
execution
...
6

Synthesizable HDL Models of Sequential Circuits

227

Their sensitivity lists include both the state and the input because their logic must respond
to a change in either or both of them
...
Notice that the reset signal is associated with the always block that
synchronizes the state transitions
...

Because the reset condition is included in the description of the state transitions, there
is no need to include it in the combinational logic that specifies the next state and the
output, and the resulting description is less verbose, simpler, and more readable
...
6 presents the Verilog behavioral model of the Moore FSM shown
in Fig
...
18 and having the state diagram given in Fig
...
19
...
e
...
e
...
The present state
of the circuit is identified by the variable state, and its transitions are triggered by the
rising edge of the clock according to the conditions listed in the case statement
...
In this example, the output of the circuits is independent of the input and
is taken directly from the outputs of the flip-flops
...
Figure 5
...
Here
are some important observations: (1) the output depends on only the state, (2) reset
“on-the-fly” forces the state of the machine back to S0 (00), and (3) the state transitions
are consistent with Fig
...
19
...
6 (Moore Machine: Zero Detector)
// Moore model FSM (see Fig
...
19)
Verilog 2001, 2005 syntax
module Moore_Model_Fig_5_19 (
output [1: 0]
y_out,
input
x_in, clock, reset
);
reg [1: 0]
state;
parameter
S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge clock, negedge reset)
if (reset == 0) state <= S0;
// Initialize to state S0
else case (state)
S0:
if (~x_in) state <= S1; else state <= S0;
S1:
if (x_in) state <= S2; else state <= S3;
S2:
if (~x_in) state <= S3; else state <= S2;
S3:
if (~x_in) state <= S0; else state <= S3;
endcase
assign y_out = state;
endmodule

// Output of flip-flops

228

Chapter 5

Synchronous Sequential Logic
0

30

60

90

t_clock
t_reset

reset on-the-fly

t_x_in
state[1:0]

0

1

2

3

0

1

0

1

3

t_y_out[1:0]

0

1

2

3

0

1

0

1

3

FIGURE 5
...
6

Structural Description of Clocked Sequential Circuits
Combinational logic circuits can be described in Verilog by a connection of gates
(primitives and UDPs), by dataflow statements (continuous assignments), or by levelsensitive cyclic behaviors (always blocks)
...
One way to describe a sequential circuit uses a combination of dataflow
and behavioral statements
...
The
combinational part can be described with assign statements and Boolean equations
...

The structural description of a Moore-type zero detector sequential circuit is shown
in HDL Example 5
...
We want to encourage the reader to consider alternative ways to
model a circuit, so as a point of comparison, we first present Moore_Model_Fig_5_20,
a Verilog behavioral description of a binary counter having the state diagram examined
earlier shown in Fig
...
20(b)
...
An alternative style, used in Moore_Model_STR_Fig_5_20, represents the structure shown in Fig
...
20(a)
...
The first describes the circuit of
Fig
...
20(a)
...
We also
show two ways to model the T flip-flop
...
The second
model describes the behavior of the toggle flip-flop in terms of its characteristic equation
...
Nonetheless, the models are interchangeable and will synthesize
to the same hardware circuit
...
The sequential circuit is a two-bit binary counter controlled
by input x_in
...
Flip-flops

Section 5
...
The flip-flop input
equations and the output equation are evaluated with continuous assignment (assign)
statements having the corresponding Boolean expressions
...

The second module describes the T flip-flop
...
The operation of the flip-flop is specified by its characteristic
equation, Q(t + 1) = Q { T
...
The stimulus module provides
common inputs to the circuits to simultaneously display their output responses
...
The second initial
block specifies a toggling of input x_in that occurs at the negative edge transition of
the clock
...
5
...
The pair (A, B) goes
through the binary sequence 00, 01, 10, 11, and back to 00
...
If x_in = 0, the
count does not change
...
This
verifies the main functionality of the circuit, but not a recovery from an unexpected
reset event
...
7 (Binary Counter_Moore Model)
// State-diagram-based model (V2001, 2005)
module Moore_Model_Fig_5_20 (
output y_out,
input x_in, clock, reset
);
reg [1: 0]
state;
parameter
S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge clock, negedge reset)
if (reset == 0) state <= S0;
// Initialize to state S0
else case (state)
S0:
if (x_in) state <= S1; else state <= S0;
S1:
if (x_in) state <= S2; else state <= S1;
S2:
if (x_in) state <= S3; else state <= S2;
S3:
if (x_in) state <= S0; else state <= S3;
endcase
assign y_out = (state == S3);
endmodule

// Output of flip-flops

// Structural model
module Moore_Model_STR_Fig_5_20 (
output
y_out, A, B,
input
x_in, clock, reset
);
wire
TA, TB;
// Flip-flop input equations
assign TA = x_in & B;

230

Chapter 5

Synchronous Sequential Logic

assign TB = x_in;
// Output equation
assign y_out = A & B;
// Instantiate Toggle flip-flops
Toggle_flip_flop_3 M_A (A, TA, clock, reset);
Toggle_flip_flop_3 M_B (B, TB, clock, reset);
endmodule
module Toggle_flip_flop (Q, T, CLK, RST_b);
output
Q;
input
T, CLK, RST_b;
reg
Q;
always @ (posedge CLK, negedge RST_b)
if (RST_b == 0) Q <= 1'b0;
else if (T) Q <= ~Q;
endmodule
// Alternative model using characteristic equation
// module Toggle_flip_flop (Q, T, CLK, RST_b);
// output Q;
// input
T, CLK, RST_b;
// reg
Q;
// always @ (posedge CLK, negedge RST)
// if (RST_b == 0) Q <= 1'b0;
// else Q <= Q ^ T;
// endmodule
module t_Moore_Fig_5_20;
wire
t_y_out_2, t_y_out_1;
reg
t_x_in, t_clock, t_reset;
Moore_Model_Fig_5_20
Moore_Model_STR_Fig_5_20
initial #200 $finish;
initial begin
t_reset = 0;
t_clock = 0;
#5 t_reset = 1;
repeat (16)
#5 t_clock = ~t_clock;
end
initial begin
t_x_in = 0;
#15 t_x_in = 1;
repeat (8)
#10 t_x_in = ~t_x_in;
end
endmodule

M1(t_y_out_1, t_x_in, t_clock, t_reset);
M2 (t_y_out_2, A, B, t_x_in, t_clock, t_reset);

Section 5
...
24
Simulation output of HDL Example 5
...
7

S TAT E R E D U C T I O N A N D A S S I G N M E N T
The analysis of sequential circuits starts from a circuit diagram and culminates in a state
table or diagram
...
Design procedures are presented in
Section 5
...
Two sequential circuits may exhibit the same input–output behavior, but
have a different number of internal states in their state diagram
...
In general, reducing the number of flipflops reduces the cost of a circuit
...
State-reduction algorithms are concerned with procedures for
reducing the number of states in a state table, while keeping the external input–output
requirements unchanged
...
An unpredictable effect in reducing the number of flip-flops is that sometimes the equivalent
circuit (with fewer flip-flops) may require more combinational gates to realize its next
state and output logic
...
We start with a sequential circuit whose specification is given in the state diagram of Fig
...
25
...
For that reason, the states marked inside the circles are denoted

232

Chapter 5

Synchronous Sequential Logic
0/0
0/0
a
0/0
1/0
0/0

0/0

b
1/0

g

d

1/0 0/0

e

1/1

1/1

0/0

c

1/1

f

1/1

FIGURE 5
...
This is in contrast to a binary counter,
wherein the binary value sequence of the states themselves is taken as the outputs
...
As an example, consider the input sequence
01010110100 starting from the initial state a
...
From the state diagram, we obtain
the output and state sequence for the given input sequence as follows: With the circuit
in initial state a, an input of 0 produces an output of 0 and the circuit remains in state a
...
With present state b and an input of 0, the output is 0 and the next state is c
...
The next state
is written on top of the next column
...

Now let us assume that we have found a sequential circuit whose state diagram has
fewer than seven states, and suppose we wish to compare this circuit with the circuit
whose state diagram is given by Fig
...
25
...
The problem of state reduction is to find ways of reducing the number of
states in a sequential circuit without altering the input–output relationships
...
7

State Reduction and Assignment

233

We now proceed to reduce the number of states for this example
...
The state table of the circuit is listed in Table 5
...

The following algorithm for the state reduction of a completely specified state table
is given here without proof: “Two states are said to be equivalent if, for each member of
the set of inputs, they give exactly the same output and send the circuit either to the
same state or to an equivalent state
...

Now apply this algorithm to Table 5
...
Going through the state table, we look for two
present states that go to the same next state and have the same output for both input
combinations
...
Therefore, states g and e are equivalent, and one of these states can be removed
...
7
...
”
Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1,
respectively
...

Therefore, states f and d are equivalent, and state f can be removed and replaced by d
...
8
...
5
...
This state diagram satisfies the
original input–output specifications and will produce the required output sequence for
any given input sequence
...
5
...
6
State Table
Next State

Output

x‫0؍‬

x‫1؍‬

x‫0؍‬

x‫1؍‬

a
b
c
d
e
f

a
c
a
e
a
g

b
d
d
f
f
f

0
0
0
0
0
0

0
0
0
1
1
1

g

a

f

0

1

Present State

e
0
0

a

234

Chapter 5

Synchronous Sequential Logic
Table 5
...
8
Reduced State Table
Next State

Output

x‫0؍‬

a
b
c
d
e

x‫1؍‬

x‫0؍‬

x‫1؍‬

a
c
a
e
a

Present State

b
d
d
d
d

0
0
0
0
0

0
0
0
1
1

In fact, this sequence is exactly the same as that obtained for Fig
...
25 if we replace g by
e and f by d
...
By judicious use of the table, it is possible
to determine all pairs of equivalent states in a state table
...
26
Reduced state diagram

c

Section 5
...
In
general, reducing the number of states in a state table may result in a circuit with
less equipment
...
In
actual practice designers may skip this step because target devices are rich in
resources
...
For a circuit with m states, the codes must contain n bits, where 2n Ú m
...
If the state table of Table 5
...
If the
state table of Table 5
...
Unused states are treated as don’t-care conditions during the
design
...

The simplest way to code five states is to use the first five integers in binary counting
order, as shown in the first assignment of Table 5
...
Another similar assignment is the
Gray code shown in assignment 2
...
This code makes it easier for the Boolean functions
to be placed in the map for simplification
...
This
configuration uses as many bits as there are states in the circuit
...
This type of assignment uses one flipflop per state, which is not an issue for register-rich field-programmable gate arrays
...
) One-hot encoding usually leads to simpler decoding logic for the next state
and output
...
9
Three Possible Binary State Assignments
State

Assignment 1,
Binary

Assignment 2,
Gray Code

Assignment 3,
One-Hot

a
b
c
d

000
001
010
011

000
001
011
010

00001
00010
00100
01000

e

100

110

10000

236

Chapter 5

Synchronous Sequential Logic
Table 5
...
This trade-off is not guaranteed, so it must be
evaluated for a given design
...
10 is the reduced state table with binary assignment 1 substituted for the letter symbols of the states
...
The binary form of the state table is used to derive the nextstate and output-forming combinational logic part of the sequential circuit
...

Sometimes, the name transition table is used for a state table with a binary assignment
...

In this book, we use the same name for both types of state tables
...
8

DESIGN PROCEDURE
Design procedures or methodologies specify hardware that will implement a desired
behavior
...
The sequential building block used by synthesis tools is the D flip-flop
...
In fact, designers generally do not concern themselves with the type of flip-flop; rather, their focus is on correctly describing
the sequential functionality that is to be implemented by the synthesis tool
...

The design of a clocked sequential circuit starts from a set of specifications and culminates in a logic diagram or a list of Boolean functions from which the logic diagram
can be obtained
...
The first step in the
design of sequential circuits is to obtain a state table or an equivalent representation,
such as a state diagram
...
The
design of the circuit consists of choosing the flip-flops and then finding a combinational
3

We will examine later another important representation of a machine’s behavior—the algorithmic state
machine (ASM) chart
...
8

Design Procedure

237

gate structure that, together with the flip-flops, produces a circuit which fulfills the stated
specifications
...
The combinational circuit is
derived from the state table by evaluating the flip-flop input equations and output equations
...
In this way, the techniques of combinational circuit design can be applied
...
From the word description and specifications of the desired operation, derive a
state diagram for the circuit
...
Reduce the number of states if necessary
...
Assign binary values to the states
...
Obtain the binary-coded state table
...
Choose the type of flip-flops to be used
...
Derive the simplified flip-flop input equations and output equations
...
Draw the logic diagram
...
It is necessary that the designer use intuition and experience to arrive at the correct interpretation of the circuit specifications, because word
descriptions may be incomplete and inexact
...
Although there are formal procedures for state reduction and assignment (steps 2 and 3), they are seldom used by experienced designers
...

The part of the design that follows a well-defined procedure is referred to as synthesis
...

The first step is a critical part of the process, because succeeding steps depend on it
...

Suppose we wish to design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line (i
...
, the input is a serial bit
stream)
...
5
...
It is derived by
starting with state S0, the reset state
...
If the next input is 1, the
change is to state S2 to indicate the arrival of two consecutive 1’s, but if the input is 0,
the state goes back to S0
...
If more
1’s are detected, the circuit stays in S3
...
In this
way, the circuit stays in S3 as long as there are three or more consecutive 1’s received
...


238

Chapter 5

Synchronous Sequential Logic
0
0
S0/0

1

S1/0

0

0

S3/1

1

S2/0

1

1

FIGURE 5
...
In fact, we can design the circuit by using an HDL
description of the state diagram and the proper HDL synthesis tools to obtain a
synthesized netlist
...
6 in Section 5
...
) To design the circuit by hand, we need to assign
binary codes to the states and list the state table
...
11
...
5
...

We choose two D flip-flops to represent the four states, and we label their outputs
A and B
...
The characteristic equation of the
D flip-flop is Q(t + 1) = DQ, which means that the next-state values in the state
table specify the D input condition for the flip-flop
...
11
State Table for Sequence Detector
Present
State

Input

Next
State

Output

A

B

x

A

B

y

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
0
1

0
1
0
0
0
1
0
1

0
0
0
0
0
0
1
1

Section 5
...
28
K-Maps for sequence detector

can be obtained directly from the next-state columns of A and B and expressed in
sum-of-minterms form as
A(t + 1) = D (A, B, x) = ©(3, 5, 7)
A
B(t + 1) = DB(A, B, x) = ©(1, 5, 7)
y(A, B, x) = ©(6, 7)
where A and B are the present-state values of flip-flops A and B, x is the input, and DA
and DB are the input equations
...

The Boolean equations are simplified by means of the maps plotted in Fig
...
28
...
Software tools
automatically infer and select the D-type flip-flop from a properly written HDL model
...
5
...


Excitation Tables
The design of a sequential circuit with flip-flops other than the D type is complicated
by the fact that the input equations for the circuit must be derived indirectly from the
state table
...
This is not the case for the JK and T types of flip-flops
...

The flip-flop characteristic tables presented in Table 5
...
These tables are useful

240

Chapter 5

Synchronous Sequential Logic

D

A

Clk
x

D

B
Clk
BЈ

Clock

y

FIGURE 5
...
During the design process, we usually know the transition from the present state to the
next state and wish to find the flip-flop input conditions that will cause the required
transition
...
Such a table is called an excitation table
...
12 shows the excitation tables for the two flip-flops (JK and T)
...
There are four
possible transitions from the present state to the next state
...
The symbol X in the tables represents a don’t-care condition, which
means that it does not matter whether the input is 1 or 0
...
When both present state
and next state are 0, the J input must remain at 0 and the K input can be either 0 or 1
...
8

Design Procedure

241

Table 5
...
If the flip-flop is to have a transition from the 0-state
to the 1-state, J must be equal to 1, since the J input sets the flip-flop
...
If K = 0, the J = 1 condition sets the flip-flop as required; if
K = 1 and J = 1, the flip-flop is complemented and goes from the 0-state to the
1-state as required
...
For a transition from the 1-state to the 0-state, we must have K = 1,
since the K input clears the flip-flop
...

The excitation table for the T flip-flop is shown in part (b)
...
Therefore, when the state of
the flip-flop must remain the same, the requirement is that T = 0
...


Synthesis Using JK Flip-Flops
The manual synthesis procedure for sequential circuits with JK flip-flops is the same as
with D flip-flops, except that the input equations must be evaluated from the presentstate to the next-state transition derived from the excitation table
...
13
...

The flip-flop inputs are derived from the state table in conjunction with the excitation
table for the JK flip-flop
...
13, we have a transition
for flip-flop A from 0 in the present state to 0 in the next state
...
12, for the JK
flip-flop, we find that a transition of states from present state 0 to next state 0 requires
that input J be 0 and input K be a don’t-care
...
Since the first row also shows a transition for flip-flop B from 0
in the present state to 0 in the next state, 0 and X are inserted into the first row under JB
and KB, respectively
...
From the excitation table, we find that a transition from 0 to 1 requires that J be 1 and K be a don’t-care, so 1 and X are copied into

242

Chapter 5

Synchronous Sequential Logic
Table 5
...
The process is continued for each row in
the table and for each flip-flop, with the input conditions from the excitation table copied
into the proper row of the particular flip-flop being considered
...
13 specify the truth table for the input equations as a
function of present state A, present state B, and input x
...
5
...
The next-state values are not used during the simplification,

A

B

Bx
00
m0

01
m1

11

10

m3

1
m4

m5

X

1

m7

X

00
m0

m2

0
A

A

B

Bx

0

X
m4

m6

X

X

A

01
m1

11
m3

X
m5

X
m7

m6

x
KA ϭ Bx
B

00

01
m1

m4

1

11
m3

1

0
A

B

Bx
m0

m5

10

A

Bx
00

m2

X
m2

1

X

1

1

x
JA ϭ BxЈ

A

10
m2

m0

X

0

x
JB ϭ x

FIGURE 5
...
8

Design Procedure

243

x
A

J
Clk
K

AЈ

J

B
Clk

K

BЈ

Clock

FIGURE 5
...
Note the
advantage of using JK-type flip-flops when sequential circuits are designed manually
...
If there are unused states in the state table, there
will be additional don’t-care conditions in the map
...

The four input equations for the pair of JK flip-flops are listed under the maps of
Fig
...
30
...
5
...


Synthesis Using T Flip-Flops
The procedure for synthesizing circuits using T flip-flops will be demonstrated by designing a binary counter
...
The state diagram of a three-bit counter is shown in Fig
...
32
...
32
State diagram of three-bit binary counter

244

Chapter 5

Synchronous Sequential Logic

seen from the binary states indicated inside the circles, the flip-flop outputs repeat the
binary count sequence with a return to 000 after 111
...
Remember that
state transitions in clocked sequential circuits are initiated by a clock edge; the flip-flops
remain in their present states if no clock is applied
...
From this point of
view, the state diagram of a counter does not have to show input and output values along
the directed lines
...
The next state of a counter depends entirely on its
present state, and the state transition occurs every time the clock goes through a transition
...
14 is the state table for the three-bit binary counter
...
Binary counters are constructed most efficiently with T
flip-flops because of their complement property
...
As an illustration, consider the flip-flop
input entries for row 001
...
Comparing these two counts, we note that A2 goes
from 0 to 0, so T is marked with 0 because flip-flop A2 must not change when a clock
A2
occurs
...
Similarly, A0 goes from 1 to 0, indicating that
it must be complemented, so T is marked with a 1
...
Going from all 1’s to all 0’s
requires that all three flip-flops be complemented
...
5
...
Note that T
A0
has 1’s in all eight minterms because the least significant bit of the counter is complemented with each count
...
The input equations listed under each map specify the combinational part of the counter
...
14
State Table for Three-Bit Counter
Present State

Next State

Flip-Flop Inputs

A2

A1

A0

A2

A1

A0

TA2

TA1

TA0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

0
0
0
1
0
0
0
1

0
1
0
1
0
1
1
1

1
1
1
1
1
1
1
1

Problems

A2

A1

A1A0
00
m0

01

11

m1

m3

0
m5

m7

1

A1

A1A0
00

m2

m0

1
m4

A2

A2

10

01
m1

0
m6

1

m3

1
m4

A2

11

m5

1

A2

10

00
m0

0

1
m7

1

A1

A1A0

m2

m6

1

01

11

m1

1
m4

A2

1

m3

1
m5

1

10
m2

1
m7

1

A0

1
m6

1

1

x

TA1 ϭ A0

TA0 ϭ 1

A0
TA2 ϭ A1A0

245

FIGURE 5
...
34
Logic diagram of three-bit binary counter

the logic diagram of the counter, as shown in Fig
...
34
...


PROBLEMS
(Answers to problems marked with * appear at the end of the book
...
)
Note: For each problem that requires writing and verifying an HDL model, a test plan should be
written to identify which functional features are to be tested during the simulation and how they
will be tested
...
The test plan is to guide development
of a test bench that will implement the plan
...
If synthesis tools and an ASIC cell library are available, the Verilog
descriptions developed for Problems 5
...
42 can be assigned as synthesis exercises
...
The same exercises can be assigned if an FPGA tool suite is
available
...
1

The D latch of Fig
...
6 is constructed with four NAND gates and an inverter
...
In each case, draw the logic diagram
and verify the circuit operation
...
An inverter
may be needed
...
Inverters may be needed
...
This can be done by connecting
the output of the upper gate in Fig
...
6 (the gate that goes to the SR latch) to the input
of the lower gate (instead of the inverter output)
...
2

Construct a JK flip-flop using a D flip-flop, a two-to-one-line multiplexer, and an inverter
...
34
...
3

Show that the characteristic equation for the complement output of a JK flip-flop is
QЈ(t + 1) = JЈQЈ + KQ

5
...

(a) Tabulate the characteristic table
...

(c) Tabulate the excitation table
...


5
...
Also, explain the difference among a Boolean equation, a state equation,
a characteristic equation, and a flip-flop input equation
...
6

A sequential circuit with two D flip-flops A and B, two inputs, x and y; and one output z
is specified by the following next-state and output equations (HDL—see Problem 5
...

(b) List the state table for the sequential circuit
...


5
...
It consists
of a full-adder circuit connected to a D flip-flop, as shown in Fig
...
7
...

x
y

S

Full
adder

C

Q

D
Clk

FIGURE P5
...
8* Derive the state table and the state diagram of the sequential circuit shown in Fig
...
8
...
(HDL—see Problem 5
...
)

A

AЈ

Clk

BЈ

Clk

T

B

T
Clock

FIGURE P5
...
9

A sequential circuit has two JK flip-flops A and B and one input x
...

(b) Draw the state diagram of the circuit
...
10 A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z
...

(b) Tabulate the state table
...

5
...
5
...

(b) Find all of the equivalent states in Fig
...
16 and draw a simpler, but equivalent, state
diagram
...


248

Chapter 5

Synchronous Sequential Logic

5
...

(b) * Tabulate the reduced state table
...

5
...

(b) The reduced state table from the previous problem
...

5
...
9 to the states in Table 5
...

5
...
Design the sequential circuit specified by the state table and show that it is equivalent to Fig
...
12(a)
...
16 Design a sequential circuit with two D flip-flops A and B, and one input x_in
...
When x_in = 1, the circuit
goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats
...
When x_in =1, the circuit
goes through the state transitions from 00 to 11, to 01, to 10, back to 00, and repeats
...
38
...
17 Design a one-input, one-output serial 2’s complementer
...
The circuit can be reset
asynchronously to start and end the operation
...
39
...
18* Design a sequential circuit with two JK flip-flops A and B and two inputs E and F
...
When E = 1 and F = 1, the
circuit goes through the state transitions from 00 to 01, to 10, to 11, back to 00, and repeats
...
(HDL—see Problem 5
...
)
5
...
The
state diagram is shown in Fig
...
19
...
Analyze the circuit obtained from the design to determine
the effect of the unused states
...
41
...

(b) Use JK flip-flops in the design
...
19
5
...
5
...

5
...
22 Draw the waveform generated by the statements below:
(a) initial begin
w = 0; #10 w = 1; # 40 w = 0; # 20 w = 1; #15 w = 0;
end
(b) initial fork
w = 0; #10 w = 1; # 40 w = 0; # 20 w = 1; #15 w = 0;
join
5
...

(a) RegA = 125;
RegB = RegA;

(b) RegA <= 125;
RegB <= RegA;

What are the values of RegA and RegB after execution?
5
...

5
...
Write and verify an HDL
behavioral description of this component
...
26 Write and verify an HDL behavioral description of the JK flip-flop using an if-else statement
based on the value of the present state
...

(b) Specify how the J and K inputs affect the output of the flip-flop at each clock tick
...
27 Rewrite and verify the description of HDL Example 5
...

5
...
5
...


250

Chapter 5

Synchronous Sequential Logic

(a) Write the HDL description of the state diagram (i
...
, behavioral model)
...
e
...

(c) Write an HDL stimulus with a sequence of inputs: 00, 01, 11, 10
...

5
...
P5
...
Write a test bench and verify the functionality of the description
...
30 Draw the logic diagram for the sequential circuit described by the following HDL module:
module Seq_Ckt (input A, B, C, E output reg Q,input CLK,);
reg E;
always @ (posedge CLK)
begin
E <= A || B;
Q <= E && C;
end
endmodule
5
...
30 be written to have the same behavior when
the assignments are made with = instead of with <= ?
5
...
end block write a Verilog description of the
waveforms shown in Fig
...
32
...
join block
...
32
Waveforms for Problem 5
...
33 Explain why it is important that the stimulus signals in a test bench be synchronized to the
inactive edge of the clock of the sequential circuit that is to be tested
...
34 Write and verify an HDL structural description of the machine having the circuit diagram
(schematic) shown in Fig
...
5
...
35 Write and verify an HDL model of the sequential circuit described in Problem 5
...

5
...
P5
...

5
...
5
...
38
5
...
40
5
...
42
5
...
44
5
...
46

251

and 5
...
Write a test bench to compare the state sequences and input–output behaviors
of the two machines
...
16
...
17

...
18
...
19
...
8 in
Chapter 4
...
5
...

Write and verify an HDL behavioral description of the three-bit binary counter in Fig
...
34
...

Write and verify an HDL behavioral description of the sequence detector described in Fig
...
27

...
When x_in
changes from 0 to 1, the output y_out is to assert for three cycles, regardless of the value
of x_in, and then de-assert for two cycles before the machine will respond to another
assertion of x_in
...

(a) Draw the state diagram of the machine
...


5
...
The machine is controlled by a single input, Run, so that counting
occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count
when Run is re-asserted
...

5
...
P5
...

Develop a test bench and demonstrate that the machine state transitions and output correspond to its state diagram
...
48

0/ 0

252

Chapter 5

Synchronous Sequential Logic

5
...
P5
...

Develop a test bench and demonstrate that the machine's state transitions and output
correspond to its state diagram
...
49
5
...
The machine
is to monitor the input and remain in its initial state until a second sample of x_in is detected
to be 1
...
When the fourth assertion of x_in is detected the
machine is to return to its initial state and resume monitoring of x_in
...

(b) Write and verify a Verilog model of the machine
...
51 Draw the state diagram of the machine described by the Verilog model given below
...
52 Draw the state diagram of the machine described by the Verilog model given below
...
53 Draw a state diagram and write a Verilog model of a Mealy synchronous state machine
having a single input, x_in, and a single output y_out, such that y_out is asserted if the total
number of 1’s received is a multiple of 3
...
54 A synchronous Moore machine has two inputs, x1, and x2, and output y_out
...
Develop
a state diagram and a write a Verilog behavioral model of the machine
...

5
...

5
...

5
...

5
...
55
...
59 Write and verify a Verilog structural model of the counter described in Problem 5
...

5
...
, 9, 0, 1, 2,
...

2
...

4
...

6
...

8
...

10
...

12
...


Bhasker, J
...
Allentown, PA: Star Galaxy Press
...

Bhasker, J
...
Verilog HDL Synthesis
...

Ciletti, M
...
1999
...
Upper
Saddle River, NJ: Prentice Hall
...
L
...
Logic Design of Digital Systems, 3rd ed
...

Gajski, D
...
1997 Principles of Digital Design
...


...
P
...
Introduction to Digital Logic Design
...

Katz, R
...
2005
...
Upper Saddle River, NJ: Prentice Hall
...
M
...
R
...
2007 Logic and Computer Design Fundamentals & Xilinx

...
3 Student Edition, 4th ed
...

Nelson, V
...
, H
...
Nagle, J
...
Irwin, and B
...
Carroll
...
Digital Logic Circuit
Analysis and Design
...

Palnitkar, S
...
Verilog HDL: A Guide to Digital Design and Synthesis
...

Roth, C
...
2009
...
St
...

Thomas, D
...
and P
...
Moorby, 2002
...
Boston: Kluwer Academic Publishers
...
F
...
Digital Design: Principles and Practices, 4th ed
...


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One-hot/cold codes

Chapter 6

Registers and Counters

6
...
The
flip‐flops are essential because, in their absence, the circuit reduces to a purely combinational
circuit (provided that there is no feedback among the gates)
...
Circuits that
include flip‐flops are usually classified by the function they perform rather than by the name
of the sequential circuit
...

A register is a group of flip‐flops, each one of which shares a common clock and is
capable of storing one bit of information
...
In addition to the flip‐flops, a
register may have combinational gates that perform certain data‐processing tasks
...
The flip‐flops hold the binary information, and the gates
determine how the information is transferred into the register
...
The gates in the counter are connected in such a way as to produce the
prescribed sequence of states
...

Various types of registers are available commercially
...
Figure 6
...
The common clock
input triggers all flip‐flops on the positive edge of each pulse, and the binary data available
at the four inputs are transferred into the register
...
The four
255

256

Chapter 6

Registers and Counters
I0

A0

D
C

R

I1

A1

D
C

R

I2

A2

D
C

R

I3

A3

D
C

R

Clock Clear_b

FIGURE 6
...

The input Clear_b goes to the active‐low R (reset) input of all four flip‐flops
...
The Clear_b input is useful for clearing the register to all 0’s prior to its clocked operation
...
1

Registers

257

at logic 1 (i
...
, de-asserted) during normal clocked operation
...


Register with Parallel Load
Registers with parallel load are a fundamental building block in digital systems
...
Synchronous digital systems have a master clock generator that supplies a continuous train of clock
pulses
...
The master
clock acts like a drum that supplies a constant beat to all parts of the system
...
The transfer of new information into a register is referred to as loading or updating the register
...
A clock edge applied to the C
inputs of the register of Fig
...
1 will load all four inputs in parallel
...
In the first case, the data bus driving the
register would be unavailable for other traffic
...
However, inserting gates into the clock path is ill advised because it means that
logic is performed with clock pulses
...
To fully synchronize
the system, we must ensure that all clock pulses arrive at the same time anywhere in the
system, so that all flip‐flops trigger simultaneously
...
For this
reason, it is advisable to control the operation of the register with the D inputs, rather
than controlling the clock in the C inputs of the flip‐flops
...

A four‐bit data‐storage register with a load control input that is directed through gates
and into the D inputs of the flip‐flops is shown in Fig
...
2
...
The load input to the register determines the action to be
taken with each clock pulse
...
When the load
input is 0, the outputs of the flip‐flops are connected to their respective inputs
...
With each clock edge, the D input determines the next state of
the register
...
e
...
The clock pulses are applied to the C inputs without interruption
...
The transfer of information from the data inputs or the outputs of
the register is done simultaneously with all four bits in response to a clock edge
...
2
Four‐bit register with parallel load

6
...
The logical configuration of a shift
register consists of a chain of flip‐flops in cascade, with the output of one flip‐flop connected to the input of the next flip‐flop
...

The simplest possible shift register is one that uses only flip‐flops, as shown in Fig
...
3
...
This
shift register is unidirectional (left‐to‐right)
...
2
Serial
input

SI

D

D

C

D

C

Shift Registers
SO

D

C

259

Serial
output

C

CLK

FIGURE 6
...
The configuration does not support a left shift
...
The serial
output is taken from the output of the rightmost flip‐flop
...
As with the
data register discussed in the previous section, the clock’s signal can be suppressed by gating the clock signal to prevent the register from shifting
...
When the clock action
is not suppressed, the other channel of the mux provides a datapath to the cell
...
If, however, the shift register of Fig
...
3
is used, the shift can be controlled with an input by connecting the clock through an AND
gate
...
Note that the simplified schematics do not show a
reset signal, but such a signal is required in practical designs
...
Information is transferred one bit at
a time by shifting the bits out of the source register and into the destination register
...

The serial transfer of information from register A to register B is done with shift
registers, as shown in the block diagram of Fig
...
4(a)
...
To prevent the loss of information
stored in the source register, the information in register A is made to circulate by connecting the serial output to its serial input
...
The
shift control input determines when and how many times the registers are shifted
...
(This practice can be problematic
because it may compromise the clock path of the circuit, as discussed earlier
...
6
...
Then the control unit that
supervises the transfer of data must be designed in such a way that it enables the shift

260

Chapter 6

Registers and Counters

SIA

SOA

Shift register A

SIB

SOB

CLK

CLK

Clock
Shift
control

Shift register B

(a) Block diagram

Clock

Shift
control

CLK

T1

T2

T3

T4

(b) Timing diagram

FIGURE 6
...
This design is shown in the timing diagram of Fig
...
4(b)
...
The next four clock pulses find the shift control signal in the active
state, so the output of the AND gate connected to the CLK inputs produces four pulses:
T1, T2, T3, and T4
...
The
fourth pulse changes the shift control to 0, and the shift registers are disabled
...

The serial transfer from A to B occurs in four steps, as shown in Table 6
...
With the first
pulse, T1, the rightmost bit of A is shifted into the leftmost bit of B and is also circulated
into the leftmost position of A
...
The previous serial output from B in the rightmost position is lost,
and its value changes from 0 to 1
...
After the fourth shift, the shift control goes
to 0, and registers A and B both have the value 1011
...
e
...

The difference between the serial and the parallel mode of operation should be apparent from this example
...
In the serial

Section 6
...
1
Serial‐Transfer Example
Timing Pulse
Initial value
After T1
After T2
After T3
After T4

Shift Register A
1
1
1
0
1

0
1
1
1
0

1
0
1
1
1

1
1
0
1
1

Shift Register B
0
1
1
0
1

0
0
1
1
0

1
0
0
1
1

0
1
0
0
1

mode, the registers have a single serial input and a single serial output
...


Serial Addition
Operations in digital computers are usually done in parallel because that is a faster
mode of operation
...
In VLSI circuits, they require less silicon area on a chip
...
The parallel
counterpart was presented in Section 4
...

The two binary numbers to be added serially are stored in two shift registers
...
6
...
The carry out of the full adder is transferred to a D flip‐flop, the output of which is then used as the carry input for the next
pair of significant bits
...
By shifting the sum into A while the bits of A are shifted
out, it is possible to use one register for storing both the augend and the sum bits
...

The operation of the serial adder is as follows: Initially, register A holds the augend,
register B holds the addend, and the carry flip‐flop is cleared to 0
...
Output Q of the flip‐flop
provides the input carry at z
...
The
shift control enables the registers for a number of clock pulses equal to the number of bits
in the registers
...
This process continues until the shift control is disabled
...

Initially, register A and the carry flip‐flop are cleared to 0, and then the first number
is added from B
...
5
Serial adder

to it through its serial input
...
This can be repeated to
perform the addition of two, three, or more four‐bit numbers and accumulate their sum
in register A
...
4, we note
several differences
...
The number of full‐adder circuits in the parallel adder
is equal to the number of bits in the binary numbers, whereas the serial adder requires
only one full‐adder circuit and a carry flip‐flop
...
This design is typical
in serial operations because the result of a bit‐time operation may depend not only on
the present inputs, but also on previous inputs that must be stored in flip‐flops
...
First, we assume that
two shift registers are available to store the binary numbers to be added serially
...
The sequential circuit to
be designed will not include the shift registers, but they will be inserted later to show
the complete circuit
...
The state table that specifies the sequential circuit is listed in
Table 6
...
The present state of Q is the present value of the carry
...
2

Shift Registers

263

Table 6
...
The next
state of Q is equal to the output carry
...

If a D flip‐flop is used for Q, the circuit reduces to the one shown in Fig
...
5
...
12)
...
2
...
6
...
The circuit consists of three gates and a JK
flip‐flop
...
Note that output S is a function not only of x and y, but also of the present state
of Q
...


Universal Shift Register
If the flip‐flop outputs of a shift register are accessible, then information entered serially
by shifting can be taken out in parallel from the outputs of the flip‐flops
...

Some shift registers provide the necessary input and output terminals for parallel
transfer
...
The most general
shift register has the following capabilities:
1
...

2
...


264

Chapter 6

Shift
control
CLK

Serial
input

Registers and Counters

SI
SO
Shift register A

x

SO
SI
Shift register B

y

S

J
C
K

Clear

FIGURE 6
...
A shift‐right control to enable the shift‐right operation and the serial input and
output lines associated with the shift right
...
A shift‐left control to enable the shift‐left operation and the serial input and output
lines associated with the shift left
...
A parallel‐load control to enable a parallel transfer and the n input lines associated with the parallel transfer
...
n parallel output lines
...
A control state that leaves the information in the register unchanged in response
to the clock
...

A register capable of shifting in one direction only is a unidirectional shift register
...
If the register has
both shifts and parallel‐load capabilities, it is referred to as a universal shift register
...
6
...

flip‐flops and four multiplexers
...
Input 0 in each multiplexer is selected when s1s0 = 00, input 1 is selected when
s1s0 = 01, and similarly for the other two inputs
...
3
...
This condition
forms a path from the output of each flip‐flop into the input of the same flip‐flop, so that
the output recirculates to the input in this mode of operation
...


Section 6
...
7
Four‐bit universal shift register

I0

266

Chapter 6

Registers and Counters
Table 6
...
6
...
This causes a shift‐right operation, with the serial input transferred into flip‐flop
A3
...
Finally, when s1s0 = 11, the binary information on the parallel input lines is
transferred into the register simultaneously during the next clock edge
...

Clear_b is an active‐low signal that clears all of the flip‐flops
...
For example, suppose it is necessary to transmit an n‐bit quantity between two
points
...
It is more economical to use a single line and transmit the information serially,
one bit at a time
...
The receiver accepts the
data serially into a shift register
...
Thus, the transmitter performs a parallel‐to‐serial
conversion of data and the receiver does a serial‐to‐parallel conversion
...
3

RIPPLE COUNTERS
A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter
...
The
sequence of states may follow the binary number sequence or any other sequence of
states
...
An
n‐bit binary counter consists of n flip‐flops and can count in binary from 0 through 2n - 1
...

In a ripple counter, a flip‐flop output transition serves as a source for triggering other
flip‐flops
...

In a synchronous counter, the C inputs of all flip‐flops receive the common clock
...
Here, we present the
binary and BCD ripple counters and explain their operation
...
3

Ripple Counters

267

Binary Ripple Counter
A binary ripple counter consists of a series connection of complementing flip‐flops, with
the output of each flip‐flop connected to the C input of the next higher order flip‐flop
...
A complementing flip‐flop can be obtained from a JK flip‐flop with the J and K inputs tied
together or from a T flip‐flop
...
In this way, the D input is always the complement of
the present state, and the next clock pulse will cause the flip‐flop to complement
...
6
...
The counter is constructed with complementing flip‐flops of the T type in part (a) and D type in part (b)
...

The flip‐flop holding the least significant bit receives the incoming count pulses
...
The bubble in front of the dynamic indicator symbol next to C indicates that the flip‐flops respond
to the negative‐edge transition of the input
...

To understand the operation of the four‐bit binary ripple counter, refer to the first
nine binary numbers listed in Table 6
...
The count starts with binary 0 and increments
by 1 with each count pulse input
...
The least significant bit, A0, is complemented with each count pulse
input
...
Every time that A1 goes
from 1 to 0, it complements A2
...
For example, consider the
transition from count 0011 to 0100
...
Since A0
goes from 1 to 0, it triggers A1 and complements it
...
A2 does not trigger A3, because A2
produces a positive transition and the flip‐flop responds only to negative transitions
...
4
Binary Count Sequence
A3

A2

A1

A0

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0

268

Chapter 6

Registers and Counters

A0

T

C

Count

A1

T

C

R

A2

D

C

R

A3

C

A1

C

A2

T

R

D

R

T

C

C

Count

R

A0

D

R

A3

D

C

R

R

Logic 1
Reset

Reset
(a) With T flip-flops

FIGURE 6
...
3

Ripple Counters

269

count goes from 0011 to 0010, then to 0000, and finally to 0100
...

A binary counter with a reverse count is called a binary countdown counter
...

The count of a four‐bit countdown counter starts from binary 15 and continues to binary
counts 14, 13, 12,
...
A list of the count sequence of a binary
countdown counter shows that the least significant bit is complemented with every count
pulse
...
Therefore, the diagram of a binary countdown counter looks the same
as the binary ripple counter in Fig
...
8, provided that all flip‐flops trigger on the positive
edge of the clock
...
) If negative‐edge‐triggered
flip‐flops are used, then the C input of each flip‐flop must be connected to the complemented output of the previous flip‐flop
...


BCD Ripple Counter
A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9
...
The sequence of
states in a decimal counter is dictated by the binary code used to represent a decimal
digit
...
6
...

A decimal counter is similar to a binary counter, except that the state after 1001 (the
code for decimal digit 9) is 0000 (the code for decimal digit 0)
...
6
...

The four outputs are designated by the letter symbol Q, with a numeric subscript equal
to the binary weight of the corresponding bit in the BCD code
...
The J and K inputs are connected either to a permanent 1 signal or to
outputs of other flip‐flops
...
Signals that affect the flip‐flop
transition depend on the way they change from 1 to 0
...
9
State diagram of a decimal BCD counter

270

Chapter 6

Registers and Counters
Q1

J
Count

C
K

Q2

J
C
K

Q4

J
C
K

Q8

J
C
K

Logic 1

FIGURE 6
...
These conditions are derived from the logic diagram and from knowledge of how a
JK flip‐flop operates
...


Section 6
...
11
Block diagram of a three‐decade decimal BCD counter

To verify that these conditions result in the sequence required by a BCD ripple counter, it is necessary to verify that the flip‐flop transitions indeed follow a sequence of
states as specified by the state diagram of Fig
...
9
...
Q2 complements every time Q1 goes from 1 to 0, as long as Q8 = 0
...
Q4 complements every time Q2 goes from 1 to 0
...
When both Q2 and Q4 become 1, Q8 complements when Q1
goes from 1 to 0
...

The BCD counter of Fig
...
10 is a decade counter, since it counts from 0 to 9
...
To count from 0 to 999,
we need a three‐decade counter
...
A three‐decade counter is
shown in Fig
...
11
...
When Q8 in one decade goes from 1 to 0, it triggers the count for the
next higher order decade while its own decade goes from 9 to 0
...
4

SYNCHRONOUS COUNTERS
Synchronous counters are different from ripple counters in that clock pulses are applied
to the inputs of all flip‐flops
...
The decision whether a
flip‐flop is to be complemented is determined from the values of the data inputs, such
as T or J and K at the time of the clock edge
...
If T = 1 or J = K = 1, the flip‐flop complements
...
8, and the
design of a three‐bit binary counter was carried out in conjunction with Fig
...
31
...


Binary Counter
The design of a synchronous binary counter is so simple that there is no need to go
through a sequential logic design process
...
A flip‐flop in any other

272

Chapter 6

Registers and Counters

position is complemented when all the bits in the lower significant positions are equal to 1
...
A0 is always complemented
...
A2 is complemented because the present state of A1A0 = 11
...

Synchronous binary counters have a regular pattern and can be constructed with
complementing flip‐flops and gates
...
6
...
The C inputs of all flip‐flops are connected to a common
clock
...
If the enable input is 0, all J and K inputs
are equal to 0 and the clock does not change the state of the counter
...
The other J and K inputs are
equal to 1 if all previous least significant stages are equal to 1 and the count is enabled
...
The counter can be extended to any number of stages, with each stage having an
additional flip‐flop and an AND gate that gives an output of 1 if all previous flip‐flop
outputs are 1
...
The polarity of the
clock is not essential here, but it is with the ripple counter
...
The complementing
flip‐flops in a binary counter can be of either the JK type, the T type, or the D type with
XOR gates
...
5
...


Up–Down Binary Counter
A synchronous countdown binary counter goes through the binary states in reverse order,
from 1111 down to 0000 and back to 1111 to repeat the count
...
The bit in the least significant position is complemented with each
pulse
...

For example, the next state after the present state of 0100 is 0011
...
The second significant bit is complemented because the first
bit is 0
...

But the fourth bit does not change, because not all lower significant bits are equal to 0
...
6
...
The two operations can be combined in
one circuit to form a counter capable of counting either up or down
...
6
...
It has an up control
input and a down control input
...
When the down input is 1 and the up input is 0, the circuit counts down,
since the complemented outputs of the previous flip‐flops are applied to the T inputs
...
4

Synchronous Counters
A0

J
C
Count_enable

K

A1

J
C
K

A2

J
C
K

A3

J
C
K

To next stage

CLK

FIGURE 6
...
13
Four‐bit up–down binary counter

Section 6
...
When the up and down inputs are both 1, the circuit counts up
...
Note
that the up input has priority over the down input
...

Because of the return to 0 after a count of 9, a BCD counter does not have a regular
pattern, unlike a straight binary count
...

The state table of a BCD counter is listed in Table 6
...
The input conditions for the
T flip‐flops are obtained from the present‐ and next‐state conditions
...
In this way, y can
enable the count of the next‐higher significant decade while the same pulse switches the
present decade from 1001 to 0000
...
The unused states
for minterms 10 to 15 are taken as don’t‐care terms
...
Synchronous BCD counters can be cascaded to form a counter for decimal numbers
of any length
...
6
...

Table 6
...

Figure 6
...
When equal to
1, the input load control disables the count operation and causes a transfer of data from
the four data inputs into the four flip‐flops
...

The carry output becomes a 1 if all the flip‐flops are equal to 1 while the count input is
enabled
...
The carry output is useful for expanding the counter to more than four bits
...
In going from state 1111
to 0000, only one gate delay occurs, whereas four gate delays occur in the AND gate chain
shown in Fig
...
12
...

The operation of the counter is summarized in Table 6
...
The four control inputs—
Clear, CLK, Load, and Count—determine the next state
...
This relationship is indicated in the table by the X entries,
which symbolize don’t‐care conditions for the other inputs
...
With the Load and Count inputs both at 0, the outputs do not change, even when clock pulses are applied
...
The input
data are loaded into the register regardless of the value of the Count input, because the
Count input is inhibited when the Load input is enabled
...

A counter with a parallel load can be used to generate any desired count sequence
...
15 shows two ways in which a counter with a parallel load is used to generate
the BCD count
...
Also, recall that the Load control inhibits the count and that the clear
operation is independent of other control inputs
...
6
...
The counter is
initially cleared to 0, and then the Clear and Count inputs are set to 1, so the counter is
active at all times
...
6
Function Table for the Counter of Fig
...
14
Clear

CLK

Load

Count

0
1

X

X
1

X
X

Clear to 0
Load inputs

0

1

Count next binary state

0

0

No change

1
1

c
c
c

Function

Section 6
...
14
Four‐bit binary counter with parallel load

278

Chapter 6

Registers and Counters
A3 A2 A1 A0

A3 A2 A1 A0

Count ϭ 1

Load
Counter
of Fig
...
14

Clear ϭ 1

Count ϭ 1

Clear
Counter
of Fig
...
14

CLK
Inputs ϭ 0
(a) Using the load input

Load ϭ 0
CLK

Inputs have no effect
(b) Using the clear input

FIGURE 6
...
When the output reaches the count of 1001, both A0 and
A3 become 1, making the output of the AND gate equal to 1
...
Since all four inputs are connected to logic 0, an all‐0’s value
is loaded into the register following the count of 1001
...

In Fig
...
15(b), the NAND gate detects the count of 1010, but as soon as this count
occurs, the register is cleared
...
A momentary spike occurs in
output A0 as the count goes from 1010 to 1011 and immediately to 0000
...
If the counter has a synchronous clear input, it is possible to clear the counter with the clock after
an occurrence of the 1001 count
...
5

OTHER COUNTERS
Counters can be designed to generate any desired sequence of states
...
The sequence may follow the binary count or may be any other
arbitrary sequence
...
Counters can also be constructed by means of shift
registers
...


Counter with Unused States
A circuit with n flip‐flops has 2n binary states
...
States that are not used

Section 6
...
In simplifying the
input equations, the unused states may be treated as don’t‐care conditions or may be
assigned specific next states
...
In that case, it is necessary to ensure that the circuit eventually
goes into one of the valid states so that it can resume normal operation
...
If the unused states are treated as don’t‐care
conditions, then once the circuit is designed, it must be investigated to determine the
effect of the unused states
...

As an illustration, consider the counter specified in Table 6
...
The count has a
repeated sequence of six states, with flip‐flops B and C repeating the binary count 00,
01, 10, and flip‐flop A alternating between 0 and 1 every three counts
...
The choice of JK flip‐flops results in the flip‐flop input conditions
listed in the table
...
The other flip‐flop input equations can be simplified by
using minterms 3 and 7 as don’t‐care conditions
...
6
...
Since there are two unused
states, we analyze the circuit to determine their effect
...
This action may be determined from an inspection of the logic diagram by
noting that when B = 1, the next clock edge complements A and clears C to 0, and when
C = 1, the next clock edge complements B
...


Table 6
...
16
Counter with unused states

The state diagram including the effect of the unused states is shown in Fig
...
16(b)
...
Thus, the counter is self‐correcting
...
An alternative design could use additional logic
to direct every unused state to a specific next state
...
A ring counter is a circular shift
register with only one flip‐flop being set at any particular time; all others are cleared
...
Figure 6
...
The
initial value of the register is 1000 and requires Preset/Clear flip‐flops
...
5

Shift
right

T0

T1

T2

Other Counters

281

T3

(a) Ring-counter (initial value ϭ 1000)

CLK

T0

T1

T2
T3

(b) Sequence of four timing signals

T0 T1 T2 T3

2ϫ4
decoder

Count
enable

2-bit counter
(c) Counter and decoder

FIGURE 6
...
Each flip‐flop is
in the 1 state once every four clock cycles and produces one of the four timing signals
shown in Fig
...
17(b)
...


282

Chapter 6

Registers and Counters

For an alternative design, the timing signals can be generated by a two‐bit counter
that goes through four distinct states
...
6
...

To generate 2n timing signals, we need either a shift register with 2n flip‐flops or an
n‐bit binary counter together with an n‐to‐2n‐line decoder
...
In the first case, we need 16 flip‐flops
...
It is
also possible to generate the timing signals with a combination of a shift register and a
decoder
...
This combination is called a Johnson counter
...
The number of states can be doubled if the shift register is connected as a
switch‐tail ring counter
...

Figure 6
...
The circular connection is made from the

A

D

B

D

C

C

D

C

C

AЈ

BЈ

E

D
C
CЈ

CLK
(a) Four-stage switch-tail ring counter

Flip-flop outputs

Sequence
number

A

B

C

E

AND gate required
for output

1
2
3
4
5
6
7
8

0
1
1
1
1
0
0
0

0
0
1
1
1
1
0
0

0
0
0
1
1
1
1
0

0
0
0
0
1
1
1
1

AЈEЈ
ABЈ
BCЈ
CEЈ
AE
AЈB
BЈC
CЈE

(b) Count sequence and required decoding

FIGURE 6
...
6

HDL for Registers and Counters

283

complemented output of the rightmost flip‐flop to the input of the leftmost flip‐flop
...

Starting from a cleared state, the switch‐tail ring counter goes through a sequence of
eight states, as listed in Fig
...
18(b)
...
Starting from all 0’s, each shift operation inserts 1’s from
the left until the register is filled with all 1’s
...

A Johnson counter is a k‐bit switch‐tail ring counter with 2k decoding gates to provide outputs for 2k timing signals
...
6
...
The eight AND gates listed in the table, when
connected to the circuit, will complete the construction of the Johnson counter
...

The decoding of a k‐bit switch‐tail ring counter to obtain 2k timing signals follows a
regular pattern
...
The all‐1’s state is decoded by taking the normal outputs of the two extreme
flip‐flops
...

For example, sequence 7 has an adjacent 0, 1 pattern in flip‐flops B and C
...

One disadvantage of the circuit in Fig
...
18(a) is that if it finds itself in an unused state,
it will persist in moving from one invalid state to another and never find its way to a valid
state
...
One correcting procedure is to disconnect the output from flip‐flop B that goes
to the D input of flip‐flop C and instead enable the input of flip‐flop C by the function
DC = (A + C)B
where DC is the flip‐flop input equation for the D input of flip‐flop C
...
The number of flip‐flops needed is one‐half the number of timing signals
...


6
...
Behavioral modeling describes only the operations of the register, as prescribed by a function table, without a preconceived structure
...
The various components are instantiated to form a hierarchical
description of the design similar to a representation of a multilevel logic diagram
...
Both are useful
...


284

Chapter 6

Registers and Counters

Shift Register
The universal shift register presented in Section 6
...
The four clocked operations that are performed with the register are specified in Table 6
...
The register also can be cleared asynchronously
...
6
...
The behavioral
model is presented in HDL Example 6
...
2
...
6
...
The elements of vector
I_par[3: 0] correspond to the bits I3,
...
6
...

The always block describes the five operations that can be performed with the register
...
Clear
must be high for the register to respond to the positive edge of the clock
...
(s1 and s0 are concatenated into a two‐bit vector and are used
as the expression argument of the case statement
...
For example, the statement
A_par <= {MSB_in, A_par [3: 1]}

specifies a concatenation of the serial data input for a right shift operation (MSB_in)
with bits A_par[3: 1] of the output data bus
...
The four‐bit result of the concatenation is
transferred to register A_par [3: 0] when the clock pulse triggers the operation
...

The shift operation overwrites the contents of A_par[0] with the contents of A_par[1]
...
A synthesis tool would create a netlist of ASIC cells to implement
the shift register in the structure of Fig
...
7(b)
...
1 (Universal Shift Register‐Behavioral Model)
// Behavioral description of a 4-bit universal shift register
// Fig
...
7 and Table 6
...
6

HDL for Registers and Counters

always @ (posedge CLK, negedge Clear_b)
if (Clear_b == 0) A_par <= 4’b0000;
else
case ({s1, s0})
2'b00: A_par <= A_par;
2'b01: A_par <= {MSB_in, A_par[3: 1]};
2'b10: A_par <= {A_par[2: 0], LSB_in};
2'b11: A_par <= I_par;
endcase
endmodule

285

// V2001, 2005

// No change
// Shift right
// Shift left
// Parallel load of input

Variables of type reg retain their value until they are assigned a new value by an
assignment statement
...


A structural model of the universal shift register can be described by referring to the
logic diagram of Fig
...
7(b)
...
A mux and flip‐flop together are modeled as a stage of the shift register
...
For simplicity, the lowest‐level modules of the
structure are behavioral models of the multiplexer and flip‐flop
...
The structural description of the register
is shown in HDL Example 6
...
The top‐level module declares the inputs and outputs and
then instantiates four copies of a stage of the register
...
The behavioral description of the flip‐flop uses
a single edge‐sensitive cyclic behavior (an always block)
...

HDL Example 6
...
6
...
6

HDL for Registers and Counters

287

// Behavioral model of D flip-flop
module D_flip_flop (Q, D, CLK, Clr_b);
output
Q;
input
D, CLK, Clr;
reg
Q;
always @ (posedge CLK, negedge Clr_b)
if (!Clr_b) Q <= 1'b0; else Q <= D;
endmodule

The above examples presented two descriptions of a universal shift register to illustrate the different styles for modeling a digital circuit
...
In practice, a designer develops only the behavioral model, which is then synthesized
...
Eliminating the
need for the designer to develop a structural model produces a huge improvement in
the efficiency of the design process
...
3 presents Binary_Counter_4_Par_Load, a behavioral model of the
synchronous counter with a parallel load from Fig
...
14
...
6
...

The internal data lines (I3, I2, I1, I0) are bundled as Data_in[3: 0] in the behavioral
model
...
It is good practice to have identifiers in the HDL model of a circuit correspond exactly to those in the documentation of the model
...
The top‐level
block diagram symbol in Fig
...
14(a) serves as an interface between the names used in
a circuit diagram and the expressive names that can be used in the HDL model
...
C_out = 1when the count reaches 15 and the counter is in the count state
...
The
always block specifies the operation to be performed in the register, depending on the
values of Clear_b, Load, and Count
...

Otherwise, if Clear_b = 1, one out of three operations is triggered by the positive edge
of the clock
...
6
...
A synthesis tool will produce the
circuit of Fig
...
14(b) from the behavioral model
...
3 (Synchronous Counter)
// Four-bit binary counter with parallel load (V2001, 2005)
// See Figure 6
...
6
module Binary_Counter_4_Par_Load (
output reg [3: 0]
A_count,
// Data output
output
C_out,
// Output carry
input [3: 0]
Data_in,
// Data input
input
Count,
// Active high to count
Load,
// Active high to load
CLK,
// Positive-edge sensitive
Clear_b
// Active low
);
assign C_out = Count && (~Load) && (A_count == 4'b1111);
always @ (posedge CLK, negedge Clear_b)
if (~Clear_b)
A_count <= 4'b0000;
else if (Load)
A_count <= Data_in;
else if (Count)
A_count <= A_count + 1'b1;
else
A_count <= A_count; // redundant statement
endmodule

Ripple Counter
The structural description of a ripple counter is shown in HDL Example 6
...
The first
module instantiates four internally complementing flip‐flops defined in the second module as Comp_D_flip_flop (Q, CLK, Reset)
...
(Count replaces CLK in the port list
of instance F0
...
(A0 replaces CLK in instance F1
...
In this way, the flip‐flops are chained
together to create a ripple counter as shown in Fig
...
8(b)
...
The circuit of a
complementing flip‐flop is constructed by connecting the complement output to the D
input
...
The flip‐flop is assigned a delay of two time
units from the time that the clock is applied to the time that the flip‐flop complements
its output
...
Notice that the delay
operator is placed to the right of the nonblocking assignment operator
...
The effect of modeling the delay will be apparent in
the simulation results
...
The results of synthesis depend on the
ASIC cell library that is accessed by the tool, not on any propagation delays that might
appear within the model that is to be synthesized
...
6

HDL for Registers and Counters

HDL Example 6
...
6
...
4 provides a stimulus for simulating and
verifying the functionality of the ripple counter
...
The flip‐flops trigger on the negative edge of
the clock, which occurs at t = 10, 20, 30, and every 10 time units thereafter
...
6
...
The control signal Count goes negative
every 10 ns
...

Each flip‐flop is complemented when its previous flip‐flop goes from 1 to 0
...
Each output is
delayed by 2 ns, and because of that, A3 goes from 0 to 1 at t = 88 ns and from 1 to 0 at
168 ns
...
This limits the practical utility of the counter
...
0 ns

57
...
0 ns

171
...
0 ns

77
...
0 ns

Reset
Count

A0
A1
A2
A3
(b) From 70 to 98 ns

FIGURE 6
...
4

t ϭ 168 ns

91
...
0 ns

Problems

291

PROBLEMS
(Answers to problems marked with * appear at the end of the book
...
)
Note: For each problem that requires writing and verifying a Verilog description, a test plan is to
be written to identify which functional features are to be tested during the simulation and how
they will be tested
...
The test plan is to guide the
development of a test bench that will implement the plan
...
If synthesis tools and an ASIC cell library or a field programmable gate array (FPGA) tool suite are available, the Verilog descriptions developed for
Problems 6
...
51 can be assigned as synthesis exercises
...

In some of the HDL problems, there may be a need to deal with the issue of unused states (see
the discussion of the default case item preceding HDL Example 4
...

6
...
6
...
One input of the NAND gate receives the clock pulses from
the clock generator, and the other input of the NAND gate provides a parallel load control
...
Explain why this circuit might have operational problems
...
2

Include a synchronous clear input to the register of Fig
...
2
...
The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal
to 1
...
35(a), (b)
...
3

What is the difference between serial and parallel transfer? Explain how to convert serial
data to parallel and parallel data to serial
...
4* The contents of a four‐bit register is initially 0110
...
What is the content of the register after each
shift?
6
...
6
...
(HDL—see Problem 6
...
)
(a) Draw a block diagram of the IC showing all inputs and outputs
...

(b) Draw a block diagram using two of these ICs to produce an eight‐bit universal shift
register
...
6

Design a four‐bit shift register with parallel load using D flip‐flops
...
When shift = 1, the content of the register is shifted by one position
...
If both
control inputs are equal to 0, the content of the register does not change
...
35(c), (d)
...
7

Draw the logic diagram of a four‐bit register with four D flip‐flops and four 4 × 1 multiplexers with mode selection inputs s1 and s0
...
(HDL—see Problem 6
...
)

292

Chapter 6

Registers and Counters
s1

s0

Register Operation

0
1
0
1

0
0
1
1

No change
Complement the four outputs
Clear register to 0 (synchronous with the clock)
Load parallel data

6
...
6
...
Register A holds the binary number
0101 and register B holds 0111
...
List the binary
values in register A and the carry flip‐flop after each shift
...
54)
...
9

Two ways for implementing a serial adder (A + B) is shown in Section 6
...
It is necessary
to modify the circuits to convert them to serial subtractors (A - B)
...
6
...
(HDL—see Problem 6
...
)
(b) *Using the circuit of Fig
...
6, show the changes needed by modifying Table 6
...
(See Problem 4
...
(HDL—see Problem 6
...
)

6
...
The binary number
is shifted out from one side and it’s 2’s complement shifted into the other side of the shift
register
...
35(j)
...
11 A binary ripple counter uses flip‐flops that trigger on the positive‐edge of the clock
...
12 Draw the logic diagram of a four‐bit binary ripple countdown counter using
(a) flip‐flops that trigger on the positive‐edge of the clock and
(b) flip‐flops that trigger on the negative‐edge of the clock
...
13 Show that a BCD ripple counter can be constructed using a four‐bit binary ripple counter
with asynchronous clear and a NAND gate that detects the occurrence of count 1010
...
35(k)
...
14 How many flip‐flop will be complemented in a 10‐bit binary ripple counter to reach the
next count after the following counts?
(a) *1001100111
(b) 1111000111
(c) 0000001111
6
...
What is the maximum delay in a 10‐bit binary ripple counter that uses
these flip‐flops? What is the maximum frequency at which the counter can operate
reliably?
6
...
6
...
Analyze the circuit and determine the next state for each of the other six
unused states
...
54
...
17* Design a four‐bit binary synchronous counter with D flip‐flops
...
18 What operation is performed in the up–down counter of Fig
...
13 when both the up and
down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the
counter does not change state
...
35(l)
...
19 The flip‐flop input equations for a BCD counter using T flip‐flops are given in Section 6
...

Obtain the input equations for a BCD counter that uses (a) JK flip‐flops and (b)* D flip‐
flops
...

6
...
6
...

(a) Show the connections of four such blocks to produce a 16‐bit counter with parallel
load
...

6
...
6
...

(a) Derive the flip‐flop input equations for J and K of the first stage in terms of L, C,
and I
...
P6
...

Verify that this circuit is equivalent to the one in (a)
...
21
6
...
6
...
e
...

(a) Using an AND gate and the load input
...

(c) Using a NAND gate and the asynchronous clear input
...
23 Design a timing circuit that provides an output signal that stays on for exactly twelve clock
cycles
...
(HDL—see Problem 6
...
)
6
...
Show that when binary states 010 and 101 are considered as don’t
,
care conditions, the counter may not operate properly
...

(HDL—see Problem 6
...
)
6
...
6
...
Design the circuit using (HDL—see Problem 6
...
):
(a) flip‐flops only
...


294

Chapter 6

Registers and Counters

6
...

Design a circuit that provides a clock with a cycle time of 50 ns
...
27 Using JK flip‐flops,
(a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6
...
50(a), 6
...

(b) Draw the logic diagram of the counter
...
28 Using D flip‐flops,
(a) *Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6
...
50(b)
...

(c) Design a counter with the following repeated binary sequence: 0, 2, 4, 6, 8
...

6
...
6
...
Determine the
next state for each of these states and show that, if the counter finds itself in an invalid
state, it does not return to a valid state
...

6
...
List the
10 states produced with five flip‐flops and the Boolean terms of each of the 10 AND gate
outputs
...
31 Write and verify the HDL behavioral and structural descriptions of the four‐bit register
Fig
...
1
...
32 (a) Write and verify an HDL behavioral description of a four‐bit register with parallel
load and asynchronous clear
...
6
...
Use a 2 * 1 multiplexer for the flip‐flop inputs
...

(c) Verify both descriptions, using a test bench
...
33 The following stimulus program is used to simulate the binary counter with parallel load
described in HDL Example 6
...
Draw waveforms showing the output of the counter and
the carry output from t = 0 to t = 155 ns
...
3
module testcounter;
reg Count, Load, CLK, Clr;
reg [3: 0] IN;
wire C0;
wire [3: 0] A;
counter cnt (Count, Load, IN, CLK, Clr, A, CO);
always
#5 CLK = ~CLK;
initial
begin
Clr = 0;
CLK = 1;
Load = 0; Count = 1;

Problems

295

#5 Clr = 1;
#40 Load = 1; IN = 4'b1001;
#10 Load = 0;
#70 Count = 0;
#20 $finish;
end
endmodule

6
...
6
...

6
...
2
(b) *A behavioral HDL model for the register described in Problem 6
...
6
(d) A behavioral HDL model for the register described in Problem 6
...
7
(f) A behavioral HDL model for the register described in Problem 6
...
6
...
9(a)
(i) A behavioral HDL model of the serial subtractor described in Problem 6
...
10
(k) A behavioral HDL model of the BCD ripple counter described in Problem 6
...
18
...
36 Write and verify the HDL behavioral and structural descriptions of the four‐bit up–down
counter whose logic diagram is described by Fig
...
13, Table 6
...
6
...
37 Write and verify a behavioral description of the counter described in Problem 6
...

(a) *Using an if … else statement
(b) Using a case statement
(c) A finite state machine
...
38 Write and verify the HDL behavioral description of a four‐bit up–down counter with
parallel load using the following control inputs:
(a) *The counter has three control inputs for the three operations: Up, Down, and Load
...

(b) The counter has two selection inputs to specify four operations: Load, Up, Down, and
no change
...
39 Write and verify HDL behavioral and structural descriptions of the counter of Fig
...
16
...
40 Write and verify the HDL description of an eight‐bit ring‐counter similar to the one shown
in Fig
...
17(a)
...
41 Write and verify the HDL description of a four‐bit switch‐tail ring (Johnson) counter
(Fig
...
18a)
...
42* The comment with the last clause of the if statement in Binary_Counter_4_Par_Load in
HDL Example 6
...
Explain why this statement can
be removed without changing the behavior implemented by the description
...
43 The scheme shown in Fig
...
4 gates the clock to control the serial transfer of data from shift
register A to shift register B
...
The

296

Chapter 6

Registers and Counters

top level of the design hierarchy is to instantiate the shift registers
...
Describe the mux and
flip‐flop modules with behavioral models
...

Develop a test bench to simulate the circuit and demonstrate the transfer of data
...
44 Modify the design of the serial adder shown in Fig
...
5 by removing the gated clock to the D
flip‐flop and supplying the clock signal to it directly
...
The shift registers are to incorporate this feature also,
rather than use a gated clock
...
Assume asynchronous reset
...

6
...
24
...
46 Problem 6
...

(b) A counter and a decoder
...

6
...
P6
...


D_in

CLK

D

Q

P_odd

CLK

reset

FIGURE P6
...
47
6
...
P6
...
P6
...

6
...
1
...
1
...
50 Write and verify a behavioral model of the counter described in
(a) Problem 6
...
28
6
...
5
...

the implementations
...
52 Write a Verilog structural model of the universal shift register in Fig
...
7 Verify all modes

...


Problems
count [7: 0]

297

count [7: 0]

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

t

t
0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

(a)

(b)

FIGURE P6
...
48
6
...
6
...

6
...
6
...

6
...
6
...

6
...
6
...

6
...
6
...

6
...
6
...
6
...

6
...
6
...
6
...

2
...

4
...

6
...

8
...

10
...

12
...

14
...


Mano, M
...
and C
...
Kime
...
Upper

...

Nelson V
...
, H
...
Nagle, J
...
Irwin, and B
...
Carroll
...
Digital Logic Circuit
Analysis and Design
...

Hayes, J
...
1993
...
Reading, MA: Addison‐Wesley
...
F
...
Digital Design: Principles and Practices, 3rd ed
...

Dietmeyer, D
...
1988
...
Boston: Allyn Bacon
...
D
...
Upper Saddle River, NJ: Prentice Hall
...

Roth, C
...
2009
...
St
...

Katz, R
...
1994
...
Upper Saddle River, NJ: Prentice Hall
...
D
...
Modeling, Synthesis, and Rapid Prototyping with Verilog HDL
...

Bhasker, J
...
Allentown, PA: Star Galaxy Press
...

Thomas, D
...
and P
...
Moorby
...
The VeriLog Hardware Description Language, 5th
ed
...

Bhasker, J
...
Verilog HDL Synthesis
...

Palnitkar, S
...
Verilog HDL: A Guide to Digital Design and Synthesis
...

Ciletti, M
...
2010
...
Upper Saddle
River, NJ: Prentice Hall
...
D
...
Starter’s Guide to Verilog 2001
...


WEB SEARCH TOPICS
BCD counter
Johnson counter
Ring counter
Sequence detector
Synchronous counter
Switch‐tail ring counter
Up–down counter

Chapter 7

Memory and Programmable Logic

7
...
When data processing takes
place, information from memory is transferred to selected registers in the processing unit
...
Binary information received from an input device is stored in memory,
and information transferred to an output device is taken from memory
...

There are two types of memories that are used in digital systems: random‐access
memory (RAM) and read‐only memory (ROM)
...
The process of storing new information into memory is referred to as a memory
write operation
...
RAM can perform both write and read operations
...
This means that suitable binary information is already stored inside memory and can be retrieved or read at any time
...

ROM is a programmable logic device (PLD)
...
The word “programming”
here refers to a hardware procedure which specifies the bits that are inserted into the
hardware configuration of the device
...
Other such units are the programmable logic array
(PLA), programmable array logic (PAL), and the field‐programmable gate array (FPGA)
...
1
Conventional and array logic diagrams for OR gate

paths that behave similarly to fuses
...
Programming the device involves blowing those fuses along the paths that must
be removed in order to obtain the particular configuration of the desired logic function
...
We also present CMOS FPGAs, which are configured
by downloading a stream of bits into the device to configure transmission gates to establish the internal connectivity required by a specified logic function (combinational or
sequential)
...
In order to show the internal logic diagram of such
a device in a concise form, it is necessary to employ a special gate symbology applicable
to array logic
...
1
input OR gate
...
The input lines are drawn perpendicular to this single line and are
connected to the gate through internal fuses
...
This type of graphical representation for the inputs of gates will
be used throughout the chapter in array logic diagrams
...
2

RANDOM-ACCESS MEMORY
A memory unit is a collection of storage cells, together with associated circuits needed
to transfer information into and out of a device
...
The time it
takes to transfer information to or from any desired random location is always the
same—hence the name random‐access memory, abbreviated RAM
...

A memory unit stores binary information in groups of bits called words
...
A memory word
is a group of 1’s and 0’s and may represent a number, an instruction, one or more
alphanumeric characters, or any other binary‐coded information
...
Most computer memories use words that are multiples of 8 bits in length
...
The
capacity of a memory unit is usually stated as the total number of bytes that the unit
can store
...
2

Random-Access Memory

301

n data input lines

k address lines
Read
Write

Memory unit
2k words
n bit per word

n data output lines

FIGURE 7
...
A block diagram of a memory unit is shown in Fig
...
2
...
The k address lines specify the particular word
chosen among the many available
...

The memory unit is specified by the number of words it contains and the number of
bits in each word
...
Each word in memory
is assigned an identification number, called an address, starting from 0 up to 2k - 1,
where k is the number of address lines
...
An internal decoder accepts
this address and opens the paths needed to select the word specified
...
It is customary to refer to the number of words (or
bytes) in memory with one of the letters K (kilo), M (mega), and G (giga)
...
Thus, 64K = 216, 2M = 221, and 4G = 232
...

Since 1K = 1,024 = 210 and 16 bits constitute two bytes, we can say that the memory
can accommodate 2,048 = 2K bytes
...
3 shows possible contents of the first
three and the last three words of this memory
...
The words are recognized by their decimal address from 0 to
1,023
...
The first address is specified with
ten 0’s; the last address is specified with ten 1’s, because 1,023 in binary is equal to
1111111111
...
When a word is read or
written, the memory operates on all 16 bits as a single unit
...
7
...

As another example, a 64K * 10 memory will have 16 bits in the address (since
64K = 216) and each word will consist of 10 bits
...
3
Contents of a 1024 * 16 memory

a memory is dependent on the total number of words that can be stored in the memory
and is independent of the number of bits in each word
...


Write and Read Operations
The two operations that RAM can perform are the write and read operations
...
On accepting one of these control signals, the internal circuits
inside the memory provide the desired operation
...
Apply the binary address of the desired word to the address lines
...
Apply the data bits that must be stored in memory to the data input lines
...
Activate the write input
...

The steps that must be taken for the purpose of transferring a stored word out of
memory are as follows:
1
...

2
...


Section 7
...
1
Control Inputs to Memory Chip
Memory Enable

Read/Write

Memory Operation

0

X

None

1

0

Write to selected word

1

1

Read from selected word

The memory unit will then take the bits from the word that has been selected by the
address and apply them to the output data lines
...
e
...

Commercial memory components available in integrated‐circuit chips sometimes
provide the two control inputs for reading and writing in a somewhat different configuration
...
The memory operations that result from these
control inputs are specified in Table 7
...

The memory enable (sometimes called the chip select) is used to enable the particular memory chip in a multichip implementation of a large memory
...
When
the memory enable input is active, the read/write input determines the operation to be
performed
...
It is declared with a reg keyword, using a two‐dimensional array
...
For example, a memory
of 1,024 words with 16 bits per word is declared as
reg[15: 0] memword [0: 1023];

This statement describes a two‐dimensional array of 1,024 registers, each containing 16
bits
...
For example,
memword[512] refers to the 16‐bit memory word at address 512
...
1
...
There are two control inputs: Enable and ReadWrite
...
The input Address must have six bits
(since 26 = 64)
...
A memory operation requires that the Enable input be active
...
If ReadWrite is 1, the memory performs a read
operation symbolized by the statement

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Memory and Programmable Logic
DataOut d Mem [Address];

Execution of this statement causes a transfer of four bits from the selected memory word
specified by Address onto the DataOut lines
...
When Enable is equal to 0, the memory is disabled
and the outputs are assumed to be in a high‐impedance state, indicated by the symbol z
...

HDL Example 7
...

module memory (Enable, ReadWrite, Address, DataIn, DataOut);
input Enable, ReadWrite;
input [3: 0] DataIn;
input [5: 0] Address;
output [3: 0] DataOut;
reg [3: 0]
DataOut;
reg [3: 0]
Mem [0: 63];
// 64 x 4 memory
always @ (Enable or ReadWrite)
if (Enable)
if (ReadWrite) DataOut = Mem [Address];
// Read
else Mem [Address] = DataIn;
// Write
else DataOut = 4'bz;
// High impedance state
endmodule

Timing Waveforms
The operation of the memory unit is controlled by an external device such as a central
processing unit (CPU)
...
The memory,
however, does not employ an internal clock
...
The access time of memory is the time required to select a
word and read it
...
The CPU must provide the memory control signals in such a way as to synchronize its internal clocked operations with the read and write operations of memory
...

Suppose as an example that a CPU operates with a clock frequency of 50 MHz, giving a period of 20 ns for one clock cycle
...
This means that the

Section 7
...
4
Memory cycle timing waveforms

write cycle terminates the storage of the selected word within a 50‐ns interval and that
the read cycle provides the output data of the selected word within 50 ns or less
...
) Since the period of the CPU cycle is 20 ns, it will
be necessary to devote at least two‐and‐a‐half, and possibly three, clock cycles for each
memory request
...
7
...
The write cycle in part (a) shows three 20‐ns cycles: T 1,

306

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Memory and Programmable Logic

T 2, and T 3
...
This is done at the beginning of T 1
...
) The memory enable and the read/write signals must be activated after the signals
in the address lines are stable in order to avoid destroying data in other memory words
...
The two control signals must stay active
for at least 50 ns
...
At the completion of the third clock cycle, the memory write operation is completed and the CPU can access the memory again with the
next T 1 cycle
...
7
...
The memory‐enable and read/write signals must be in their high level for a read
operation
...
The CPU can transfer the data into one of its internal registers during the
negative transition of T 3
...


Types of Memories
The mode of access of a memory system is determined by the type of components used
...
In a sequential‐access memory,
the information stored in some medium is not immediately accessible, but is available
only at certain intervals of time
...
Each
memory location passes the read and write heads in turn, but information is read out
only when the requested word has been reached
...
In a sequential‐
access memory, the time it takes to access a word depends on the position of the word
with respect to the position of the read head; therefore, the access time is variable
...
Static RAM (SRAM) consists essentially of internal latches that store the
binary information
...
Dynamic RAM (DRAM) stores the binary information in the form of electric
charges on capacitors provided inside the chip by MOS transistors
...
Refreshing is done by cycling through the
words every few milliseconds to restore the decaying charge
...
SRAM is
easier to use and has shorter read and write cycles
...
CMOS integrated circuit RAMs, both static and dynamic, are of this category, since
the binary cells need external power to maintain the stored information
...
3

Memory Decoding

307

of power
...
ROM is another nonvolatile memory
...
Programs and data that cannot be altered are stored in ROM, while other
large programs are maintained on magnetic disks
...
Before the power is turned off, the binary information from
the computer RAM is transferred to the disk so that the information will be retained
...
3

MEMORY DECODING
In addition to requiring storage components in a memory unit, there is a need for decoding circuits to select the memory word specified by the input address
...
To be able to include the entire memory in one diagram, the memory unit
presented here has a small capacity of 16 bits, arranged in four words of 4 bits each
...
We then give an example
of address multiplexing commonly used in DRAM integrated circuits
...
The
binary storage cell is the basic building block of a memory unit
...
7
...
The storage part of
the cell is modeled by an SR latch with associated gates to form a D latch
...
5
Memory cell

(b) Block diagram

308

Chapter 7

Memory and Programmable Logic

cell is an electronic circuit with four to six transistors
...
A binary storage cell must be very small
in order to be able to pack as many cells as possible in the small area available in the
integrated circuit chip
...
The select input
enables the cell for reading or writing, and the read/write input determines the operation
of the cell when it is selected
...
A 0 in the read/write input provides
the write operation by forming a path from the input terminal to the latch
...
7
...
This RAM consists of
four words of four bits each and has a total of 16 binary cells
...
 7
...
A memory with four words needs two address lines
...
The decoder is enabled with

Input data
Word 0
BC

BC

BC

BC

BC

BC

BC

BC

BC

BC

BC

BC

Address
inputs

BC

BC

BC

BC

Word 1
2ϫ4
decoder

Word 2

Memory
enable

EN
Word 3

Read/Write

Output data

FIGURE 7
...
3

Memory Decoding

309

the memory‐enable input
...
With the memory select at 1, one of the
four words is selected, dictated by the value in the two address lines
...
During the read operation, the four bits of the selected word go through OR gates to the output terminals
...
7
...
)
During the write operation, the data available in the input lines are transferred into the
four binary cells of the selected word
...
When the memory select input that
goes into the decoder is equal to 0, none of the words are selected and the contents of
all cells remain unchanged regardless of the value of the read/write input
...
The logical construction of a large‐capacity memory would be a
direct extension of the configuration shown here
...
Each one of the decoder
outputs selects one word of n bits for reading or writing
...

The total number of gates and the number of inputs per gate can be reduced by
employing two decoders in a two‐dimensional selection scheme
...
In this configuration, two k/2‐input decoders are used instead of
one k‐input decoder
...

The two‐dimensional selection pattern is demonstrated in Fig
...
7 for a 1K‐word
memory
...

With the single decoder, we would need 1,024 AND gates with 10 inputs in each
...
The five most significant
bits of the address go to input X and the five least significant bits go to input Y
...
Thus, each word in memory is selected by the coincidence between 1 of 32 rows and
1 of 32 columns, for a total of 1,024 words
...

As an example, consider the word whose address is 404
...
This makes X = 01100 (binary 12) and Y = 10100 (binary 20)
...
All the bits of the word are selected for reading or writing
...
7
...
In order to
build memories with higher density, it is necessary to reduce the number of transistors in
a cell
...
The charge stored

310

Chapter 7

Memory and Programmable Logic
Y

5 ϫ 32 decoder

0

1

2
...



...
31

0
1

X

5 ϫ 32
decoder

2

...


...


...

31

binary address
01100 10100
X

Y

FIGURE 7
...
Because of their simple cell structure, DRAMs typically have
four times the density of SRAMs
...
The cost per bit of DRAM storage is three to four times
less than that of SRAM storage
...
These advantages make DRAM the preferred technology for large memories in personal digital computers
...
Most DRAMs have a 1‐bit word size, so several chips
have to be combined to produce a larger word size
...
To reduce the
number of pins in the IC package, designers utilize address multiplexing whereby one
set of address input pins accommodates the address components
...
Since the same set of pins is used for both parts of the
address, the size of the package is decreased significantly
...

A diagram of the decoding configuration is shown in Fig
...
8
...
3

Memory Decoding

311

8-bit column
register

CAS

8 ϫ 256
decoder
RAS

8-bit
address

8-bit
row
register

8 ϫ 256
decoder

256 ϫ 256
memory
cell array

Data
in

Read/Write

Data
out

FIGURE 7
...
There is a single data input line, a single data output line,
and a read/write control, as well as an eight‐bit address input and two address strobes,
the latter included for enabling the row and column address into their respective registers
...
The bar on top of the name
of the strobe symbol indicates that the registers are enabled on the zero level of the
signal
...
Initially,
both strobes are in the 1 state
...
This loads the row address into the row address register
...
After a time equivalent to the settling time of the row selection, RAS goes back
to the 1 level
...
This transfers the column address into the column register and

312

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Memory and Programmable Logic

enables the column decoder
...

CAS must go back to the 1 level before initiating another memory operation
...
4

ERROR DETECTION AND CORRECTION
The dynamic physical interaction of the electrical signals affecting the data path of a
memory unit may cause occasional errors in storing and retrieving the binary information
...
The most common error detection scheme is the parity bit
...
9
...
The parity of the word is checked after reading it from memory
...
If the parity checked results in an
inversion, an error is detected, but it cannot be corrected
...
Each check bit is a parity over a group of bits in the data
word
...
If the check bits are correct, no error has occurred
...
A single error occurs when a bit
changes in value from 1 to 0 or from 0 to 1 during the write or read operation
...


Hamming Code
One of the most common error‐correcting codes used in RAMs was devised by R
...

Hamming
...
The bit positions are numbered in sequence from 1 to n + k
...
The remaining bits are the data bits
...
Before giving
the general characteristics of the code, we will illustrate its operation with a data word
of eight bits
...
We include 4 parity bits with
the 8‐bit word and arrange the 12 bits as follows:
Bit position:

1

2

3

4

5

6

7

8

9

10

11

12

P1

P2

1

P4

1

0

0

P8

0

1

0

0

Section 7
...
The 8 bits
of the data word are in the remaining positions
...
Thus, each
parity bit is set so that the total number of 1’s in the checked positions, including the
parity bit, is always even
...
Substituting the 4 P bits in their proper positions, we obtain the 12‐bit
composite word stored in memory:
0
Bit position:

0

1

1

1

0

0

1

0

1

0

0

1

2

3

4

5

6

7

8

9

10

11

12

When the 12 bits are read from memory, they are checked again for errors
...
The 4 check bits are
evaluated as follows:
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
A 0 check bit designates even parity over the checked bits and a 1 designates odd parity
...
However, if C ϶ 0, then the 4‐bit binary number formed by
the check bits gives the position of the erroneous bit
...
In the second case, there is an
error in bit position number 1 because it changed from 0 to 1
...
Evaluating the XOR of the corresponding bits, we determine the 4 check bits to be as follows:
C8

C4

C2

C1

For no error:

0

0

0

0

With error in bit 1:

0

0

0

1

With error in bit 5:

0

1

0

1

Thus, for no error, we have C = 0000; with an error in bit 1, we obtain C = 0001; and with
an error in bit 5, we get C = 0101
...
The error can be corrected by complementing the corresponding bit
...

The Hamming code can be used for data words of any length
...
The syndrome
value C consists of k bits and has a range of 2k values between 0 and 2k - 1
...
Each of these 2k - 1 values can
be used to uniquely describe a bit in error
...
For example, when k = 3, the number of data bits
that can be used is n … (23 - 1 - 3) = 4
...
The data word may be less than 11 bits, but must have at least 5 bits; otherwise,
only 3 check bits will be needed
...
Ranges of n for various values of k are listed in Table 7
...

The grouping of bits for parity generation and checking can be determined from a
list of the binary numbers from 0 through 2k - 1
...
The second significant bit is a 1 in the binary numbers
,
Table 7
...
5

Read‐Only Memory

315

2, 3, 6, 7, and so on
...
Note
that each group of bits starts with a number that is a power of 2: 1, 2, 4, 8, 16, etc
...


Single‐Error Correction, Double‐Error Detection
The Hamming code can detect and correct only a single error
...
If we include this additional parity bit, then the previous 12‐bit coded
word becomes 001110010100P13, where P13 is evaluated from the exclusive‐OR of the
other 12 bits
...
When the
13‐bit word is read from memory, the check bits are evaluated, as is the parity P over
the entire 13 bits
...
The following four cases can arise:
If C = 0 and P = 0, no error occurred
...

If C ϶ 0 and P = 0, a double error occurred that is detected, but that cannot be
corrected
...

This scheme may detect more than two errors, but is not guaranteed to detect all such
errors
...
The modified Hamming code
uses a more efficient parity configuration that balances the number of bits used to calculate the XOR operation
...

of 16 and 32 bits
...


7
...
The binary information must be specified by the designer and is
then embedded in the unit to form the required interconnection pattern
...

A block diagram of a ROM consisting of k inputs and n outputs is shown in Fig
...
9
...
The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words
...
Integrated

316

Chapter 7

Memory and Programmable Logic

2k ϫ n
ROM

k inputs (address)

n outputs (data)

FIGURE 7
...

Consider, for example, a 32 * 8 ROM
...

There are five input lines that form the binary numbers from 0 through 31 for the
address
...
10 shows the internal logic construction of this ROM
...
Each output of the
decoder represents a memory address
...
The diagram shows the array logic convention used in complex circuits
...
6
...
) Each OR gate must be considered as having 32 inputs
...
Since each OR
gate has 32 input connections and there are 8 OR gates, the ROM contains 32 * 8 = 256
internal connections
...
Each OR gate has 2k inputs, which are connected to each of the outputs
of the decoder
...


...


I3

28

I4

29
30
31

A7

FIGURE 7
...
5

Read‐Only Memory

317

The 256 intersections in Fig
...
10 are programmable
...
The programmable intersection between two lines is sometimes called a crosspoint
...
One of the simplest technologies employs a fuse that normally connects the
two points, but is opened or “blown” by the application of a high‐voltage pulse into
the fuse
...
For example, the content of a 32 * 8 ROM may be
specified with a truth table similar to the one shown in Table 7
...
The truth table shows
the five inputs under which are listed all 32 addresses
...
The table shows only the first four and
the last four words in the ROM
...

The hardware procedure that programs the ROM blows fuse links in accordance with
a given truth table
...
3 results in the configuration shown in Fig
...
11
...
For example, the table specifies the eight‐bit word 10110010
for permanent storage at address 3
...
The four 1’s in the word are marked with a * to denote
a temporary connection, in place of a dot used for a permanent connection in logic
diagrams
...
The signal equivalent to logic 1 at decoder output
3 propagates through the connections to the OR gate outputs of A7, A5, A4, and A1
...
The result is that the stored word 10110010 is applied to
the eight data outputs
...
3
ROM Truth Table (Partial)
Inputs

Outputs

I4

I3

I2

I1

I0

A7

A6

A5

A4

A3

A2

A1

A0

0
0
0
0

0
0
0
0

0
0
0
0
f

0
0
1
1

0
1
0
1

1
0
1
1

0
0
1
0

1
0
0
1

1
1
0
1

0
1
0
0

1
1
1
0

1
0
0
1

0
1
1
0

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

0
1
0
0

0
1
1
0

0
1
0
1

0
0
0
1

1
0
1
0

0
0
0
0

0
1
1
1

1
0
0
1

f

318

Chapter 7

Memory and Programmable Logic

0
1

I0

2

I1
I2

5 ϫ 32
decoder

3

...


...
11
Programming the ROM according to Table 7
...
9, it was shown that a decoder generates the 2k minterms of the k input
variables
...
The ROM is essentially a device that
includes both the decoder and the OR gates within a single device to form a minterm
generator
...

The internal operation of a ROM can be interpreted in two ways
...
The second
interpretation is that of a unit which implements a combinational circuit
...
For example, the ROM of Fig
...
11 may be considered to be a combinational circuit with eight outputs, each a function of the five input
variables
...
)
A connection marked with * in the figure produces a minterm for the sum
...

In practice, when a combinational circuit is designed by means of a ROM, it is not
necessary to design the logic or to show the internal gate connections inside the unit
...
The truth table gives all the information for programming the
ROM
...


Section 7
...
1
Design a combinational circuit using a ROM
...

The first step is to derive the truth table of the combinational circuit
...
In other cases, we can use a partial truth table for the ROM by
utilizing certain properties in the output variables
...
4 is the truth table for the
combinational circuit
...
We note that output B0 is always equal to input A0, so there
is no need to generate B0 with a ROM, since it is equal to an input variable
...
We actually need to generate
only four outputs with the ROM; the other two are readily obtained
...
Three inputs specify eight
words, so the ROM must be of size 8 * 4
...
  7
...
The three inputs specify eight words of four bits each
...
  7
...
The block
diagram of Fig
...
12(a) shows the required connections of the combinational circuit
...
4
Truth Table for Circuit of Example 7
...
12
ROM implementation of Example 7
...
The first
is called mask programming and is done by the semiconductor company during the
last fabrication process of the unit
...
The
truth table may be submitted in a special form provided by the manufacturer or in
a specified format on a computer output medium
...
This procedure is costly because the vendor charges the customer a
special fee for custom masking the particular ROM
...

For small quantities, it is more economical to use a second type of ROM called programmable read‐only memory, or PROM
...
The fuses in the PROM are
blown by the application of a high‐voltage pulse to the device through a special pin
...
This procedure allows the user to program the PROM in the laboratory to achieve the desired
relationship between input addresses and stored words
...
In any case,
all procedures for programming ROMs are hardware procedures, even though the word
programming is used
...
Once a bit pattern
has been established, the unit must be discarded if the bit pattern is to be changed
...
When the EPROM is
placed under a special ultraviolet light for a given length of time, the shortwave radiation
discharges the internal floating gates that serve as the programmed connections
...

The fourth type of ROM is the electrically erasable PROM (EEPROM or E2PROM)
...
The advantage is that the
device can be erased without removing it from its socket
...
They have widespread application in modern technology in cell phones,
digital cameras, set‐top boxes, digital TV, telecommunications, nonvolatile data storage,
and microcontrollers
...
Flash memories incorporate additional
circuitry, too, allowing simultaneous erasing of blocks of memory, for example, of size
16 to 64 K bytes
...


Section 7
...
13
Basic configuration of three PLDs

Combinational PLDs
The PROM is a combinational programmable logic device (PLD)—an integrated circuit
with programmable gates divided into an AND array and an OR array to provide an
AND–OR sum‐of‐product implementation
...
Figure 7 shows the configuration of the three PLDs
...
13
AND array constructed as a decoder and a programmable OR array
...
The PAL has a
programmable AND array and a fixed OR array
...
The most flexible PLD is the PLA, in which both the AND and OR arrays can
be programmed
...
The names PAL and PLA
emerged from different vendors during the development of PLDs
...
The design of
combinational circuits with PLA and PAL is presented in the next two sections
...
6

P R O G R A M M A B L E L O G I C A R R AY
The PLA is similar in concept to the PROM, except that the PLA does not provide full
decoding of the variables and does not generate all the minterms
...
The product terms are then connected to OR gates to provide the sum of products for the required Boolean functions
...
7
...

Such a circuit is too small to be useful commercially, but is presented here to demonstrate
the typical logic configuration of a PLA
...
Each input goes through a buffer–inverter combination, shown in the
diagram with a composite graphic symbol, that has both the true and complement outputs
...
The outputs of the AND
gates are connected to the inputs of each OR gate
...
The output is inverted when the XOR input is connected to 1 (since
x { 1 = xЈ)
...
The particular Boolean functions implemented in the PLA of Fig
...
14
F1 = ABЈ + AC + AЈBCЈ
F2 = (AC + BC)Ј
A

B

C
1

ABЈ

2

AC

3

BC

4

AЈBCЈ

C CЈ B BЈ A AЈ

0
1
F1

F2

FIGURE 7
...
6

Programmable Logic Array

323

The product terms generated in each AND gate are listed along the output of the gate
in the diagram
...
The output of an OR gate gives the logical sum of
the selected product terms
...

The fuse map of a PLA can be specified in a tabular form
...
7 is listed in Table 7
...
14

...
The first section lists the product terms numerically
...
The third
section specifies the paths between the AND and OR gates
...
The
product terms listed on the left are not part of the table; they are included for reference
only
...
If a variable
in the product term appears in the form in which it is true, the corresponding input variable is marked with a 1
...
If the variable is absent from the product term, it is marked with a
dash
...
A 1 in the input column specifies a connection from
the input variable to the AND gate
...
A dash specifies a blown
fuse in both the input variable and its complement
...

The paths between the AND and OR gates are specified under the column head
“Outputs
...
Each product term that has a 1 in the output column
requires a path from the output of the AND gate to the input of the OR gate
...
It is assumed that an open terminal in the
input of an OR gate behaves like a 0
...

Table 7
...


324

Chapter 7

Memory and Programmable Logic

The size of a PLA is specified by the number of inputs, the number of product terms,
and the number of outputs
...
For n inputs, k product terms, and m outputs, the internal logic of the PLA consists of n buffer–inverter gates, k AND gates, m OR gates, and
m XOR gates
...

In designing a digital system with a PLA, there is no need to show the internal connections of the unit as was done in Fig
...
14
...
As with a
ROM, the PLA may be mask programmable or field programmable
...
This table
is used by the vendor to produce a custom‐made PLA that has the required internal
logic specified by the customer
...

In implementing a combinational circuit with a PLA, careful investigation must be
undertaken in order to reduce the number of distinct product terms, since a PLA has a
finite number of AND gates
...
The number of literals in a term is not important, since all
the input variables are available anyway
...


EXAMPLE 7
...
7
...
Both the true value and the
complement of the functions are simplified into sum‐of‐products form
...
The PLA
programming table for the combination is shown in the figure
...
This is because F1 is
generated with an AND–OR circuit and is available at the output of the OR gate
...


Section 7
...
15
Solution to Example 7
...
2 is too simple for implementing with
a PLA
...
A typical PLA has a large
number of inputs and product terms
...
The computer‐aided design (CAD) program simplifies each function and its
complement to a minimum number of terms
...
The PLA programming table is then generated and the
required fuse map obtained
...


7
...
Because only the AND gates are programmable, the PAL is easier to program than, but is not as flexible as, the PLA
...
16 shows the logic configuration of
a typical PAL with four inputs and four outputs
...
There are four sections in the unit,
each composed of an AND–OR array that is three wide, the term used to indicate that
there are three programmable AND gates in each section and one fixed OR gate
...
The horizontal line symbolizes the multiple‐input
configuration of the AND gate
...

Commercial PAL devices contain more gates than the one shown in Fig
...
16
...
The output terminals are sometimes driven by
three‐state buffers or inverters
...
Unlike the situation with a PLA, a product term cannot be shared among two
or more OR gates
...
16
PAL with four inputs, four outputs, and a three‐wide AND–OR structure

Section 7
...
The number of product terms in each section is fixed, and if
the number of terms in the function is too large, it may be necessary to use two sections
to implement one Boolean function
...
The logical sum of two of these terms
is equal to w
...

The PAL programming table is similar to the one used for the PLA, except that
only the inputs of the AND gates need to be programmed
...
6 lists the PAL
Table 7
...
17
Fuse map for PAL as specified in Table 7
...
8

Sequential Programmable Devices

329

programming table for the four Boolean functions
...
7
...
The first
two sections need only two product terms to implement the Boolean function
...
Using the output from w, we can
reduce the function to three terms
...
7
...
17
For each 1 or 0 in the table, we mark the corresponding intersection in the diagram with
the symbol for an intact fuse
...
If the AND gate is not used, we leave all its input fuses
intact
...

As with all PLDs, the design with PALs is facilitated by using CAD techniques
...


7
...
Since the combinational PLD
consists of only gates, it is necessary to include external flip‐flops when they are used in
the design
...
In this
way, the device can be programmed to perform a variety of sequential‐circuit functions
...
The internal logic of these
devices is too complex to be shown here
...
Sequential (or simple) programmable logic device (SPLD)
2
...
Field‐programmable gate array (FPGA)
The sequential PLD is sometimes referred to as a simple PLD to differentiate it from
the complex PLD
...
The result is a sequential circuit as shown in Fig
...
18
...
The circuit outputs can be taken from the OR gates or from the outputs of the
Inputs
AND–OR array
(PAL or PLA)

Outputs
Flip-flops

FIGURE 7
...
Additional programmable connections are available to include the flip‐flop
outputs in the product terms formed with the AND array
...

The first programmable device developed to support sequential circuit implementation
is the field‐programmable logic sequencer (FPLS)
...
The flip‐flops are flexible in that they can be
programmed to operate as either the JK or the D type
...
The configuration mostly
used in an SPLD is the combinational PAL together with D flip‐flops
...
Each section of an SPLD is called a macrocell, which is
a circuit that contains a sum‐of‐products combinational logic function and an optional
flip‐flop
...
7

...
19 shows the logic of a basic macrocell
...
7
...
The output is driven by an edge‐triggered
D flip‐flop connected to a common clock input and changes state on a clock edge
...
The output of the flip‐flop is fed
back into one of the inputs of the programmable AND gates to provide the present‐state
condition for the sequential circuit
...
19
Basic macrocell logic

Section 7
...
All the flip‐flops are connected to the common CLK input, and all
three‐state buffers are controlled by the OE input
...
Typical programming options include the ability to either use or bypass
the flip‐flop, the selection of clock edge polarity, the selection of preset and clear for the
register, and the selection of the true value or complement of an output
...
Multiplexers select between two or
four distinct paths by programming the selection inputs
...
For this type of application, it is more
economical to use a complex programmable logic device (CPLD), which is a collection
of individual PLDs on a single integrated circuit
...

Figure 7
...
The device consists of multiple PLDs interconnected through a programmable switch matrix
...
Each I/O pin is driven by a three‐
state buffer and can be programmed to act as input or output
...
Similarly,
selected outputs from macrocells are sent to the outputs as needed
...
If a macrocell has unused
product terms, they can be used by other nearby macrocells
...

Different manufacturers have taken different approaches to the general architecture
of CPLDs
...
20
General CPLD configuration

PLD

PLD

332

Chapter 7

Memory and Programmable Logic

function blocks), the type of macrocells, the I/O blocks, and the programmable interconnection structure
...

The basic component used in VLSI design is the gate array, which consists of a pattern
of gates, fabricated in an area of silicon, that is repeated thousands of times until the entire
chip is covered with gates
...
The design with
gate arrays requires that the customer provide the manufacturer the desired interconnection pattern
...
Additional fabrication steps are required to interconnect the
gates according to the specifications given by the designer
...
A typical FPGA consists of an array of millions of logic blocks,
surrounded by programmable input and output blocks and connected together via programmable interconnections
...
The performance of each type of device depends on the circuit
contained in its logic blocks and the efficiency of its programmed interconnections
...
A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic block
...
5
...
The
combinational logic section, along with a number of programmable multiplexers, is
used to configure the input equations for the flip‐flop and the output of the logic
block
...
The disadvantage is that the memory is
volatile and presents the need for the lookup table’s content to be reloaded in the event
that power is disrupted
...
The program remains in SRAM until the FPGA is reprogrammed or the power is turned off
...
The ability to reprogram the FPGA can serve a variety of applications by using different logic implementations in the program
...
Among the tools that are available
are schematic entry packages and hardware description languages (HDLs), such as
ABEL, VHDL, and Verilog
...
As an
example of CMOS FPGA technology, we will discuss the Xilinx FPGA
...
Altera
...


Section 7
...
2 The XC3000 and XC4000 families soon followed, setting the stage for
today’s Spartan™, and Virtex™ device families
...
For example, the Spartan family of devices initially offered a maximum of
40K system gates, but today’s Spartan‐6 offers 150,000 logic cells plus 4
...


Basic Xilinx Architecture
The basic architecture of Spartan and earlier device families consists of an array of
configurable logic blocks (CLBs), a variety of local and global routing resources, and
input–output (I/O) blocks (IOBs), programmable I/O buffers, and an SRAM‐based
configuration memory, as shown in Fig
...
21
...
21
Basic architecture of Xilinx Spartan and predecessor devices
2

See www
...
com for detailed, up‐to‐date information about Xilinx products
...
7
...
22
table can generate any arbitrary function of four inputs, and the third (H) can generate any
Boolean function of three inputs
...
The three function generators can be programmed
to generate (1) three different functions of three independent sets of variables (two with
four inputs and one with three inputs—one function must be registered within the CLB),
(2) an arbitrary function of five variables, (3) an arbitrary function of four variables together
with some functions of six variables, and (4) some functions of nine variables
...
The storage elements can get their inputs from the function
generators or from the Din input
...
The function generators can also drive two outputs (X and Y) directly and
independently of the outputs of the storage elements
...
The storage elements are driven by a global set/
reset during power‐up; the global set/reset is programmed to match the programming
of the local S/R control for a given storage element
...
The XC4000 devices do not have block RAM, but
a group of their CLBs can form an array of memory
...


Interconnect Resources
A grid of switch matrices overlays the architecture of CLBs to provide general‐purpose
interconnect for branching and routing throughout the device
...
A grid of horizontal and vertical single‐length lines connects an array of
switch boxes that provide a reduced number of connections between signal paths within
each box, not a full crossbar switch
...

Direct (dedicated) interconnect lines provide routing between adjacent vertical and
horizontal CLBs in the same column or row
...
Direct interconnect lines do not use the switch matrices, thus eliminating
the delay incurred on paths going through a matrix
...


C1
...
G4

D SD

YQ
Q

HЈ

Section 7
...
22
CLB architecture

Note: Muxes without a select line
are configured by the program memory
...
F4

EC

FЈ

Logic
Function HЈ
of FЈ, GЈ,
and H1

F4
F3
F2
F1

SR/H0

335

336

Chapter 7

Memory and Programmable Logic
Configuration Control
Write
Static RAM
Cell
Read

Interconnect path

FIGURE 7
...
These lines provide a more efficient implementation
of intermediate‐length connections by eliminating a switch matrix from the path, thereby
reducing the delay of the path
...
They drive low‐skew,
high‐fan‐out control signals
...
The routing resources are exploited automatically
by the routing software
...

The signals that drive long lines are buffered
...
Long
lines provide three‐state buses within the architecture and implement wired‐AND logic
...

The programmable interconnect resources of the device connect CLBs and IOBs, either
directly or through switch boxes
...
A PIP is a
CMOS transmission gate whose state (on or off) is determined by the content of a static
RAM cell in the programmable memory, as shown in Fig
...
23
...
e
...
Thus, the device can
be reprogrammed simply by changing the contents of the controlling memory cell
...
7
...
The configuration of CMOS transmission gates determines the connection between a horizontal line and the opposite horizontal line and between the vertical lines at the connection
...


Section 7
...
24
Circuit for a programmable PIP

I/O Block (IOB)
Each programmable I/O pin has a programmable IOB having buffers for compatibility
with TTL and CMOS signal levels
...
25 shows a simplified schematic for a programmable IOB
...
An IOB
that is configured as an input can have direct, latched, or registered input
...
The output buffer of an IOB has
skew and slew control
...
There is a global set/reset
...
This strategy eliminates the hold condition on the data at an external pin
...
The output and the enable for the output can be
inverted
...
The IOB pin can be programmed
for pull‐up or pull‐down to prevent needless power consumption and noise
...
1 (JTAG) boundary scan
standard
...
Under testing, the device can be checked to verify that all
the pins on a PC board are connected and operate properly by creating a serial chain of
all of the I/O pins of the chips on the board
...


Enhancements
Spartan chips can accommodate embedded soft cores, and their on‐chip distributed, dual‐
port, synchronous RAM (SelectRAM) can be used to implement first‐in, first‐out register

Chapter 7

Memory and Programmable Logic
VCC

Passive
pull-up
pull-down

Slew rate
control

OE
I/O
PAD

D Q
O

Output
buffer

Output
clock

Input
buffer

I1
Delay
I2
Q D

Input
clock

FIGURE 7
...
26
Distributed RAM cell formed from a lookup table

files (FIFOs), shift registers, and scratchpad memories
...
Figure 7
...
8

Sequential Programmable Devices

339

WE

16 ϫ 1
RAM array

Write
control

D

Read row
select

4

Input register

A[3:0]

Write row
select

4

SPO

Read
out

Read row
select

Write row
select

WCLK

16 ϫ 1
RAM array

Write
control

Read
out

DPRA[3:0]
4

SPO

FIGURE 7
...
Each CLB can be programmed as a 16 * 2 or 32 * 1 memory
...
 7
...
A CLB can
form a memory having a maximum size of 16 * 1
...
4 The lookup tables of the devices can implement 22
different functions of n inputs
...
Logic capacity is expressed in terms
of the number of two‐input NAND gates that would be required to implement the same number and type of logic
functions (Xilinx App
...


340

Chapter 7

Memory and Programmable Logic

Table 7
...

1 Logic cell = four‐input lookup table + flip‐flop
...
Spartan XL devices
offer up to 80‐MHz system performance, depending on the number of cascaded lookup
tables, which reduce performance by introducing longer paths
...
7 presents significant attributes of devices in the Spartan XL family
...

These devices support only distributed memory, whose use reduces the number of
CLBs that could be used for logic
...
Beginning with the Spartan II series, Xilinx
supported configurable embedded block memory, as well as distributed memory in a
new architecture
...
5 V), four other features distinguish the
Spartan II devices from the Spartan devices: (1) on‐chip block memory, (2) a novel
architecture, (3) support for multiple I/O standards, and (4) delay locked loops (DLLs)
...
22>0
...


Section 7
...
A large on‐chip memory can improve system performance by eliminating
or reducing the need to access off‐chip storage
...
If the clock signal arrives at different times at different parts of a circuit,
the device may fail to operate correctly
...
It can also shorten the effective
hold‐time margin of a flip‐flop in a shift register and cause the register to shift incorrectly
...
Buffered clock
trees are commonly used to minimize clock skew in FPGAs
...
DLLs eliminate
the clock distribution delay and provide frequency multipliers, frequency dividers, and
clock mirrors
...
Device attributes are
summarized in Table 7 , and the evolution of technology in the Spartan series is evident

...
9
...
8
Spartan II Device Attributes
Spartan II FPGAs
System Gates

1

2

Logic Cells

Block RAM Bits
Max Avail I/O
1
2

XC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

6K–15K

13K–30K

23K–50K 37K–100K 52K–150K

71K–200K

432

972

1,728

2,700

3,888

5,292

16,384

24,576

32,768

40,960

49,152

57
,344

86

132

176

196

260

284

20–30% of CLBs as RAM
...


Table 7
...
3 V

2
...
28
Spartan II architecture

The top‐level tiled architecture of the Spartan II device, shown in Fig
...
28 , marks
a new organization structure of the Xilinx parts
...

Each CLB contains four logic cells, organized as a pair of slices
...
7
...
The CLB contains additional logic for configuring functions of five or six inputs
...

The IOBs of the Spartan II family are individually programmable to support the
reference, output voltage, and termination voltages of a variety of high‐speed memory

6

Parts are available with up to 14 blocks (56K bits)
...
8

Sequential Programmable Devices

343

Logic Cell
COUT
YB
Y
G4

I4

G2

Lookup
I3 Table
O
I2

G1

D S Q

I1

G3

Carry
and
Control
Logic

YQ

CK
EC

R

F5IN
BY
SR
XB
X
F4

I4

F2

Lookup
I3 Table
O
I2

F1

Carry
and
Control
Logic

D S Q

XQ

I1

F3

CK
EC

R

BX
CIN
CLK
CE

FIGURE 7
...
(See Fig
...
30
...
One register (TFF ) can be used to register the signal that (synchronously) controls the programmable output buffer
...

(Alternatively, a signal from the internal logic can pass directly to the output buffer
...
(Alternatively, this

344

Chapter 7

Memory and Programmable Logic

T

CLK

D SR Q
TFF
CK

TCE

EC

VCCO
Package Pin
VCC
OE

SR
D SR Q
OFF
CK

O

OCE

Programmable
output buffer

Programmable
Bias &
ESD Network

I/O
Package Pin

Internal
Reference

EC
Programmable
Delay

IQ
D SR Q
IFF
CK

I

ICE

EC

I/O
Package Pin

Programmable
input buffer

To Other
External
VREF
Inputs of
Banks

To Next
I/O

FIGURE 7
...
) A common clock drives each register,
but each has an independent clock enable
...


Xilinx Virtex FPGAs
The Virtex device series7 is the leading edge of Xilinx technology
...
The family targets
applications requiring a balance of high‐performance logic, serial connectivity, signal
processing, and embedded processing (e
...
, wireless communications)
...


Section 7
...
31
Virtex II overall architecture

for leading‐edge Virtex parts stand at 65 nm, with a 1‐V operating voltage
...

The Virtex family incorporates physical (electrical) and protocol support for
20 different I/O standards, including LVDS and LVPECL, with individually programmable pins
...
The Virtex architecture is shown in Fig
...
31, and its IOB is shown
in Fig
...
32
...
32
Virtex IOB block

PROBLEMS
Answers to problems marked with * appear at the end of the book
...
1

The memory units that follow are specified by the number of words times the number of
bits per word
...
2*

Give the number of bytes stored in the memories listed in Problem 7

...


7
...
7 contains the binary equivalent of 1,212
...
3
List the 10‐bit address and the 16‐bit memory content of the word
...
4

Show the memory cycle timing waveforms for the write and read operations
...


7
...
1
...

stored contents
...
6

Enclose the 4 * 4 RAM of Fig
...
6 in a block diagram showing all inputs and outputs
...


Problems

347

7
...

(a) What is the size of each decoder, and how many AND gates are required for decoding
the address?
(b) Determine the X and Y selection lines that are enabled when the input address is the
binary equivalent of 6,000
...
8*

(a) How many 32K * 8 RAM chips are needed to provide a memory capacity of 256K
bytes?
(b) How many lines of the address must be used to access 256K bytes? How many of these
lines are connected to the address inputs of all chips?
(c) How many lines must be decoded for the chip select inputs? Specify the size of the
decoder
...
9

A DRAM chip uses two‐dimensional address multiplexing
...
What is the capacity
of the memory?

7
...

7
...

7
...
What was the original 8‐bit data word that was written into memory if the 12‐bit
word read out is as follows:
(a) 000011101010
(b) 101110000110
(c) 101111110100
7
...

(b) 32 bits
...

7
...

(a)* Evaluate the 7‐bit composite code word for the data word 0010
...

(c) Assume an error in bit D5 during writing into memory
...

(d) Add parity bit P8 to include double‐error detection in the code
...
Show how the double error is detected
...
15 Using 64 * 8 ROM chips with an enable input, construct a 512 * 8 ROM with eight chips
and a decoder
...
16* A ROM chip of 4,096 * 8 bits has two chip select inputs and operates from a 5‐V power
supply
...

7
...
P7 , converts a six‐bit binary

...
For example, binary 100001 converts
to BCD 011 0011 (decimal 33)
...


348

Chapter 7

Memory and Programmable Logic
20

21
22

/2

23

/3

24

/4

25

/5

D1

/1

100

D2
32 ϫ 6
ROM

D3
D4
D5

101

D6

FIGURE P7
...
18* Specify the size of a ROM (number of words and number of bits per word) that will
accommodate the truth table for the following combinational circuit components:
(a) a binary multiplier that multiplies two 4‐bit binary words,
(b) a 4‐bit adder–subtractor,
(c) a quadruple two‐to‐one‐line multiplexer with common select and enable inputs, and
(d) a BCD‐to‐seven‐segment decoder with an enable input
...
19 Tabulate the PLA programming table for the four Boolean functions listed below
...

A(x, y, z) = ⌺(1, 3, 5, 6)
B(x, y, z) = ⌺(0, 1, 6, 7)
C(x, y, z) = ⌺(3, 5)
D(x, y, z) = ⌺(1, 2, 4, 5, 7)
7
...
Specify the memory contents at addresses 1 and 4
...
21 Derive the PLA programming table for the combinational circuit that squares a three‐bit
number
...
(See Fig
...
12 for the equivalent ROM
implementation
...
22 Derive the ROM programming table for the combinational circuit that squares a 4‐bit
number
...

7
...
4
...


References

349

7
...


...
25* The following is a truth table of a three‐input, four‐output combinational circuit:
Inputs

Outputs

x

y

z

A

B

C

D

0

0

0

0

1

0

0

0

0

1

1

1

1

1

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

0

0

1

1

1

0

1

0

1

0

0

0

1

1

1

0

1

0

1

0

1

1

1

0

1

1

1

Tabulate the PAL programming table for the circuit, and mark the fuse map in a PAL
diagram similar to the one shown in Fig
...
17
...
26 Using the registered macrocell of Fig
...
19
two inputs x and y and one flip‐flop A described by the input equation
DA = x { y { A
7
...
7
...
7
...
The diagram should conform with the block
diagram of a sequential circuit
...
Using the modified registered PAL diagram,
show the fuse map that will implement a three‐bit binary counter with an output carry
...
28 Draw a PLA circuit to implement the functions
F1 = AЈB + AC + AЈBCЈ
F2 = (AC + AB + BC)Ј
7
...
26
...

2
...

4
...


Hamming, R
...
1950
...
Bell Syst
...
J
...

Kitson, B
...
Programmable Array Logic Handbook
...

Lin, S
...
J
...
2004
...
2nd ed
...

Memory Components Handbook
...
Santa Clara, CA: Intel
...
P
...
T
...
D
...
D
...
1995
...
Upper Saddle River, NJ: Prentice Hall
...

7
...

9
...
1994
...

Tocci, R
...
and N
...
Widmer
...
Digital Systems Principles and Applications, 9th ed
...

Trimberger, S
...
1994
...
Boston: Kluwer
Academic Publishers
...
F
...
Digital Design: Principles and Practices, 4th ed
...


WEB SEARCH TOPICS
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Chapter 8

Design at the Register Transfer Level

8
...

Such systems are said to have “memory
...
Sequential circuits can be specified by means of
state tables as shown in Chapter 5
...
To overcome this difficulty, digital systems are designed via a modular approach
...
The modules are constructed
from such digital devices as registers, decoders, multiplexers, arithmetic elements, and
control logic
...
In this chapter, we will introduce a design methodology for
describing and designing large, complex digital systems
...
2

R E G I S T E R T R A N S F E R L E V E L N O TAT I O N
The modules of a digital system are best defined by a set of registers and the operations that are performed on the binary information stored in them
...
Registers are assumed to be the
basic components of the digital system
...
We’ll see subsequently how a hardware description language (HDL) includes
operators that correspond to the register transfer operations of a digital system
...
The set of registers in the system
...
The operations that are performed on the data stored in the registers
...
The control that supervises the sequence of operations in the system
...
A register can load new
information or shift the information to the right or the left
...
g
...
A flip‐flop is a one‐bit register that can
be set, cleared, or complemented
...

The operations executed on the information stored in registers are elementary operations that are performed in parallel on the bits of a data word during one clock cycle
...
Alternatively, the result may be transferred to
another register (i
...
, an operation on a register may leave its contents unchanged)
...
A counter with a parallel load is able to perform the increment‐by‐one and load
operations
...

The operations in a digital system are controlled by signals that sequence the operations in a prescribed manner
...
The outputs of the control
logic of a digital system are binary variables that initiate the various operations in the
system’s registers
...
The statement
R2 d R1
denotes a transfer of the contents of register R1 into register R2—that is, a replacement
of the contents of register R2 by the contents of register R1
...
By definition, the contents of the source register R1 do not change
after the transfer
...
The arrow symbolizes the transfer and
its direction; it points from the register whose contents are being transferred and towards
the register that will receive the contents
...

The controller in a digital system is a finite state machine (see Chapter 5) whose
outputs are the control signals governing the register operations
...
For example, register
R2 might be synchronized to have its contents replaced at the positive edge of the clock
...
e
...
2

Register Transfer Level Notation

353

inputs of the destination register and that the destination register has a parallel load
capability
...
Normally, we want a register transfer
operation to occur, not with every clock cycle, but only under a predetermined condition
...
Note that the clock is not
included as a variable in the register transfer statements
...
e
...
Although
a control condition such as T1 may become true before the clock transition, the actual
transfer does not occur until the clock transition does
...
Propagation delays depend on the physical characteristics of the transistors
implementing the flip‐flops of the register and the wires connecting devices
...

A comma may be used to separate two or more operations that are executed at the
same time (concurrently)
...
This simultaneous (concurrent) operation is possible with registers that have
edge‐triggered flip‐flops controlled by a common clock (synchronizing signal)
...
The type of operations most often encountered in digital systems can be classified into four categories:
1
...
e
...

2
...
g
...

3
...
g
...

4
...

The transfer operation does not change the information content of the data being moved
from the source register to the destination register unless the source and destination are

354

Chapter 8

Design at the Register Transfer Level

the same
...
The register transfer notation and the symbols used to represent the various register transfer operations are not standardized
...
The notation introduced in this section will be used informally to specify and
explain digital systems at the register transfer level
...


8
...
In the
Verilog HDL, descriptions of RTL operations use a combination of behavioral and dataflow constructs and are employed to specify the register operations and the combinational logic functions implemented by hardware
...

Combinational circuit functions are specified at the RTL level by means of continuous
assignment statements or by procedural assignment statements within a level‐sensitive
cyclic behavior
...
Synchronization with the clock is represented by associating with an always
statement an event control expression in which sensitivity to the clock event is qualified
by posedge or negedge
...
The @ operator and the
event control expression preceding the block of statements synchronize the execution
of the statements to the clock event
...
g
...
In simulation, a continuous assignment statement executes
when the expression on the right‐hand side changes
...


Section 8
...
) Similarly, a level‐sensitive cyclic behavior (e
...
, always @ (A, B)) executes during simulation when a change is detected by its
event control expression (sensitivity list)
...
The continuous assignment statement (assign S = A + B) describes a
binary adder with inputs A and B and output S
...
The procedural assignment made in the level‐sensitive cyclic
behavior in the second example shows an alternative way of specifying a combinational
circuit for addition
...

There are two kinds of procedural assignments: blocking and nonblocking
...
Blocking assignments use the
equals symbol (=) as the assignment operator, and nonblocking assignments use the left
arrow (6 =) as the operator
...

Nonblocking assignments are made concurrently
...
Consequently, there is no interaction between the result of any assignment and the evaluation of an expression affecting
another assignment
...
Consider (c) in the example
given above
...

The value in RA after the clock event is the sum of the values in RA and RB immediately
before the clock event
...
In the nonblocking procedural assignment ((d) above), the two assignments
are performed concurrently, so that RD receives the original value of RA
...

The registers in a system are clocked simultaneously (concurrently)
...
To ensure synchronous operations in RTL design, and
to ensure a match between an HDL model and the circuit synthesized from the model,
it is necessary that nonblocking procedural assignments be used for all variables that
are assigned a value within an edge‐sensitive cyclic behavior (always clocked)
...
In general, the
blocking assignment operator (=) is used in a procedural assignment statement only
when it is necessary to specify a sequential ordering of multiple assignment statements
...
1
...
The

356

Chapter 8

Design at the Register Transfer Level
Table 8
...

The operands of the arithmetic operators are numbers
...

The exponentiation operator (**) was added to the language in 2001 and forms a
double‐precision floating‐point value from a base and exponent having a real, integer,

Section 8
...
Negative numbers are represented in 2’s‐complement form
...
For example,
14 % 3 evaluates to 2
...
The
bitwise operators perform a bit‐by‐bit operation on two vector operands to form a vector result
...
Negation (~) is a unary operator; it complements
the bits of a single vector operand to form a vector result
...
They operate pairwise on the bits of a word, from right to left, and yield a one‐bit result
...
The result of applying the NOR operation on the first two bits is used with the
third bit, and so forth
...
Truth tables for the bitwise operators acting on a pair of
scalar operands are the same as those listed in Table 4
...
12 for the corresponding Verilog primitive (e
...
, the and primitive and the & bitwise operator have the
same truth table)
...

The logical and relational operators are used to form Boolean expressions and can
take variables or expressions as operands
...
) Used
basically for determining true or false conditions, the logical and relational operators
evaluate to 1 if the condition expressed is true and to 0 if the condition is false
...
An operand that is a variable evaluates to 0
if the value of the variable is equal to zero and to 1 if the value is not equal to zero
...

Results of other operations with these values are as follows:
A && B = 0

// Logical AND:

(1010) && (0000) = 0

A & B = 0000

// Bitwise AND:

(1010) & (1010) = (0000)

A || B = 1

// Logical OR:

(1010) || (0000) = 1

A | B = 1010

// Bitwise OR:

(1010) | (0000) = (1010)

!A = 0

// Logical negation

!(1010) = !(1) = 0

~A = 0101

// Bitwise negation

~(1010) = (0101)

!B = 1

// Logical negation

!(0000) = !(0) = 1

~B = 1111

// Bitwise negation

~(0000) = 1111

(A > B) = 1

// is greater than

(A == B) = 0

// identity (equality)

The relational operators = = = and ! = = test for bitwise equality (identity) and inequality in Verilog’s four‐valued logic system
...


358

Chapter 8

Design at the Register Transfer Level

Verilog 2001 has logical and arithmetic shift operators
...
The vacated bit
positions are filled with zeros
...
The value of R that results from the logical right‐shift
operation (11010) >> 1 is 01101
...
The arithmetic left‐shift operator fills the vacated cell with a 0
when the word is shifted to the left
...
If R = 11010, then the statement
R >>> 1;

produces the result R = 11101; if R = 01101, it produces the result R = 00110
...

The concatenation operator provides a mechanism for appending multiple operands
...
This aspect of its operation was shown in HDL Example 6
...

Expressions are evaluated from left to right, and their operators associate from left
to right (with the exception of the conditional operator) according to the precedence
shown in Table 8
...
For example, in the expression A + B – C, the value of B is added
to A, and then C is subtracted from the result
...
Use parentheses to establish
precedence
...


Loop Statements
Verilog HDL has four types of loops that execute procedural statements repeatedly:
repeat, forever, while, and for
...

The repeat loop executes the associated statements a specified number of times
...


Section 8
...
2
Verilog Operator Precedence
+ − ! ~ & ~& | ~ | ^ ~^ ^~ (unary)

Highest precedence

**
*/%
+ − (binary)
<< >> <<< >>>
< < = > >=
== != === !==
& (binary)
^ ^~ ~^ (binary)
| (binary)
&&
||
?: (conditional operator)
{}{{}}

Lowest precedence

The forever loop causes unconditional, repetitive execution of a procedural statement
or a block of procedural statements
...
If the expression is false to begin with, the statement is never executed
...
Each increment is delayed by five time
units, and the loop exits at the count of 64
...
Integers are declared with the keyword integer, as in the previous
example
...

Variables declared as data type reg are stored as unsigned numbers
...
The default
width of an integer is a minimum of 32 bits
...
The for loop contains three parts separated by two
semicolons:
• An initial condition
...

• An assignment to change the control variable
...
The
control variable is j, the initial condition is j = 0, and the loop is repeated as long as j is less
than 8
...

A description of a two‐to‐four‐line decoder using a for loop is shown in HDL Example 8
...
Since output Y is evaluated in a procedural statement, it must be declared as
type reg
...
When the loop is expanded
(unrolled), we get the following four conditions (IN and Y are in binary, and the index
for Y is in decimal):
if IN = 00 then Y(0) = 1; else Y(0) = 0;
if IN = 01 then Y(1) = 1; else Y(1) = 0;
if IN = 10 then Y(2) = 1; else Y(2) = 0;
if IN = 11 then Y(3) = 1; else Y(3) = 0;

HDL Example 8
...
3

Register Transfer Level in HDL

361

always @ (IN)
for (k = 0; k <= 3; k = k + 1)
if (IN == k) Y[k] = 1;
else Y[k] = 0;
endmodule

Logic Synthesis
Logic synthesis is the automatic process by which a computer‐based program (i
...
, a
synthesis tool) transforms an HDL model of a logic circuit into an optimized netlist of
gates that perform the operations specified by the source code
...
The effective use of
an HDL description requires that designers adopt a vendor‐specific style suitable for
the particular synthesis tools
...
Logic synthesis is widely used in industry to
design and implement large circuits efficiently, correctly, and rapidly
...
Designs written in Verilog or a comparable language for the purpose of logic synthesis tend to be at the register transfer level
...
The following examples discuss
how a logic synthesizer can interpret an HDL construct and convert it into a gate
structure
...
In an HDL, it represents a Boolean equation for a logic circuit
...

An expression with an addition operator (+) is interpreted as a binary adder using
full‐adder circuits
...
4
...

A statement with a conditional operator such as
assign Y = S ? In_1 : In_0;

translates into a two‐to‐one‐line multiplexer with control input S and data inputs In_1
and In_0
...

A cyclic behavior (always
...

A synthesis tool will interpret as combinational logic a level‐sensitive cyclic behavior
whose event control expression is sensitive to every variable that is referenced within
the behavior (e
...
, by the variable’s appearing in the right‐hand side of an assignment

362

Chapter 8

Design at the Register Transfer Level

statement)
...
For example,
always @ (In_1 or In_0 or S)
if (S) Y = In_1;
else Y = In_0;

// Alternative: (In_1, In_0, S)

translates into a two‐to‐one‐line multiplexer
...
The casex statement treats the logic values x and z
as don’t‐cares when they appear in either the case expression or a case item
...
g
...
The implementation of the corresponding circuit
consists of D flip‐flops and the gates that implement the synchronous register transfer
operations specified by the statements associated with the event control expression
...
A sequential circuit description
with a case statement translates into a control circuit with D flip‐flops and gates that
form the inputs to the flip‐flops
...
For
synthesizable sequential circuits, the event control expression must be sensitive to the
positive or the negative edge of the clock (synchronizing signal), but not to both
...
8
...
The RTL description of the HDL design is simulated and checked for
proper operation
...
The test bench provides the stimulus signals to the simulator
...
After the simulation run shows a valid design, the RTL description
is ready to be compiled by the logic synthesizer
...
The synthesis tool generates a
netlist equivalent to a gate‐level description of the design as it is represented by the
model
...
The gate‐level circuit is simulated with the same set of stimuli used to
check the RTL design
...
The results of the two simulations are compared to
see if they match
...
Then the description is compiled again by the logic synthesizer
to generate a new gate‐level description
...
In practice, additional testing will be performed to verify that the timing
specifications of the circuit can be met in the chosen hardware technology
...

Logic synthesis provides several advantages to the designer
...
The ease of changing the description
facilitates exploration of design alternatives
...
4

Algorithmic State Machines (ASMs)

363

Develop specification

Develop/edit HDL
description

Simulate/verify HDL
description

No

Test bench

Correct?

Yes

Synthesize
netlist

Yes Synthesis
tools?

No

Develop
(manually)
gate-level
model

Compare
simulation
results

Simulate netlist/model

Create production
masks for ICs

Yes

Match?

No

FIGURE 8
...
A schematic and the database for fabricating the integrated
circuit can be generated automatically by synthesis tools
...
g
...


8
...
Data are discrete elements of information (binary words) that are
manipulated by performing arithmetic, logic, shift, and other similar data‐processing

364

Chapter 8

Design at the Register Transfer Level

operations
...
Control information provides command signals that coordinate and execute the various operations in the data
section of the machine in order to accomplish the desired data‐processing tasks
...
One
part is concerned with designing the digital circuits that perform the data‐processing
operations
...

The relationship between the control logic and the data‐processing operations in a
digital system is shown in Fig
...
2
...

The control unit issues a sequence of commands to the datapath unit
...
We’ll see later that understanding how to model this feedback
relationship with an HDL is very important
...
e
...
The
control commands for the system are produced by the FSM as functions of the primary
inputs, the status signals, and the state of the machine
...
Depending on status conditions and other external inputs, the FSM goes
to its next state to initiate other operations
...

Input
data

Input
signals
(external)

Control
signals
Control unit
(FSM)

Datapath
unit
Status
signals

Output
data

FIGURE 8
...
4

Algorithmic State Machines (ASMs)

365

The control sequence and datapath tasks of a digital system are specified by means of
a hardware algorithm
...
A hardware algorithm is a procedure for
solving the problem with a given piece of equipment
...
The goal is to implement the algorithms in silicon as an integrated circuit
...
A flowchart for a hardware algorithm translates the verbal
instructions to an information diagram that enumerates the sequence of operations
together with the conditions necessary for their execution
...
A state machine is another term for a sequential circuit,
which is the basic structure of a digital system
...
A conventional flowchart describes the procedural steps and decision paths of an
algorithm in a sequential manner, without taking into consideration their time relationship
...
e
...
e
...
The chart is adapted to specify accurately the control sequence and datapath operations in a digital system, taking into consideration the
constraints of digital hardware
...
The boxes themselves are connected by directed edges indicating the sequential precedence and evolution of the states as the machine operates
...
In one, a state in the control
sequence is indicated by a state box, as shown in Fig
...
3(a)
...
The state is given a symbolic
name, which is placed within the upper left corner of the box
...
(The state symbol and code can be placed
Binary code
State name
Moore-type
output signals, register operations

(a)

FIGURE 8
...
) Figure 8
...
The state has the
symbolic name S_pause, and the binary code assigned to it is 0101
...
The
name Start_OP_A inside the box indicates, for example, a Moore‐type output signal that
is asserted while the machine is in state S_pause and that launches a certain operation
in the datapath unit
...
8
...
Although the
operation is written inside the state box, it actually occurs when the machine makes a
transition from S_pause to its next state
...

Later we’ll introduce a chart and notation that are more suited to digital design and that
will eliminate any ambiguity about the register operations controlled by a state machine
...
e
...
The box is diamond shaped and has two or more exit paths, as shown in Fig
...
4
...
One or the other exit path is taken, depending on
the evaluation of the condition
...
When an input condition is assigned a
binary value, the two paths are indicated by 1 and 0, respectively
...
The third element, the conditional box, is unique to the ASM chart
...
8
...
Its rounded corners differentiate it from the state box
...
The outputs listed inside the conditional box are generated as Mealy‐type signals during a given state; the register operations listed in the
conditional box are associated with a transition from the state
...
5(b) shows an
example with a conditional box
...
If Flag = 1, then R is cleared to 0; otherwise,
R remains unchanged
...
A register operation is

1

Exit path

Condition

2
Exit path

FIGURE 8
...
4

Algorithmic State Machines (ASMs)
Reset_b

Reset_b

Binary code

001

001
S_1

S_1

State name
Moore-type output signals
Unconditional register
operations

Start

0

Flag

Condition

Start

1

R
Conditional
(Mealy) outputs
and register
operations

367

0

1

Flag

0

Flush_R

010
S_2
F

010
S_2
Load_F_G

G
100

S_3

(a)

100
S_3

(b)

(c)

FIGURE 8
...
We again note that this style of chart can be a source of confusion,
because the state machine does not execute the indicated register operation R d 0 when
it is in S_1 or the operation F d Gwhen it is in S_2
...
Likewise, in state S_2, the controller must generate a Moore‐type output signal that
causes the register operation F d G to execute in the datapath unit
...
Thus, the control signal generated in a given
state affects the operation of a register in the datapath when the next clock transition
occurs
...

The ASM chart in Fig
...
5(b) mixes descriptions of the datapath and the controller
...
8
...
In their place are the control signals that must be generated by the
control unit to launch the operations of the datapath unit
...

(We’ll address this issue later
...


368

Chapter 8

Design at the Register Transfer Level

ASM Block
An ASM block is a structure consisting of one state box and all the decision and conditional boxes connected to its exit path
...
An ASM chart consists
of one or more interconnected blocks
...
8
...

Associated with state S_0 are two decision boxes and one conditional box
...
A state
box without any decision or conditional boxes constitutes a simple block
...
e
...
The operations within the state and conditional boxes in Fig
...
6(a) are initiated by a common
clock pulse when the state of the controller transitions from S_0 to its next state
...
The ASM chart for the controller alone
is shown in Fig
...
6(b)
...
In general, the Moore‐type outputs of the controller
are generated unconditionally and are indicated within a state box; the Mealy‐type
outputs are generated conditionally and are indicated in the conditional boxes connected to the edges that leave a decision box
...
Each state block is equivalent
to a state in a sequential circuit
...
6
ASM blocks

1

E
0

F
100

S_3

(a)

001
S_0
incr_A

1

Clear_B

010
S_1

011
S_2

100
S_3

(b)

Section 8
...
7
State diagram equivalent to the ASM chart of Fig
...
6

written along the directed lines that connect two states in a state diagram
...
As an illustration, the ASM chart
of Fig
...
6 is drawn as a state diagram (outputs are omitted) in Fig
...
7 The states are

...
The directed lines indicate
the conditions that determine the next state
...


Simplifications
A binary decision box of an ASM chart can be simplified by labeling only the edge corresponding to the asserted decision variable and leaving the other edge without a label
...
Output signals that are not asserted are not shown
on the chart; the presence of the name of an output signal indicates that it is asserted
...
The clock pulses are applied not only to the registers of the datapath,
but also to all the flip‐flops in the state machine implementing the control unit
...
If the input signal changes at an arbitrary
time independently of the clock, we call it an asynchronous input
...
To simplify the design, we will assume that all inputs
are synchronized with the clock and change state in response to an edge transition
...
For example, if Fig
...
6 were
a conventional flowchart, then the operations listed would be considered to follow one
after another in sequence: First register A is incremented, and only then is E evaluated
...
Otherwise (if E = 0),
the next step is to evaluate F and go to state S_1 or S_2
...
All the register operations that are specified within

370

Chapter 8

Design at the Register Transfer Level
Positive edge of Clock
Clock

Present state
( S_0 )

Next state
(S_1 or S_2 or S_3)

FIGURE 8
...
This sequence of events is presented
pictorially in Fig
...
8
...
An asserted asynchronous reset signal (reset_b) transfers the control circuit into
state S_0
...
If reset_b is not asserted, the following operations occur
simultaneously at the next positive edge of the clock:
1
...

2
...

3
...
8
...

Note that the two operations in the datapath and the change of state in the control logic
occur at the same time
...
8
...
Conversely, the chart in Fig
...
6(b) indicates the
control signals, but not the datapath operations
...


ASMD Chart
Algorithmic state machine and datapath (ASMD) charts were developed to clarify the
information displayed by ASM charts and to provide an effective tool for designing a
control unit for a given datapath unit
...
Thus, an ASMD chart associates register operations
with state transitions rather than with states; it also associates register operations with the
signals that cause them
...
There is no room for confusion about the timing of register
operations or about the signals that launch them
...


Section 8
...
Form an ASM chart showing only the states of the controller and the input signals2
that cause state transitions,
2
...
e
...
Modify the ASMD chart to identify the control signals that are generated by the
controller and that cause the indicated operations in the datapath unit
...

One important use of a state machine is to control register operations on a datapath
in a sequential machine that has been partitioned into a controller and a datapath
...
ASMD charts help clarify the design of a sequential machine by separating the
design of its datapath from the design of the controller, while maintaining a clear relationship between the two units
...
The
outputs generated by the controller are the signals that control the registers of the
datapath and cause the register operations annotated on the ASMD chart
...
5

DESIGN EXAMPLE (ASMD CHART)
We will now present a simple example demonstrating the use of the ASMD chart and
the register transfer representation
...

The datapath unit is to consist of two JK flip‐flops E and F, and one four‐bit binary
counter A[3: 0]
...
A signal, Start, initiates the system’s operation by clearing the counter A and flip‐flop F
...
Counter bits A2 and A3 determine
the sequence of operations:
If A2 = 0, E is cleared to 0 and the count continues
...

2

In general, the inputs to the control unit are external (primary) inputs and status signals that originate in
the datapath unit
...

A block diagram of the system’s architecture is shown in Fig
...
9(a), with (1) the
registers of the datapath unit, (2) the external (primary) input signals, (3) the status
signals fed back from the datapath unit to the control unit, and (4) the control signals
generated by the control unit and input to the datapath unit
...
For example, clr_A_F clears registers A and F
...
The internal
details of each unit are not shown
...
8
...
8
...
The chart shows the state transitions of the
controller and the datapath operations associated with those transitions
...

The nonblocking Verilog operator (6=) is shown instead of the arrow ( d ) for register
transfer operations because we will ultimately use the ASMD chart to write a Verilog
description of the system
...
This transition is shown for S_idle in the diagram, but all other synchronous reset paths are omitted for clarity
...
When that happens (i
...
, Start = 1), the state moves to S_1
...
From S_2, it moves unconditionally to S_idle, where it
awaits another assertion of Start
...
e
...
g
...
With Start asserted in S_idle,
the state will transition to S_1 and the registers A and F will be cleared
...

For example, register A is incremented at every clock edge that occurs while the
machine is in the state S_1
...
The signal controlling the
operation will be a Mealy‐type signal asserted when the system is in state S_1 and
A2 has the value 1
...

In addition to showing that the counter is incremented in state S_1, the annotated
paths show that other operations occur conditionally with the same clock edge:
Either E is cleared and control stays in state S_1 (A2 = 0) or
E is set and control stays in state S_1 (A2A3 = 10) or
E is set and control goes to state S_2 (A2A3 = 11)
...
5

Design Example (ASMD Chart)

373

Status signals
A3
A2
Datapath

clr_E
set_E
set_F
clr_A_F
incr_A

Controller

Start

A
E
F

reset_b
clock
(a)

Note: A3 denotes A[3],
A2 denotes A[2],
Ͻϭ denotes nonblocking assignment
reset_b denotes active-low reset condition

reset_b

S_idle
S_idle

reset_b

Start

A Ͻϭ 0
F Ͻϭ 0

reset_b

1

S_idle
1
A Ͻϭ 0
F Ͻϭ 0

A Ͻϭ 0
F Ͻϭ 0

Start

Start

E Ͻϭ 0

1

E Ͻϭ 0

S_1
incr_A

clr_E

1
A2

S_1

S_1

A Ͻϭ A ϩ 1

A Ͻϭ A ϩ 1

A Ͻϭ A ϩ 1

E Ͻϭ 1
1

set_E

1

A3

1

E Ͻϭ 1

A2

A2
E Ͻϭ 1

clr_A_F
E Ͻϭ 0

A3

1
S_2
(b)

F Ͻϭ 1

A3
1

1
S_2

(c)

F Ͻϭ 1

F Ͻϭ 1

S_2
set_F
(d)

FIGURE 8
...

The third and final step in creating the ASMD chart is to insert conditional boxes for
the signals generated by the controller or to insert Moore‐type signals in the state boxes,
as shown in Fig
...
9(d)
...
The ASM chart has three states
and three blocks
...
The block associated with S_2 consists of only the state
box
...

In this example, we have shown how a verbal (text) description (specification) of a
design is translated into an ASMD chart that completely describes the controller for the
datapath, indicating the control signals and their associated register operations
...
However, once the
ASMD chart is established, the procedure for designing the circuit is straightforward
...
We will
first design the system manually and then write the HDL description, keeping synthesis
as an optional step for those who have access to synthesis tools
...
The control signals specified within the
state and conditional boxes in the block are formed while the controller is in the indicated state, and the annotated operations occur in the datapath unit when the state
makes a transition along an edge that exits the state
...
In order to appreciate the timing relationship
involved, we will list the step‐by‐step sequence of operations after each clock edge,
beginning with an assertion of the signal Start until the system returns to the reset (initial) state, S_idle
...
3 shows the binary values of the counter and the two flip‐flops after every
clock pulse
...
We start with state S_1 right after the input signal Start has
caused the counter and flip‐flop F to be cleared
...

Therefore, the value of E is assumed to be 1, because E is set to 1 when the machine
enters S_2, before moving to S_idle (as shown at the bottom of the table), and because
E does not change during the transition from S_idle to S_1
...
Each pulse increments the counter and either clears or
sets E
...
5

Design Example (ASMD Chart)

375

Table 8
...
When A = (A3 A2 A1 A0) 0011, the next (4th) clock pulse increments
the counter to 0100, but that same clock edge sees the value of A2 as 0, so E remains
cleared
...
Similarly, E is cleared to 0 not when
the count goes from 0111 to 1000, but when it goes from 1000 to 1001, which is when
A2 is 0 in the present value of the counter
...
The next clock edge
increments A by 1, sets E to 1, and transfers control to state S_2
...
The clock edge associated with the path leaving S_2 sets flip‐
flop F to 1 and transfers control to state S_idle
...

From an observation of Table 8
...
This is the difference between an ASMD chart and a
conventional flowchart
...
8
...
The operations that are performed in the digital hardware, as specified
by a block in the ASMD chart, occur during the same clock cycle and not in a sequence
of operations following each other in time, as is the usual interpretation in a conventional flowchart
...
This is
because the decision box for E belongs with the same block as state S_1
...
The next clock edge executes
all the operations in the registers and flip‐flops, including the flip‐flops in the controller
that determine the next state, using the present values of the output signals of the
controller
...


Controller and Datapath Hardware Design
The ASMD chart provides all the information needed to design the digital system — the
datapath and the controller
...
The requirements for the design of the datapath are indicated by the
control signals inside the state and conditional boxes of the ASMD chart and are specified by the annotations of the edges indicating datapath operations
...
The hardware
configuration of the datapath and controller is shown in Fig
...
10
...
The status
signals provide information about the present condition of the datapath
...
The
outputs of the controller are inputs to the datapath and determine which operations will
be executed when the clock undergoes a transition
...

The control subsystem is shown in Fig
...
10 with only its inputs and outputs, with
names matching those of the ASMD chart
...
The datapath unit consists of a four‐bit binary counter and two
JK flip‐flops
...
6
...
The counter is incremented with every clock pulse when the controller state is S_1
...
The logic for the signal clr_A_F will be
included in the controller and requires an AND gate to guarantee that both conditions
are present
...
Depending on whether the controller is in state S_1 and whether
A2 is asserted, set_F controls flip‐flop F and is asserted unconditionally during state S_2
...


Section 8
...
10
Datapath and controller for design example

Register Transfer Representation
A digital system is represented at the register transfer level by specifying the registers
in the system, the operations performed, and the control sequence
...
It is convenient to
separate the control logic from the register operations of the datapath
...
The control information and register transfer operations can also be represented
separately, as shown in Fig
...
11
...
11
Register transfer‐level description of design example

Section 8
...
The state transition and the signal controlling the register operation are
shown with the operation
...
8
...
Only the ASMD chart is really
needed, but the state diagram for the controller is an alternative representation that is
useful in manual design
...
The state names are specified in each state box
...
The directed lines between
states and the condition associated with each follow the same path as in the ASMD
chart
...
They are taken from the state boxes or the annotated edges of the
ASMD chart
...
First, we must assign binary values to each state in the
ASMD chart
...
A chart with 3 or 4 states requires a sequential circuit with
two flip‐flops
...
Each combination
of flip‐flop values represents a binary number for one of the states
...
In most cases, there are many don’t‐care input conditions

Section 8
...
4
State Table for the Controller of Fig
...
10
Present
State

Next
State

Present‐State
Symbol

G1

G0

Start

A2

A3

G1

G0

clr_E

set_F

clr_A_F

incr_A

Outputs
set_E

Inputs

S_idle
S_idle
S_1
S_1
S_1
S_2

0
0
0
0
0
1

0
0
1
1
1
1

0
1
X
X
X
X

X
X
0
1
1
X

X
X
X
0
1
X

0
0
0
0
1
0

0
1
1
1
1
0

0
0
0
1
1
0

0
0
1
0
0
0

0
0
0
0
0
1

0
1
0
0
0
0

0
0
1
1
1
0

that must be included, so it is advisable to arrange the state table to take those conditions
into consideration
...
Binary state 10 is not used and will be treated as a don’t‐care
condition
...
4
...
There are three inputs and five
outputs
...
The outputs
depend on the inputs and the present state of the control
...
Initial state 00 goes to state 01 or stays
in 00, depending on the value of input Start
...
While the system is
in binary state 00 with Start = 1, the control unit provides an output labeled clr_A_F to
initiate the required register operations
...
The system goes to binary state 11 only if A2 A3 = 11; otherwise, it
remains in binary state 01
...


Control Logic
The procedure for designing a sequential circuit starting from a state table was presented in Chapter 5
...
4, we need to use five‐
variable maps to simplify the input equations
...
Instead of using maps
to simplify the input equations, we can obtain them directly from the state table by
inspection
...
From Table 8
...
The D input of flip‐flop G1 must

380

Chapter 8

Design at the Register Transfer Level

be equal to 1 during present state S_1 when both inputs A2 and A3 are equal to 1
...
8
...
8
...
Note that although we derived the output equations from Table 8
...
8
...
This simple example illustrates the

w1
Start

G0

D

clr_A_F

C

incr_A
set_E

w2
A3
A2

G1

D

set_F

w3
C

clock
reset_b

FIGURE 8
...
8
...
6

HDL Description of Design Example

381

manual design of a controller for a datapath, using an ASMD chart as a starting point
...


8
...
We are now in a position to incorporate these components into the description
of a specific design
...
Behavioral descriptions may be classified as being either
at the register transfer level or at an abstract algorithmic level
...

The structural description is the lowest and most detailed level
...
The various
components may include gates, flip‐flops, and standard circuits such as multiplexers and
counters
...
A top‐level module combines the entire system by instantiating all the lower level modules
...

The RTL description specifies the digital system in terms of the registers, the operations performed, and the control that sequences the operations
...
The RTL description implies a certain hardware configuration among
the registers, allowing the designer to create a design that can be synthesized automatically, rather than manually, into standard digital components
...
It does not provide any detail on how the design is to be implemented with
hardware
...
Descriptions
at this level are accessible to nontechnical users who understand programming languages
...

We will now illustrate the RTL and structural descriptions by using the design example of the previous section
...
(An algorithmic‐based description is illustrated in Section 8
...
)

RTL Description
The block diagram in Fig
...
10 describes the design example
...
The former option simply ignores the boundaries between the functional
units; the modules in the latter option establish the boundaries shown in Fig
...
9(a) and
Fig
...
10
...
This choice also allows one to easily
substitute alternative controllers for a given datapath (e
...
, replace an RTL model by
a structural model)
...
2
...
8
...
e
...
Likewise, our description has
three modules: Design_Example_RTL, Controller_RTL, and Datapath_RTL
...
8
...

Design_Example_RTL declares the input and output ports of the module and instantiates Controller_RTL and Datapath_RTL
...
Failure to do so will produce port mismatch errors
when the descriptions are compiled together
...
The primary (external) inputs to
the controller are Start, clock (to synchronize the system), and reset_b
...
Without
that signal, the controller could not be placed in a known initial state
...
An edge‐sensitive
behavior updates the state at the positive edge of the clock, depending on whether a
reset condition is asserted
...
Notice that the description includes default assignments to all of the outputs
(e
...
, set_E = 0)
...
e
...
The approach also ensures that every path through the assignment logic assigns
a value to every variable
...
Synthesis tools will
provide the latch, wasting silicon area
...
Only three of the possible two‐bit patterns are used, so the case statement
for the next‐state logic includes a default assignment to handle the possibility that one
of the three assigned codes is not detected
...
Also, the first statement of the next‐state logic assigns next_state = S_idle to guarantee that the next state
is assigned in every thread of the logic
...

The description of Datapath_RTL is written by testing for an assertion of each
control signal from Controller_RTL
...
6

HDL Description of Design Example

383

the ASMD chart (Fig
...
9(d))
...
This ensures that the register operations and state transitions are concurrent, a feature that is especially crucial during
control state S_1
...
To
accomplish a valid synchronous design, it is necessary to ensure that A[2] is checked
before A is incremented
...
However, by using nonblocking assignments, we accomplish the required synchronization
without being concerned about the order in which the statements are listed
...

The cyclic behaviors of the controller and the datapath interact in a chain reaction:
At the active edge of the clock, the state and datapath registers are updated
...
The updated values
are used at the next active edge of the clock to determine the state transition and the
updates of the datapath
...
8
...
8
...
8
...
In contrast, an
RTL model describes the state transitions of the controller and the operations of the
datapath as a step toward automatically synthesizing the circuit that implements them
...


HDL Example 8
...
8
...
8
...
8
...
8
...
8
...
6

HDL Description of Design Example

385

Testing the Design Description
The sequence of operations for the design example was investigated in the previous
section
...
3 shows the values of E and F while register A is incremented
...
The test bench in HDL Example 8
...
(The procedure
for writing test benches is explained in Section 4
...
) The test module generates signals
for Start, clock, and reset_b, and checks the results obtained from registers A, E, and F
...
At time t = 5, the reset_b signal is de‐asserted by setting it to 1, the Start input
is asserted by setting it to 1, and the clock is then repeated for 16 cycles
...
The output of the simulation is
listed in the example under the simulation log
...
The first positive clock
transition, at time = 10, clears A and F, but does not affect E, so E is unknown at this
time
...
3
...
This occurs during the second transition, from S_idle
to S_1
...
3
// Test bench for design example
'timescale 1 ns / 1 ps
module t_Design_Example_RTL;
reg
Start, clock, reset_b;
wire [3: 0] A;
wire
E, F;
// Instantiate design example
Design_Example_RTL M0 (A, E, F, Start, clock, reset_b);
// Describe stimulus waveforms
initial #500 $finish;
// Stopwatch
initial
begin
reset_b = 0;
Start = 0;
clock = 0;
#5 reset_b = 1; Start = 1;
repeat (32)
begin
#5 clock = ~ clock;
// Clock generator
end

386

Chapter 8

Design at the Register Transfer Level
end
initial
$monitor ("A = %b E = %b F = %b time = %0d", A, E, F, $time);
endmodule
Simulation log:
A = xxxx E = x F = x time = 0
A = 0000 E = x F = 0 time = 10
A = 0001 E = 0 F = 0 time = 20
A = 0010 E = 0 F = 0 time = 30
A = 0011 E = 0 F = 0 time = 40
A = 0100 E = 0 F = 0 time = 50
A = 0101 E = 1 F = 0 time = 60
A = 0110 E = 1 F = 0 time = 70
A = 0111 E = 1 F = 0 time = 80
A = 1000 E = 1 F = 0 time = 90
A = 1001 E = 0 F = 0 time = 100
A = 1010 E = 0 F = 0 time = 110
A = 1011 E = 0 F = 0 time = 120
A = 1100 E = 0 F = 0 time = 130
A = 1101 E = 1 F = 0 time = 140
A = 1101 E = 1 F = 1 time = 150
A = 0000 E = 1 F = 0 time = 160

Waveforms produced by a simulation of Design_Example_RTL with the test bench
are shown in Fig
...
13
...
The results
are annotated to call attention to the relationship between a control signal and the
operation that it causes to execute
...
Likewise, set_F asserts during
the clock cycle before the edge at which F is set to 1
...
A more thorough verification of Design_Example_
RTL would confirm that the machine recovers from a reset on the fly (i
...
, a reset that
is asserted randomly after the machine is operating)
...
It is strongly recommended that the state always be displayed, because this information is essential for verifying that the machine is operating correctly and for debugging
its description when it is not
...


Structural Description
The RTL description of a design consists of procedural statements that determine the
functional behavior of the digital circuit
...
6
0

Name

HDL Description of Design Example

50

100

387

150

clock
reset_b
Start
A2
A3
state[1: 0]

0

1

3

0

1

clr_A_F
set_E
clr_E
set_F
incr_A
A[3: 0]
E
F

x

0

1

2

3

4

5

6

7

8

9

a

b

c

d

0

FIGURE 8
...
It is also possible to describe the design by its structure rather than its
function
...
In this regard, a structural
description is equivalent to a schematic diagram or a block diagram of the circuit
...

For convenience, the circuit is again decomposed into two parts: the controller and
the datapath
...
8
...
8
...

The structure of the datapath is evident in Fig
...
10 and consists of the flip‐flops and the
four‐bit counter with synchronous clear
...
The descriptions of Controller_STR
and Datapath_STR will be structural
...
4 presents the structural description of the design example
...

For simplicity, the counter and flip‐flops are described by RTL models
...
8
...
The port list is identical to the list used in the
RTL description
...

The control module describes the circuit of Fig
...
12
...
G1 and G0 cannot be declared as reg data
type because they are outputs of an instantiated D flip‐flop
...
e
...
The name of a variable is local to the module or
procedural block in which it is declared
...
g
...
end)
...
g
...
e
...
The instantiated gates
specify the combinational part of the circuit
...
The outputs of the flip‐flops G1 and G0 and the input equations
DG1 and DG0 replace output Q and input D in the instantiated flip‐flops
...
The structure of the datapath unit has direct
inputs to the JK flip‐flops
...
8
...
10, and 8
...


HDL Example 8
...
8
...
12)
module Design_Example_STR
( output
[3: 0]
A,
// V 2001 port syntax
output
E, F,
input
Start, clock, reset_b
);
Controller_STR M0 (clr_A_F, set_E, clr_E, set_F, incr_A, Start, A[2], A[3], clock,
reset_b );
Datapath_STR M1 (A, E, F, clr_A_F, set_E, clr_E, set_F, incr_A, clock);
endmodule
module Controller_STR
( output clr_A_F, set_E, clr_E, set_F, incr_A,
input Start, A2, A3, clock, reset_b
);
wire
parameter
wire

G0, G1;
S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11;
w1, w2, w3;

Section 8
...
8
...
The only change necessary is the replacement
of the instantiation of the example from Design_Example_RTL by Design_Example_STR
...
However, a comparison of the two descriptions indicates that the RTL style is easier

Section 8
...


8
...
It presents a hardware algorithm for
binary multiplication, proposes the register configuration for its implementation, and
then shows how to use an ASMD chart to design its datapath and its controller
...
The hardware
developed in Section 4
...
In contrast, in this section, a more efficient hardware algorithm results
in a sequential multiplier that uses only one adder and a shift register
...
A parallel adder uses more hardware, but forms its result in one cycle of the
clock; a sequential adder uses less hardware, but takes multiple clock cycles to form its
result
...
e
...
The process is best illustrated with a numerical
example
...

Successive bits of the multiplier are examined, least significant bit first
...
The
numbers copied in successive lines are shifted one position to the left from the previous number
...
The
product obtained from the multiplication of two binary numbers of n bits each can
have up to 2n bits
...

When the multiplication process is implemented with digital hardware, it is convenient to change the process slightly
...
A choice to form the

392

Chapter 8

Design at the Register Transfer Level

product in the time span of a single clock cycle will synthesize the circuit of a parallel
multiplier like the one discussed in Section 4
...
On the other hand, an RTL model of
the algorithm adds shifted copies of the multiplicand to an accumulated partial product
...
Among the many possibilities for distributing the effort of
multiplication over multiple clock cycles, we will consider that in which only one partial product is formed and accumulated in a single cycle of the clock
...
) Instead of providing digital circuits to store and add simultaneously as
many binary numbers as there are 1’s in the multiplier, it is less expensive to provide
only the hardware needed to sum two binary numbers and accumulate the partial
products in a register
...
This leaves the partial product and
the multiplicand in the required relative positions
...


Register Configuration
A block diagram for the sequential binary multiplier is shown in Fig
...
14(a), and the
register configuration of the datapath is shown in Fig
...
14(b)
...
A parallel adder adds the contents of
register B to register A
...
The counter
P is initially set to hold a binary number equal to the number of bits in the multiplier
...
When the
content of the counter reaches zero, the product is formed in the double register A
and Q, and the process stops
...
The system then performs the multiplication
...
The output
carry from the addition, whether 0 or 1, is transferred to C
...
The least significant bit of A is
shifted into the most significant position of Q, the carry from C is shifted into the most
significant position of A, and 0 is shifted into C
...
In this manner, the least significant bit of register Q, designated by Q[0], holds the bit of the multiplier that must be inspected next
...
The control logic
also receives a signal, Zero, from a circuit that checks counter P for zero
...
The input signal Start is an external control
input
...


Section 8
...
14
(a) Block diagram and (b) datapath of a binary multiplier

The interface between the controller and the datapath consists of the status signals
and the output signals of the controller
...
Signal Load_regs loads the internal registers of the
datapath, Shift_regs causes the shift register to shift, Add_regs forms the sum of the
multiplicand and register A, and Decr_P decrements the counter
...
The contents of the register holding the product vary during execution, so it is
useful to have a signal indicating that its contents are valid
...
Only
the signals needed to control the datapath are included in the interface
...
Not good
...
8
...
The intermediate form
in Fig
...
15(a) annotates the ASM chart of the controller with the register operations,
and the completed chart in Fig
...
15(b) identifies the Moore and Mealy outputs of the
controller
...
As long as the circuit
is in the initial state and Start = 0, no action occurs and the system remains in state S_idle
with Ready asserted
...
Then, (1) control goes to state S_add, (2) register A and carry flip‐flop C are cleared to 0, (3) registers

reset_b

S_idle
Ready

reset_b

A Ͻϭ 0
C Ͻϭ 0
B Ͻϭ Multiplicand
Q Ͻϭ Multiplier
P Ͻϭ n

Start

S_idle

1
A Ͻϭ 0
C Ͻϭ 0
B Ͻϭ Multiplicand
Q Ͻϭ Multiplier
P Ͻϭ n

Start
1

S_add

Q[0]

Load_regs
P Ͻϭ PϪ1
S_add
Decr_P
{C, A} Ͻϭ A ϩ B

P Ͻϭ PϪ1 Decrement counter

1

{C, A} Ͻϭ A ϩ B
Add multiplicand
to shifted sum

Q[0]

1
Add_regs

S_shift
Shift_regs
S_shift

Zero

{C, A, Q} Ͻϭ {C, A, Q} ϾϾ 1
17-bit register shifts to the
right by one bit

{C, A, Q} Ͻϭ {C, A, Q} ϾϾ 1
Zero
1

1

(b)

(a)

FIGURE 8
...
7

Sequential Binary Multiplier

395

B and Q are loaded with the multiplicand and the multiplier, respectively, and (4) the
sequence counter P is set to a binary number n, equal to the number of bits in the multiplier
...
The carry from the addition is
transferred to C
...
The counter P is decremented by 1 regardless of the value of Q[0], so Decr_P is formed in state
S_add as a Moore output of the controller
...
Registers C, A, and Q are combined into one composite register CAQ, denoted by the
concatenation {C, A, Q}, and its contents are shifted once to the right to obtain a new
partial product
...
It is equivalent to the following statement in register
transfer notation:
Shift right CAQ, C d 0
In terms of individual register symbols, the shift operation can be described by the following register operations:
A d shr A, An - 1 d C
Q d shr Q, Qn - 1 d A0
Cd0
Both registers A and Q are shifted right
...
The leftmost bit of Q, Qn - 1, receives the bit from the rightmost
position of A in A0, and C is reset to 0
...

The value in counter P is checked after the formation of each partial product
...
The process stops when the counter reaches 0
and the controller’s status input Zero is equal to 1
...
The final
product is available in A and Q, with A holding the most significant bits and Q the least
significant bits of the product
...
5 to clarify the multiplication
process
...
The data shown
in the table can be compared with simulation results
...
Register A is a shift register with parallel
load to accept the sum from the adder and must have a synchronous clear capability to
reset the register to 0
...
The counter P is a binary down counter with a facility to parallel load a binary constant
...
Registers B and Q need a parallel
load capability in order to receive the multiplicand and multiplier prior to the start of the
multiplication process
...
5
Numerical Example For Binary Multiplier
Multiplicand B = 101112 = 17H = 2310

Multiplier Q = 100112 = 13H = 1910
C

Multiplier in Q
Q0 = 1; add B
First partial product
Shift right CAQ
Q0 = 1; add B
Second partial product
Shift right CAQ
Q0 = 0; shift right CAQ
Q0 = 0; shift right CAQ
Q0 = 1; add B
Fifth partial product
Shift right CAQ
Final product in AQ = 01101101012 = 1b5H

8
...
The control logic is a finite state machine; its Mealy‐ and Moore‐type outputs
control the operations of the datapath
...
The design of the system can be synthesized from an RTL description
derived from the ASMD chart
...
The information needed to form the state diagram of the controller is already contained in the
ASMD chart, since the rectangular blocks that designate state boxes are the states
of the sequential circuit
...

As an example, the control state diagram for the binary multiplier developed in the
previous section is shown in Fig
...
16(a)
...
8
...
The three states S_idle through S_shift are taken from
the rectangular state boxes
...
The register transfer operations for each of the three states are
listed in Fig
...
16(b) and are taken from the corresponding state and conditional boxes
in the ASMD chart
...


Section 8
...
16
Control specifications for binary multiplier

We must execute two steps when implementing the control logic: (1) establish the
required sequence of states, and (2) provide signals to control the register operations
...
The signals
for controlling the operations in the registers are specified in the register transfer statements annotated on the ASMD chart or listed in tabular format
...
The block diagram of the control
unit is shown in Fig
...
14(a)
...
We note that Q[0] affects only the output of the controller, not its state
transitions
...

An important step in the design is the assignment of coded binary values to the states
...
6
...
A state assignment often used in control design is
the one‐hot assignment
...
At any given time, only one bit is equal to 1 (the one that is hot)

398

Chapter 8

Design at the Register Transfer Level
Table 8
...
This type of assignment uses a flip‐flop for each
state
...

Because the decoding logic does not become more complex as states are added to the
machine, the speed at which the machine can operate is not limited by the time required
to decode the state
...
However, in most cases this method is difficult to
carry out manually because of the large number of states and inputs that a typical control
circuit may have
...

We will now present two such design procedures
...
The method will be presented for a small circuit,
but it applies to larger circuits as well
...


Sequence Register and Decoder
The sequence‐register‐and‐decoder (manual) method, as the name implies, uses a register for the control states and a decoder to provide an output corresponding to each of
the states
...
) A register with n flip‐
flops can have up to 2n states, and an n‐to‐2n‐line decoder has up to 2n outputs
...

The ASMD chart and the state diagram for the controller of the binary multiplier
have three states and two inputs
...
) To implement the
design with a sequence register and decoder, we need two flip‐flops for the register and
a two‐to‐four‐line decoder
...
The Mealy‐type outputs will be formed from the Moore outputs
and the inputs
...
7
...
8
...
 8
...
We designate the two flip‐flops as G1 and G0 and assign the binary states
00, 01, and 10 to S_idle, S_add, and S_shift, respectively
...
8

Control Logic

399

Table 8
...
The outputs of the control circuit are designated by the names given in the ASMD
chart
...
Those output variables
are shaded in Table 8
...
Thus, when the present state is G1G0 = 00, output Ready must
be equal to 1, while the other outputs remain at 0
...
8
...

The state machine of the controller can be designed from the state table by means of
the classical procedure presented in Chapter 5
...
In most control logic
applications, the number of states and inputs is much larger
...
The design can be simplified if we take
into consideration the fact that the decoder outputs are available for use in the design
...
Moreover, instead of
using maps to simplify the flip‐flop equations, we can obtain them directly by inspection of
the state table
...
These conditions can be specified by the equation
DG1 = T1
where DG1 is the D input of flip‐flop G1
...
17
Logic diagram of control for binary multiplier using a sequence register and decoder

400

Section 8
...
(Synthesis tools
take care of this detail automatically
...

The logic diagram of the control circuit is drawn in Fig
...
17(b)
...
The outputs of the decoder are used to
generate the inputs to the next‐state logic as well as the control outputs
...


One‐Hot Design (One Flip‐Flop per State)
Another method of control logic design is the one‐hot assignment, which results in a
sequential circuit with one flip‐flop per state
...
The single 1 propagates from one flip‐flop to another
under the control of decision logic
...

This method uses the maximum number of flip‐flops for the sequential circuit
...
By
contrast, with the method of one flip‐flop per state, the circuit requires 12 flip‐flops, one
for each state
...
But the method offers some advantages that may not be
apparent
...
No state or excitation tables are
needed if D‐type flip‐flops are employed
...

The design procedure for a one‐hot state assignment will be demonstrated by obtaining
the control circuit specified by the state diagram of Fig
...
16(a)
...
The input equations for setting
each flip‐flop to 1 are determined from the present state and the input conditions along
the corresponding directed lines going into the state
...
These conditions are specified by the input equation:
DG0 = G0 StartЈ + G2 Zero
In fact, the condition for setting a flip‐flop to 1 is obtained directly from the state diagram, from the condition specified in the directed lines going into the corresponding
flip‐flop state ANDed with the previous flip‐flop state
...
Using this procedure for the other
three flip‐flops, we obtain the remaining input equations:
DG1 = G0 Start + G2 ZeroЈ
DG2 = G1

402

Chapter 8

Design at the Register Transfer Level

Ready
Start

D Set
(S_idle)

Load_regs
G0

C
Q[0]

Zero

D
(S_add)
C

G1

Add_regs
Decr_P

Rst

D
(S_shift) G2
C
clock

Shift_regs

Rst

reset_b

FIGURE 8
...
 8
...
The circuit consists of three D flip‐flops labeled G0 through G2, together with the
associated gates specified by the input equations
...
This can be done by using an asynchronous preset on flip‐flop G0 and an asynchronous clear for the other flip‐flops
...
Only one flip‐flop will be
set to 1 with each clock edge; all others are reset to 0, because their D inputs are equal to 0
...
9

H D L D E S C R I P T I O N O F B I N A RY M U LT I P L I E R
A second example of an HDL description of an RTL design is given in HDL Example 8
...
7 For simplicity, the entire description is “flat
...
Comments will identify the controller and the
datapath
...
9

HDL Description of Binary Multiplier

403

in the block diagram of Fig
...
14(a)
...
5
...
The second part of
the description declares all registers in the controller and the datapath, as well as the one‐
hot encoding of the states
...
The continuous assignments for Zero and Ready are accomplished by
assigning a Boolean expression to their wire declarations
...
Again, note that default assignments are made to next_state, Load_regs,
Decr_P, Add_regs, and Shift_regs
...
The state transitions and the output logic are written directly from the
ASMD chart of Fig
...
15(b)
...
3 (For clarity, separate cyclic behaviors are used; we do not mix the
description of the datapath with the description of the controller
...
The addition and subtraction
operations will be implemented in hardware by combinational logic
...

Because the controller and datapath have been partitioned into separate units, the control signals completely specify the behavior of the datapath; explicit information about
the state of the controller is not needed and is not made available to the datapath unit
...
The default case item and the default
assignments preceding the case statement ensure that the machine will recover if it
somehow enters an unused state
...

(Remember, a synthesis tool will synthesize latches when what was intended to be combinational logic in fact fails to completely specify the input–output function of the logic
...
5 (Sequential Multiplier)
module Sequential_Binary_Multiplier (Product, Ready, Multiplicand, Multiplier, Start,
clock, reset_b);
// Default configuration: five-bit datapath
parameter
dp_width = 5;
// Set to width of datapath
output
[2*dp_width -1: 0]
Product;
output
Ready;
input
[dp_width -1: 0]
Multiplicand, Multiplier;
input
Start, clock, reset_b;

3

The width of the datapath here is dp‐width
...
9

HDL Description of Binary Multiplier

405

if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1;
if (Decr_P) P <= P -1;
end
endmodule

Testing the Multiplier
HDL Example 8
...
The inputs and outputs
are the same as those shown in the block diagram of Fig
...
14(a)
...
A more strategic approach to testing and
verification exploits the partition of the design into its datapath and control unit
...
A separate
test bench can be developed to verify that the datapath executes each operation and
generates status signals correctly
...
A separate test
bench can verify that the control unit exhibits the complete functionality specified by
the ASMD chart (i
...
, that it makes the correct state transitions and asserts its outputs
in response to the external inputs and the status signals)
...
The final step in the design process is to integrate
the verified models within a parent module and verify the functionality of the overall
machine
...
For example, a mismatch in the
listed order of signals may not be detected by the compiler
...
In practice, this requires writing a comprehensive
test plan identifying that functionality
...

The exercise to write a test plan is not academic: The quality and scope of the test plan
determine the worth of the verification effort
...

Testing and verifying an HDL model usually requires access to more information
than the inputs and outputs of the machine
...
Fortunately, Verilog provides a mechanism to hierarchically de‐reference identifiers so that any variable at any level of the design hierarchy
can be visible to the test bench
...
Simulators use this mechanism to
display waveforms of any variable in the design hierarchy
...
For example, the register P within

406

Chapter 8

Design at the Register Transfer Level

the datapath unit is not an output port of the multiplier, but it can be referenced as
M0
...
The hierarchical path name consists of the sequence of module identifiers or
block names, separated by periods and specifying the location of the variable in the
design hierarchy
...

The first test bench in HDL Example 8
...
This task is similar to the $display and $monitor tasks
explained in Section 4
...
The $strobe system task provides a synchronization mechanism to ensure that data are displayed only after all assignments in a given time step are
executed
...
When the system is synchronized to the positive edge of the clock, using
$strobe after the always @ (posedge clock) statement ensures that the display shows
values of the signal after the clock pulse
...
6 instantiates the module Sequential Binary_Multiplier of HDL Example 8
...
Both modules
must be included as source files when simulating the multiplier with a Verilog HDL
simulator
...
5
...
Waveforms for a sample
of simulation results are shown in Fig
...
19
...
Insight can
be gained by studying the displayed waveforms of the control state, the control signals,
the status signals, and the register operations
...
In this example,
1910 * 2310 = 43710, and 17H + 0bH = 02H with C = 1
...

HDL Example 8
...
9

HDL Description of Binary Multiplier

65885

Name

65925

65965

407
66005

clock
reset_b
Start
state[2: 0]

4

1

2

4

2

4

2

4

2

4

2

4

1

2

Load_regs
Decr_P
Add_regs
Shift_regs
P[2: 0]

0

5

4

3

2

1

5

0

Zero
B[4: 0]

17

16

A[4: 0]

0d

00

17

0b

02

18

11

08

0c

04

16

1b

0d

00

15

13

C
Q[4: 0]

02

13

19

0b

Multiplicand[4: 0]

16

17

18

Multiplicand[4: 0]

22

23

24

Multiplier[4: 0]

13

Multiplier[4: 0]

19

Product[9: 0]

1a2

013

2j3

179

059

22c

11b

08b

36b

1b5

013

Product[9: 0]

418

19

755

377

89

556

278

139

875

437

19

Ready

FIGURE 8
...
5
always @ (posedge clock)
$strobe ("C=%b A=%b Q=%b P=%b time=%0d",M0
...
A,M0
...
P, $time);
endmodule
Simulation log:
C=0 A=00000 Q=10011 P=101 time=5
C=0 A=10111 Q=10011 P=100 time=15
C=0 A=01011 Q=11001 P=100 time=25
C=1 A=00010 Q=11001 P=011 time=35
C=0 A=10001 Q=01100 P=011 time=45
C=0 A=10001 Q=01100 P=010 time=55
C=0 A=01000 Q=10110 P=010 time=65
C=0 A=01000 Q=10110 P=001 time=75
C=0 A=00100 Q=01011 P=001 time=85
C=0 A=11011 Q=01011 P=000 time=95
C=0 A=01101 Q=10101 P=000 time=105
C=0 A=01101 Q=10101 P=000 time=115
C=0 A=01101 Q=10101 P=000 time=125
/* Test bench for exhaustive simulation
module t_Sequential_Binary_Multiplier;
parameter
dp_width = 5;
// Width of datapath
wire
[2 * dp_width -1: 0] Product;
wire
Ready;
reg
[dp_width -1: 0]
Multiplicand, Multiplier;
reg
Start, clock, reset_b;
Sequential_Binary_Multiplier M0 (Product, Ready, Multiplicand, Multiplier, Start, clock,
reset_b);
initial #1030000 $finish;
initial begin clock = 0; #5 forever #5 clock = ~clock; end
initial fork
reset_b = 1;
#2 reset_b = 0;
#3 reset_b = 1;
join

Section 8
...
Ready) 5 Multiplicand = Multiplicand + 1;
end
end
endmodule
*/

Behavioral Description of a Parallel Multiplier
Structural modeling implicitly specifies the functionality of a digital machine by prescribing an interconnection of gate‐level hardware units
...
g
...
Hardware design at this level often
requires cleverness and accrued experience
...
In contrast, behavioral RTL modeling specifies functionality abstractly, in terms
of HDL operators
...
RTL modeling implicitly schedules operations by
explicitly assigning them to clock cycles
...
Thus, algorithmic modeling allows a designer to
explore trade‐offs in the space (hardware) and time domains, trading processing speed
for hardware complexity
...
7 presents an RTL model and an algorithmic model of a binary
multiplier
...
The RTL model expresses the
functionality of a multiplier in a single statement
...
7
...
The time required to form the product will depend on the propagation
delays of the gates available in the library of standard cells used by the synthesis tool
...
A synthesis tool will
unroll the loop of the algorithm and infer the need for a gate‐level circuit equivalent to
that shown in Section 4
...

Be aware that a synthesis tool may not be able to synthesize a given algorithmic
description, even though the associated HDL model will simulate and produce correct
results
...
It then becomes necessary to distribute the operations over multiple clock cycles
...
7
// Behavioral (RTL) description of a parallel multiplier (n = 8)
module Mult (Product, Multiplicand, Multiplier);
input [7: 0]
Multiplicand, Multiplier;
output reg [15: 0] Product;
always @ (Multiplicand, Multiplier)
Product = Multiplicand * Multiplier;
endmodule
module Algorithmic_Binary_Multiplier #(parameter dp_width = 5) (
output [2*dp_width -1: 0] Product, input [dp_width -1: 0] Multiplicand, Multiplier);
reg [dp_width -1: 0]
A, B, Q;
// Sized for datapath
reg
C;
integer
k;
assign
Product = {C, A, Q};
always @ (Multiplier, Multiplicand) begin
Q = Multiplier;
B = Multiplicand;
C = 0;
A = 0;
for (k = 0; k <= dp_width -1; k = k + 1) begin
if (Q[0]) {C, A} = A + B;
{C, A, Q} = {C, A, Q} >> 1;
end
end
endmodule
module t_Algorithmic_Binary_Multiplier;
parameter
dp_width = 5;
// Width of datapath
wire [2* dp_width -1: 0]
Product;
reg [dp_width -1: 0]
Multiplicand, Multiplier;
integer
Exp_Value;
reg
Error;
Algorithmic_Binary_Multiplier M0 (Product, Multiplicand, Multiplier);
// Error detection
initial # 1030000 finish;
always @ (Product) begin
Exp_Value = Multiplier * Multiplicand;
// Exp_Value = Multiplier * Multiplicand +1; // Inject error to confirm detection
Error = Exp_Value ^ Product;
end
// Generate multiplier and multiplicand exhaustively for 5 bit operands
initial begin
#5 Multiplicand = 0;
Multiplier = 0;

Section 8
...
In effect, a behavioral synthesis tool would have to allocate the registers and adders to implement multiplication
...
Behavioral synthesis tools require a different and more
sophisticated style of modeling and are not within the scope of this text
...
10

D E S I G N W I T H M U LT I P L E X E R S
The register‐and‐decoder scheme for the design of a controller has three parts: the
flip‐flops that hold the binary state value, the decoder that generates the control outputs,
and the gates that determine the next‐state and output signals
...
11, it was
shown that a combinational circuit can be implemented with multiplexers instead of
individual gates
...
The first level consists of multiplexers that determine the
next state of the register
...
The third level has a decoder that asserts a unique output line for each
control state
...

Consider, for example, the ASM chart of Fig
...
20, consisting of four states and four
control inputs
...

These signals are independent of the register operations of the datapath, so the edges of
the graph are not annotated with datapath register operations, and the graph does not
identify the output signals of the controller
...
The decision boxes specify the state
transitions as a function of the four control inputs: w, x, y, and z
...
8
...
The outputs of the state‐register
flip‐flops are applied to the decoder inputs and also to the select inputs of the multiplexers
...
The outputs of the multiplexers are then applied to the D inputs of G1 and
G0
...
The inputs of the multiplexers

412

Chapter 8

Design at the Register Transfer Level

00
S_0

0

w

1
01
S_1

0

x

1

11

10

S_3

S_2

0

0

z

y

1

1

1

1

z

y

0

0

FIGURE 8
...
For
example, state 00 stays at 00 or goes to 01, depending on the value of input w
...

The next state of G0 is 0 if w = 0 and 1 if w = 1
...
This means that when the select inputs of the
multiplexers are equal to present state 00, the outputs of the multiplexers provide the
binary value that is transferred to the register at the next clock pulse
...
10

0

0

1

1

y

Design with Multiplexers

413

G1

2

D
C

MUX1
y
zЈ

3
s1

s0

d0
2ϫ4
decoder

MUX select

d1
d2
d3

s1
w

1

G0

0

xЈ

s0

y
z

D
C

MUX2

2
yЈ

3

CLK

FIGURE 8
...
Table 8
...
8
...
There are two transitions from present
state 00 or 01 and three from present state 10 or 11
...
The input conditions listed in the table are
obtained from the decision boxes in the ASM chart
...
8
...

In the table, we mark these input conditions as x and xЈ, respectively
...
The multiplexer input for each present state is determined from
the input conditions when the next state of the flip‐flop is equal to 1
...
Therefore, the input of MUX1 is made equal to 1 and that of
MUX2 to xЈwhen the present state of the register is 01
...
When these two Boolean terms are ORed together and then simplified, we obtain
the single binary variable y, as indicated in the table
...
If the next state of G1 remains at 0 after a given
present state, we place a 0 in the multiplexer input, as shown in present state 00 for

414

Chapter 8

Design at the Register Transfer Level

Table 8
...
If the next state of G1 is always 1, we place a 1 in the multiplexer input, as
shown in present state 01 for MUX1
...
The multiplexer inputs from the table are then used in the
control implementation of Fig
...
21
...
Otherwise, the multiplexer input is equal to the control variable, the complement
of the control variable, 0, or 1
...
The example will also demonstrate the formulation of the ASMD chart and the
implementation of the datapath subsystem
...
(A more efficient implementation is considered
in the problems at the end of the chapter
...
For example, if the
binary number loaded into R1 is 10111001, the circuit counts the five 1’s in R1 and sets
register R2 to the binary count 101
...
The value in E is checked by the control, and each time it
is equal to 1, register R2 is incremented by 1
...
8
...
The
datapath contains registers R1, R2, and E, as well as logic to shift the leftmost bit of R1
into E
...


Shift_left

R1

Shift_left

Incr_R2

...
22
Block diagram and ASMD chart for count‐of‐ones circuit

415

416

Chapter 8

Design at the Register Transfer Level

detail is omitted in the figure)
...

The controller has status input signals E and Zero from the datapath
...
E is the output of the flip‐flop
...
The circuit produces an
output Zero = 1 when R1 is equal to 0 (i
...
, when R1 is empty of 1’s)
...
8
...
8
...
Asserting
Start with the controller in S_idle transfers the state to S_1, concurrently loads register R1 with the binary data word, and fills the cells of R2 with 1’s
...

Thus, the first transition from S_1 to S_2 will clear R2
...
The content of
R1, as indicated by Zero, will also be examined in S_1
...
In state S_1, Incr_R2 is asserted
to cause the datapath unit to increment R2 at each clock pulse
...
The number in R1 is shifted and its leftmost bit is transferred into E
...
For every 1 detected in E, register
R2 is incremented and register R1 is checked again for more 1’s
...
Note that the state box of S_3 has no
register operations, but the block associated with it contains the decision box for E
...
The register R1 in Fig
...
22(a) is a shift register
...
The multiplexer input conditions for the
control are determined from Table 8
...
The input conditions are obtained from the
ASMD chart for each possible binary state transition
...
9
Multiplexer Input Conditions for Design Example
Present
State

Next
State

G1

G0

G1

G0

0
0
0
0
1
1
1

0
0
1
1
0
1
1

0
0
0
1
1
1
0

0
1
0
0
1
0
1

Input
Conditions

Multiplexer
Inputs
MUX1

StartЈ
Start
Zero
ZeroЈ
None
EЈ
E

MUX2

0

Start

ZeroЈ
1

0
1

EЈ

E

Section 8
...
23
Control implementation for count‐of‐ones circuit

binary values 00 through 11
...

The transition from present state 01 depends on Zero, and the transition from present state 11 on E
...
The values
under MUX1 and MUX2 in the table are determined from the Boolean input conditions for the next state of G1 and G0, respectively
...
8
...
This is a
three‐level implementation, with the multiplexers in the first level
...
9
...
8
instantiates structural models of the controller and the datapath
...
Note that the datapath
unit does not have a reset signal to clear the registers, but the models for the flip‐flop,
shift register, and counter have an active‐low reset
...
Note also that the test bench uses hierarchical de‐referencing to access
the state of the controller to make the debug and verification tasks easier, without having to alter the module ports to provide access to the internal signals
...
The lower level
models are described behaviorally for simplicity
...
8 (Ones Counter)
module Count_Ones_STR_STR (count, Ready, data, Start, clock, reset_b);
// Mux – decoder implementation of control logic
// controller is structural
// datapath is structural
parameter R1_size = 8, R2_size = 4;
output
[R2_size -1: 0] count;
output
Ready;
input [R1_size -1: 0]
data;
input
Start, clock, reset_b;
wire
Load_regs, Shift_left, Incr_R2, Zero, E;
Controller_STR M0 (Ready, Load_regs, Shift_left, Incr_R2, Start, E, Zero, clock, reset_b);
Datapath_STR M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock);
endmodule
module Controller_STR (Ready, Load_regs, Shift_left, Incr_R2, Start, E, Zero, clock,
reset_b);
output
Ready;
output
Load_regs, Shift_left, Incr_R2;
input
Start;
input
E, Zero;
input
clock, reset_b;
supply0
GND;
supply1
PWR;
parameter
S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; // Binary code
wire
Load_regs, Shift_left, Incr_R2;
wire
G0, G0_b, D_in0, D_in1, G1, G1_b;
wire
Zero_b = ~Zero;
wire
E_b = ~E;
wire [1: 0]
select = {G1, G0};
wire [0: 3]
Decoder_out;
assign
Ready = ~Decoder_out[0];
assign
Incr_R2 = ~Decoder_out[1];
assign
Shift_left = ~Decoder_out[2];
and
(Load_regs, Ready, Start);
mux_4x1_beh
Mux_1
(D_in1, GND, Zero_b, PWR, E_b, select);
mux_4x1_beh
Mux_0
(D_in0, Start, GND, PWR, E, select);
D_flip_flop_AR_b
M1
(G1, G1_b, D_in1, clock, reset_b);
D_flip_flop_AR_b
M0
(G0, G0_b, D_in0, clock, reset_b);
decoder_2x4_df
M2
(Decoder_out, G1, G0, GND);
endmodule

Section 8
...
4
...
Note: The figure uses symbol E, but the
// Verilog model uses enable to indicate functionality clearly
...
10

Design with Multiplexers

421

parameter R1_size = 8, R2_size = 4;
wire
[R2_size -1: 0]
R2;
wire
[R2_size -1: 0]
count;
wire
Ready;
reg
[R1_size -1: 0]
data;
reg
Start, clock, reset_b;
wire
[1: 0]
state;
// Use only for debug
assign state = {M0
...
G1, M0
...
G0};
Count_Ones_STR_STR M0 (count, Ready, data, Start, clock, reset_b);
initial #650 $finish;
initial begin clock = 0; #5 forever #5 clock = ~clock; end
initial fork
#1 reset_b = 1;
#3 reset_b = 0;
#4 reset_b = 1;
#27 reset_b = 0;
#29 reset_b = 1;
#355 reset_b = 0;
#365 reset_b = 1;
#4 data = 8'Hff;
#145 data = 8'haa;
# 25 Start = 1;
# 35 Start = 0;
#55 Start = 1;
#65 Start = 0;
#395 Start = 1;
#405 Start = 0;
join
endmodule

Testing the Ones Counter
The test bench in HDL Example 8
...
 8
...
Annotations have been added for clarification
...
8
...
(The default is x
...
4 When reset_b is
asserted (low) again at t = 27 the state enters S_idle
...
At the next clock, R2
4

Remember, this simulation is in Verilog’s four‐valued logic system
...

Without a known applied value for the inputs, the next state and outputs will be undetermined, even after the reset
signal has been applied
...
24
Simulation waveforms for count‐of‐ones circuit

starts counting from 0
...
Notice that R2 is incremented in
the next cycle after incr_R2 is asserted
...
The counting
sequence continues in Fig
...
24(b) until Zero is asserted, with E holding the last 1 of the
data word
...
(Additional
testing is addressed in the problems at the end of the chapter
...
11

RACE‐FREE DESIGN (SOFTWARE RACE
CONDITIONS)
Once a circuit has been synthesized, either manually or with tools, it is necessary to
verify that the simulation results produced by the HDL behavioral model match those of
the netlist of the gates (standard cells) of the physical circuit
...
11

Race‐Free Design (Software Race Conditions)
R1 is empty of
1s

120

Name

Machine returns to
S_idle

180

423

Computations are
done

240

300

clock
reset_b

Start
Zero
E
1

state[1: 0]
state[1]
state[0]

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

0

Ready
Load_regs
Shift_left
Incr_R2
ff

data[7: 0]

aa

f8

R1[7: 0]
E
R2[3: 0]
count[3: 0]

2
2

f0
3
3

e0
4
4

c0
5
5

80
6
6

00
7
7

8
8

R2 holds number of 1s
(b)

Figure 8
...
There are various
potential sources of mismatch between the results of a simulation, but we will consider
one that typically happens in HDL‐based design methodology
...
e
...
e
...


424

Chapter 8

Design at the Register Transfer Level

Now consider a sequential machine with an HDL model in which all assignments
are made with the blocked assignment operator
...
Which
executes first? Suppose that when a clock pulse occurs, the state of the controller
changes before the register operations execute
...
The new values of the outputs would be used by the
datapath when it finally executes its assignments at that same clock pulse
...
Conversely, suppose that
when the clock pulse occurs, the datapath unit executes its operations and updates its
status signals first
...
The result could
differ from that which would result if the state had been updated before the edge‐
sensitive operations in the datapath executed
...
Failing to detect a mismatch can have disastrous consequences for
the user of the design
...
It is better to avoid the mismatch by following a strict discipline in your
design
...

A designer can eliminate the software race conditions just described by observing
the rule of modeling combinational logic with blocked assignments and modeling
state transitions and edge‐sensitive register operations with nonblocking assignments
...
The mechanism does this because simulators
evaluate the expressions on the right‐hand side of their nonblocking assignment
statements before any blocked assignments are made
...
This matches the
hardware reality
...

It also might appear that the physical structure of a datapath and the controller
together create a physical (i
...
, hardware), race condition, because the status signals are
fed back to the controller and the outputs of the controller are fed forward to the
datapath
...
The state cannot update until the next edge of the clock, even though the
status signals update the value of the next state
...
12

Latch‐Free Design (Why Waste Silicon?)

425

between clock cycles
...
Remember, the design must implement the correct logic and operate at
the speed prescribed by the clock
...
12

L AT C H ‐ F R E E D E S I G N ( W H Y W A S T E
SILICON?)
Continuous assignments model combinational logic implicitly
...
In simulation, the
simulator monitors the right‐hand sides of all continuous assignments, detects a change
in any of the referenced variables, and updates the left‐hand side of an affected assignment statement
...
If a level‐sensitive cyclic behavior is used to describe combinational logic, it is
essential that the sensitivity list include every variable that is referenced on the right‐hand
side of an assignment statement in the behavior
...
This
implementation wastes silicon area and may have a mismatch between the simulation of
the behavioral model and the synthesized circuit
...

Consequently, Verilog 2001 included a new operator to reduce the risk of accidentally
synthesizing latches
...
In effect, the operator @* indicates that the logic is to be interpreted

HDL Example 8
...


426

Chapter 8

Design at the Register Transfer Level

and synthesized as level‐sensitive combinational logic; the logic has an implicit sensitivity
list composed of all of the variables that are referenced by the procedural assignments
...


8
...
Verilog 2001 contains features
that are very useful to designers, but which are not considered here
...
These enhancements are treated in more
advanced texts using Verilog 2001 and Verilog 2005
...

8
...
2

A logic circuit with active‐low synchronous reset has two control inputs x and y
...
If x is 0 and y
is 1, register R is cleared to zero and control goes from the initial state to a third state
...
Draw (1) a block diagram showing the controller, datapath unit (with internal registers), and signals, and (2) the portion of an ASMD
chart starting from an initial state
...
3

Draw the ASMD charts for the following state transitions:
(a) If x = 1, control goes from state S1 to state S2; if x = 0, generate a conditional operation R 6 = R + 2 and go from S1 to S2
...

(c) Start from state S1; then if xy = 11, go to S2; if xy = 01 go to S3; and if xy = 10, go to S1;
otherwise, go to S3
...
4

Show the eight exit paths in an ASM block emanating from the decision boxes that check
the eight possible binary values of three control variables x, y, and z
...
5

Explain how the ASM and ASMD charts differ from a conventional flowchart
...
  8
...
Explain the difference
between and ASM chart and an ASMD chart
...


8
...
The one door through which people enter the room has a photocell
that changes a signal x from 1 to 0 while the light is interrupted
...
The datapath circuit consists of an up–down counter with a display that
shows how many people are in the room
...
7* Draw a block diagram and an ASMD chart for a circuit with two eight‐bit registers RA
and RB that receive two unsigned binary numbers
...
5, and set a borrow flip‐flop to 1 if
the answer is negative
...

8
...

(b) If the number in AR is negative, divide the number in AR by 2 and transfer the result
to register CR
...

(d) If the number in AR is zero, clear register CR to 0
...

8
...
8
...
Use one flip‐flop per
state (a one‐hot assignment)
...

8
...
P8
...
It has four states and two
inputs x and y
...
Write and verify a Verilog model of the
controller
...
10
Control state diagram for Problems 8
...
11
8
...
P8
...
Use D flip‐flops
...
12 Design the four‐bit counter with synchronous clear specified in Fig
...
10
...


428

Chapter 8

Design at the Register Transfer Level

8
...
4), and verify that its behavior
matches that of the RTL description
...

8
...
2) entering an unused state?
8
...
2, and verify that it recovers from an
unexpected reset condition during its operation, i
...
, a “running reset” or a “reset on‐the‐fly
...
16* Develop a block diagram and an ASMD chart for a digital circuit that multiplies two binary
numbers by the repeated‐addition method
...
Design the
circuit
...
An adder circuit adds the contents of BR to PR
...
Write and verify a Verilog behavioral model of the circuit
...
17* Prove that the multiplication of two n‐bit numbers gives a product of length less than or
equal to 2n bits
...
18* In Fig
...
14, the Q register holds the multiplier and the B register holds the multiplicand
...

(a) How many bits can be expected in the product, and where is it available?
(b) How many bits are in the P counter, and what is the binary number loaded into it
initially?
(c) Design the circuit that checks for zero in the P counter
...
19 List the contents of registers C, A, Q, and P in a manner similar to Table 8
...

8
...
8
...

8
...
 8
...

8
...
22 shows an alternative ASMD chart for a sequential binary multiplier
...
Compare this design with that described by the ASMD
chart in Fig
...
15(b)
...
23 Figure P8
...
Write
and verify an RTL model of the system
...
8
...

8
...
5
encapsulates the descriptions of the controller and the datapath in a single Verilog
module
...

8
...
8
...
Therefore, it executes for a fixed
number of clock cycles, independently of the data
...


Problems

429

reset

S_idle
Ready

A Ͻϭ 0
C Ͻϭ 0
B Ͻϭ Multiplicand
Q Ͻϭ Multiplier
P Ͻϭ m_size

Start
1
Load_regs

S_loaded
Decr_P

P Ͻϭ P Ϫ 1
Decrement counter
{C, A} Ͻϭ A ϩ B

Q[0]

1

Add multiplicand
to shifted sum
Add_regs

Shift_regs

S_sum

Shift_regs

S_shifted

{C, A, Q} Ͻϭ {C, A, Q} ϾϾ 1
17-bit register shifts to the
right by one bit

Zero
1

FIGURE P8
...
22

(b) Write an HDL description of the circuit
...

(c) Write a test plan and a test bench, and verify the circuit
...
26 Modify the ASMD chart of the sequential binary multiplier shown in Fig
...
15 to add and
shift in the same clock cycle
...

8
...
6 generates a product for all possible
values of the multiplicand and multiplier
...
23
ASMD chart for Problem 8
...
Write additional statements to compare the result produced by the RTL description with the expected result
...
Repeat for the structural model of the multiplier
...
28 Write the HDL structural description of the multiplier designed in Section 8
...
Use the
block diagram of Fig
...
14(a) and the control circuit of Fig
...
18
...
6
...
29 An incomplete ASMD chart for a finite state machine is shown in Fig
...
29
...

(a) Draw the equivalent state diagram
...

(c) List the state table for the control unit
...
29
ASMD chart for Problem 8
...

(e) Derive a table showing the multiplexer input conditions for the control unit
...

(g) Using the results of (f), write and verify a structural model of the controller
...


432

Chapter 8

Design at the Register Transfer Level

8
...
31* Using the Verilog HDL operators listed in Table 8
...
32 Consider the following always block:
always @ (posedge CLK)
if (S1) R1 <= R1 + R2;
else if (S2) R1 <= R1 + 1;
else R1 <= R1;
Using a four‐bit counter with parallel load for R1 (as in Fig
...
15) and a four‐bit adder,
draw a block diagram showing the connections of components and control signals for a
possible synthesis of the block
...
33 The multilevel case statement is often translated by a logic synthesizer into hardware
multiplexers
...
34 The design of a circuit that counts the number of ones in a register is carried out in Section
8
...
The block diagram for the circuit is shown in Fig
...
22(a), a complete ASMD chart
for the circuit appears in Fig
...
22(c), and structural HDL models of the datapath and
controller are given in HDL Example 8
...
Using the operations and signal names indicated on the ASMD chart,
(a) Write Datapath_BEH, an RTL description of the datapath unit of the ones counter
...
Execute the test plan to verify the functionality of the datapath
unit, and produce annotated simulation results relating the test plan to the waveforms
produced in a simulation
...

Write a test plan specifying the functionality that will be tested, and write a test bench
to implement the plan
...

(c) Write Count_Ones_BEH_BEH, a top‐level module encapsulating and integrating
Controller_BEH and Datapath_BEH
...
Produce annotated simulation results relating the test plan to the
waveforms produced in a simulation
...
8
...
Write a test plan specifying the functionality that
will be tested, and write a test bench to implement the plan
...

(e) Write Count_Ones_BEH_1_Hot, a top‐level module encapsulating the module Controller_BEH_1_Hot and Datapath_BEH
...
Produce annotated simulation results relating the test plan to the
waveforms produced in a simulation
...
35 The HDL description and test bench for a circuit that counts the number of ones in a
register are given in HDL Example 8
...
Modify the test bench and simulate the circuit to
verify that the system operates correctly for the following patterns of data: 8Јhff, 8Јh0f,
8Јhf0, 8Јh00, 8Јhaa, 8Јh0a, 8Јha0, 8Јh55, 8Јh05, 8Јh50, 8Јha5, and 8Јh5a
...
36 The design of a circuit that counts the number of ones in a register is carried out in Section
8
...
The block diagram for the circuit is shown in Fig
...
22(a), a complete ASMD chart
for this circuit appears in Fig
...
22(c), and structural HDL models of the datapath and
controller are given in HDL Example 8
...
Using the operations and signal names indicated on the ASMD chart,
(a) Design the control logic, employing one flip‐flop per state (a one‐hot assignment)
...

(b) Write Controller_Gates_1_Hot, a gate‐level HDL structural description of the circuit,
using the control designed in part (a) and the signals shown in the block diagram of
Fig
...
22(a)
...

(d) Write Count_Ones_Gates_1_Hot_STR, a top‐level module encapsulating and integrating
instantiations of Controller_Gates_1_Hot and Datapath_STR
...
Produce annotated simulation results relating the
test plan to the waveforms produced in a simulation
...
37 Compared with the circuit presented in HDL Example 8
...
P8
...
This circuit accomplishes addition and shifting
in the same clock cycle and adds the LSB of the data register to the counter register at
every clock cycle
...

(b) Using the ASMD chart, write an RTL description of the circuit
...

(c) Design the control logic, using one flip‐flop per state (a one‐hot assignment)
...

(d) Write the HDL structural description of the circuit, using the controller designed in
part (c) and the block diagram of Fig
...
37(a)
...
Simulate the circuit to verify the operation described
in both the RTL and the structural programs
...
38 The addition of two signed binary numbers in the signed‐magnitude representation follows
the rules of ordinary arithmetic: If the two numbers have the same sign (both positive or
both negative), the two magnitudes are added and the sum has the common sign; if the
two numbers have opposite signs, the smaller magnitude is subtracted from the larger and

434

Chapter 8

Design at the Register Transfer Level

Status
signals

reset_b

data
R1[0]
Zero

S_idle
Ready

Datapath R1

...


Start
R2

1
S_running

Ready

1
reset_b
Clock

R1 Ͻϭ data
R2 Ͻϭ 0

R2 Ͻϭ R2 ϩ R1[0]
R1 Ͻϭ R1 ϾϾ 1

Zero

count
(a)

(b)

FIGURE P8
...
37

the result has the sign of the larger magnitude
...
The leftmost bit of the number holds the sign and the other seven bits hold the magnitude
...
39* For the circuit designed in Problem 8
...
The datapath and controller are to be described in separate units
...
The datapath and controller are to
be described in separate units
...
40 Modify the block diagram of the sequential multiplier given in Fig
...
14(a) and the ASMD
chart in Fig
...
15(b) to describe a system that multiplies 32‐bit words, but with 8‐bit (bytewide) external datapaths
...
When
Start is asserted, the machine is to fetch the data bytes from a single 8‐bit data bus in
consecutive clock cycles (multiplicand bytes first, followed by multiplier bytes, least significant byte first) and store the data in datapath registers
...
When Run is asserted, the product is
to be formed sequentially
...
When a signal Send_Data is asserted, each byte of the product
is to be placed on an 8‐bit output bus for one clock cycle, in sequence, beginning with the
least significant byte
...
Consider safeguards, such as not attempting to send or receive data
while the product is being formed
...
For example, do not continue to multiply if the shifted multiplier
is empty of 1’s
...
41
Two‐stage pipeline register: Datapath unit and ASMD chart

8
...
P8
...

Decimators are used in digital signal processors to move data from a datapath with a high
clock rate to a datapath with a lower clock rate, converting data from a parallel format
to a serial format in the process
...
The contents of the
holding register R0 can be shifted out serially, to accomplish an overall parallel‐to‐serial
conversion of the data stream
...
Note that
synchronous transitions which would occur from the other states to S_idle under the
action of rst are not shown
...
At the next clock, the state goes to
S_full, and now the pipe is full
...
If Ld is not asserted, the machine

436

Chapter 8

Design at the Register Transfer Level

enters S_wait and remains there until Ld is asserted, at which time it dumps the pipe and
returns to S_1 or to S_idle, depending on whether En is asserted, too
...

(a) Develop the complete ASMD chart
...

(c) Write and verify a Verilog behavioral model of the control unit
...

8
...
8
...
It
arises because the status signal E is formed as the output of a flip‐flop into which the MSB
of R1 is shifted
...


REFERENCES
1
...

3
...

5
...

7
...


9
...

11
...

13
...


Arnold, M
...
1999
...
Upper Saddle River, NJ: Prentice
Hall
...
1997 A Verilog HDL Primer
...


...
1998
...
Allentown, PA: Star Galaxy Press
...
D
...
Modeling, Synthesis, and Rapid Prototyping with Verilog HDL
...

Ciletti, M
...
2010
...
Upper Saddle River,
NJ: Prentice Hall
...
R
...
Designing Logic Systems Using State Machines
...

Hayes, J
...
1993
...
Reading, MA: Addison‐Wesley
...
2005
...

Mano, M
...
1993
...
Upper Saddle River, NJ: Prentice
Hall
...
M
...
R
...
2005
...

Upper Saddle River, NJ: Prentice Hall
...
2003
...
Mountain View,
CA: SunSoft Press (a Prentice Hall Title)
...
J
...
HDL Chip Design
...

Thomas, D
...
, and P
...
Moorby
...
The Verilog Hardware Description Language,
5th ed
...

Winkler, D
...
Prosser
...
Englewood Cliffs, NJ:

...


Web Search Topics

WEB SEARCH TOPICS
Algorithmic state machine
Algorithmic state machine chart
Asynchronous circuit
Decimator
Digital control unit
Digital datapath unit
Mealy machine
Moore machine
Race condition

437

Chapter 9

Laboratory Experiments with
Standard ICs and FPGAs

9
...
The
experiments give the student using this book hands‐on experience
...
The experiments are ordered according to
the material presented in the book
...
If an FPGA prototyping board is available, the experiments can be implemented in an FPGA as an alternative to standard ICs
...

2
...

4
...

Toggle switches to provide logic‐1 and logic‐0 signals
...

A clock‐pulse generator with at least two frequencies: a low frequency of about
1 pulse per second to observe slow changes in digital signals and a higher frequency
for observing waveforms in an oscilloscope
...
A power supply of 5 V
...
Socket strips for mounting the ICs
...
Solid hookup wires and a pair of wire strippers for cutting the wires
...
A digital logic trainer contains LED lamps, toggle switches, pulsers,
438

Section 9
...
Some experiments may require
additional switches, lamps, or IC socket strips
...

Additional equipment required is a dual‐trace oscilloscope (for Experiments 1, 2, 8,
and 15), a logic probe to be used for debugging, and a number of ICs
...

The integrated circuits to be used in the experiments can be classified as small‐scale
integration (SSI) or medium‐scale integration (MSI) circuits
...
The eight
SSI gate ICs needed for the experiments—two‐input NAND, NOR, AND, OR, and
XOR gates, inverters, and three‐input and four‐input NAND gates—are shown in
Fig
...
1
...
The pins are
numbered from 1 to 14
...
These are the supply terminals, which must be connected to a power supply
of 5 V for proper operation of the circuit
...

Detailed descriptions of the MSI circuits can be found in data books published by
the manufacturers
...
Various semiconductor companies publish data books for the 7400 series
...
The operation of the circuit is explained by referring to similar circuits in
previous chapters
...
Nevertheless, reference to a
data book will always be preferable, as it gives more detailed description of the circuits
...
To
illustrate, we introduce the ripple counter IC, type 7493
...

The information about the 7493 IC that is found in a data book is shown in Figs
...
2(a)
and (b)
...
All inputs and outputs are given symbolic letters and assigned to pin
numbers
...
Some of the pins are not used by the circuit and are marked as
NC (no connection)
...
When drawing schematic diagrams in this
chapter, we will show the IC in block diagram form, as in Fig
...
2(c)
...
All input terminals are placed on the left of the
block and all output terminals on the right
...
VCC, and GND are the power terminals
connected to pins 5 and 10
...
1
Digital gates in IC packages with identification numbers and pin assignments

440

Section 9
...
2
IC type 7493 ripple counter

and output terminals
...

The operation of the circuit is similar to the ripple counter shown in Fig
...
8(a) with
an asynchronous clear to each flip‐flop
...
To clear all four flip‐
flops to 0, the output of the NAND gate must be equal to 0
...
Note that the J and K inputs show
no connections
...
Note also that
output QA is not connected to input B internally
...
It can operate as a four‐bit counter using input A if output QA is connected
to input B
...
The reset inputs, R1 and R2, at pins 2
and 3, respectively, must be grounded
...
The input pulses must be applied to input A at pin 14, and the four flip‐flop
outputs of the counter are taken from QA, QB, QC, and QD at pins 12, 9, 8, and 11,
respectively, with QA being the least significant bit
...
2(c) demonstrates the way that all MSI circuits will be symbolized graphically in this chapter
...
The letter symbols for the inputs and outputs in the IC block
diagram will be according to the symbols used in the data book
...
1
Integrated Circuits Required for the Experiments
Graphic Symbol

7447

Description

In Chapter 9

In Chapter 10

Various gates

IC Number

Fig
...
1

Fig
...
1

BCD‐to‐seven‐segment decoder

Fig
...
8

—

7474

Dual D‐type flip‐flops

Fig
...
13

Fig
...
9(b)

7476

Dual JK‐type flip‐flops

Fig
...
12

Fig
...
9(a)

7483

Four‐bit binary adder

Fig
...
10

Fig
...
2

7493

Four‐bit ripple counter

Fig
...
2

Fig
...
13

8 * 1 multiplexer

Fig
...
9

Fig
...
7(a)

74155

3 * 8 decoder

Fig
...
7

Fig
...
6

74157

Quadruple 2 * 1 multiplexers

Fig
...
17

Fig
...
7(b)

74161

Four‐bit synchronous counter

Fig
...
15

Fig
...
14

74189

16 * 4 random‐access memory

Fig
...
18

Fig
...
15

74194

Bidirectional shift register

Fig
...
19

Fig
...
12
Fig
...
11

74151

74195
7730
72555

Four‐bit shift register

Fig
...
16

Seven‐segment LED display

Fig
...
8

—

Timer (same as 555)

Fig
...
21

—

Section 9
...
The
operation of the circuit will be specified by means of a truth table or a function table
...
These are
standard graphic symbols approved by the Institute of Electrical and Electronics
Engineers and are given in IEEE Standard 91‐1984
...
10
...
The standard graphic symbol
for the 7493 IC is shown in Fig
...
13
...
9
...
The standard graphic symbols of the other ICs that are needed to
run the experiments are presented in Chapter 10
...

Table 9
...
In addition, the table lists the numbers
of the figures in Chapter 10 in which the equivalent standard graphic symbols are drawn
...
Section 9
...


9
...
It serves as an introduction to the breadboard used
in the laboratory and acquaints the student with the cathode‐ray oscilloscope
...
2, on binary numbers, and Section 1
...

,

Binary Count
IC type 7493 consists of four flip‐flops, as shown in Fig
...
2
...
Connect the IC to operate as a four‐bit binary counter by
wiring the external terminals, as shown in Fig
...
3
...
Input A at pin 14 is connected to a pulser that
provides single pulses
...
The
four outputs go to four indicator lamps, with the low‐order bit of the counter from QA
connected to the rightmost indicator lamp
...
All connections should be made with the power supply in the off position
...
The four‐bit number in the
output is incremented by 1 for every pulse generated in the push‐button pulser
...
Disconnect the input of the counter at pin
14 from the pulser, and connect it to a clock generator that produces a train of pulses at
a low frequency of about 1 pulse per second
...

Note that the binary counter will be used in subsequent experiments to provide the
input binary signals for testing combinational circuits
...
3
Binary counter

Oscilloscope Display
Increase the frequency of the clock to 10 kHz or higher and connect its output to an oscilloscope
...
Using a
dual‐trace oscilloscope, connect the output of QA to one channel and the output of the
clock to the second channel
...
Note also that the clock frequency at the output of the first flip‐flop is one‐half that of the input clock frequency
...
The four‐bit counter divides the
incoming frequency by 16 at output QD
...
Make sure that you include at least 16 clock
cycles
...
Then repeat by observing and
recording the waveforms of QA together with QB, followed by the waveforms of QB with
QC and then QC with QD
...


BCD Count
The BCD representation uses the binary numbers from 0000 to 1001 to represent the
coded decimal digits from 0 to 9
...
9
...
Outputs QB and QD are connected
to the two reset inputs, R1 and R2
...
The counter starts from 0, and every
input pulse increments it by 1 until it reaches the count of 1001
...
This momentary output cannot be

Section 9
...
4
BCD counter

sustained, because the four cells immediately clear to 0, with the result that the output
goes to 0000
...

Connect the IC to operate as a BCD counter
...
Verify that the count goes from 0000 to 1001
...
Observe the
clock waveform and the four outputs on the oscilloscope
...
Make sure to include
at least 10 clock cycles in the oscilloscope display and in the composite timing diagram
...
This means that each bit in the
four outputs produces a fixed pattern of 1’s and 0’s that is repeated every 10 pulses
...
The list
will show that output QA, being the least significant bit, produces a pattern of alternate
1’s and 0’s
...
Obtain the pattern for the other two outputs and then check all four
patterns on the oscilloscope
...
The
pattern of 1’s and 0’s for the corresponding output is obtained by observing the output
levels at the vertical positions where the pulses change from 1 to 0
...
This is done
by connecting one or two outputs to the reset inputs, R1 and R2
...
9
...

Utilizing your knowledge of how R1 and R2 affect the final count, connect the 7493
IC to count from 0000 to the following final counts:
(a) 0101
(b) 0111
(c) 1011
Connect each circuit and verify its count sequence by applying pulses from the pulser
and observing the output count in the indicator lamps
...


9
...
9
...
“Quadruple” means
that there are four gates within the package
...
8
...
7
...
The truth table
is obtained by connecting the inputs of the gate to switches and the output to an indicator lamp
...
2
...


Waveforms
For each gate listed, obtain the input–output waveform of the gate
...
Use the two low‐order outputs of a binary counter
(Fig
...
3) to provide the inputs to the gate
...
9
...
The oscilloscope display will repeat this
waveform, but you should record only the nonrepetitive portion
...
3

Experiment 2: Digital Logic Gates

A

QA
QB

QA

0

1

0

1

QB

0

0

1

1

F

Input
pulses

1

1

1

447

0

F

Fig
...
3
(counter)

FIGURE 9
...
The output will be the same as
the input, except that it will be delayed by the time it takes the signal to propagate
through all six inverters
...
Using the
oscilloscope, determine the delay from the input to the output of the sixth inverter during the upswing of the pulse and again during the downswing
...
Set the time‐base knob to the lowest
time‐per‐division setting
...
Divide the total delay by 6 to obtain an average propagation delay per inverter
...
(See Fig
...
32
...


NAND Circuit
Using a single 7400 IC, construct a circuit with NAND gates that implements the Boolean
function
F = AB + CD
1
...

2
...

3
...


448

Chapter 9

Laboratory Experiments

4
...

5
...
9
...
Connect the input clock pulses from the counter to one
channel of a dual‐trace oscilloscope and output F to the other channel
...


9
...
The Boolean functions are simplified by using the map
method, as discussed in Chapter 3
...
7
...
9
...
For example, if the circuit needs an inverter and
there is an extra two‐input gate available in a 7400 IC, then both inputs of the gate are
to be connected together to form a single input for an inverter
...
The logic diagram shown in Fig
...
6 requires two ICs—a 7400 and a 7410
...
If the inverters were taken from a 7404 IC, the circuit would have required
three ICs
...

Assign pin numbers to all inputs and outputs of the gates, and connect the circuit with
the x, y, and z inputs going to three switches and the output F to an indicator lamp
...

Obtain the Boolean function of the circuit and simplify it, using the map method
...
Test both circuits by
applying identical inputs to each and observing the separate outputs
...
This will
prove that the simplified circuit behaves exactly like the original circuit
...
4

Experiment 3: Simplification of Boolean Functions

449

x

y

F

z

FIGURE 9
...
Obtain a composite logic diagram with four
inputs, A, B, C, and D, and two outputs, F1 and F2
...
Do not duplicate the same gate if
the corresponding term is needed for both functions
...
Connect the circuit and check its operation
...


Complement
Plot the following Boolean function in a map:
F = AЈD + BD + BЈC + ABЈD
Combine the 1’s in the map to obtain the simplified function for F in sum‐of‐products
form
...
Implement both F and FЈ with NAND gates, and connect the two
circuits to the same input switches, but to separate output indicator lamps
...


450

Chapter 9

Laboratory Experiments

9
...

The first two circuits are to be constructed with NAND gates, the third with XOR gates,
and the fourth with a decoder and NAND gates
...
9
...
9
...
F
is to be equal to 1 when A = 1, provided that B = 0, or when B = 1, provided that
either C or D is also equal to 1
...

1
...

2
...

3
...

4
...


Majority Logic
A majority logic is a digital circuit whose output is equal to 1 if the majority of the inputs
are 1’s
...
Design and test a three‐input majority circuit using
NAND gates with a minimum number of ICs
...
Use XOR gates
...


Decoder Implementation
A combinational circuit has three inputs—x, y, and z—and three outputs—F1, F2, and
F3
...


Section 9
...
9
...
The
74155 can be connected as a dual 2 * 4 decoder or as a single 3 * 8 decoder
...
The function of the circuit is
similar to that illustrated in Fig
...
18
...
The eight outputs are labeled with symbols given in the data book
...
The implementation with the decoder is as shown in
Fig
...
21, except that the OR gates must be replaced with external NAND gates when
the 74155 is used
...
7
IC type 74155 connected as a 3 * 8 decoder

452

Chapter 9

Laboratory Experiments

9
...
In this
experiment, you will design and construct three combinational‐circuit converters
...
4
...
6) into the equivalent four‐bit binary number
...
(This can be done with one 7486 IC
...


9’s Complementer
Design a combinational circuit with four input lines that represent a decimal digit in
BCD and four output lines that generate the 9’s complement of the input digit
...
This output should
be equal to logic 1 when the four inputs have one of the unused combinations of the
BCD code
...
9
...


Seven‐Segment Display
A seven‐segment indicator is used to display any one of the decimal digits 0 through 9
...
A BCD‐to‐seven‐segment decoder accepts
a decimal digit in BCD and generates the corresponding seven‐segment code, as is
shown pictorially in Problem 4
...

Figure 9
...
The
7447 IC is a BCD‐to‐seven‐segment decoder/driver that has four inputs for the BCD
digit
...
The four‐bit BCD
digit is converted to a seven‐segment code with outputs a through g
...
This
IC contains the seven light‐emitting diode (LED) segments on top of the package
...
A 47@⍀ resistor to VCC is
needed in order to supply the proper current to the selected LED segments
...

Construct the circuit shown in Fig
...
8
...
Inputs 1010 through 1111 have
no meaning in BCD
...
Observe and record the output patterns of the
six unused input combinations
...
7

Experiment 6: Design With Multiplexers

453

VCC ϭ 5 V

16

47 ⍀

VCC
a
7
1
2
6

b

A

c
B
7447

d

C
e
D
f
g

13

1

12

13

11

10

10

8

9

7

15

2

14

11

a

a
b

f

g

CA

14

b

c
d
e
f

e

c
d
7730

g

GND
8

FIGURE 9
...
7

E X P E R I M E N T 6 : D E S I G N W I T H M U LT I P L E X E R S
In this experiment, you will design a combinational circuit and implement it with multiplexers, as explained in Section 4
...
The multiplexer to be used is IC type 74151, shown
in Fig
...
9
...
 4
...
The eight inputs are designated D0 through D7
...
A strobe control S acts as an enable signal
...

Output W is the complement of Y
...


Design Specifications
A small corporation has 10 shares of stock, and each share entitles its owner to one vote
at a stockholder’s meeting
...
W: 1 share
Mr
...
Y: 3 shares
Mrs
...
9
IC type 74151 38 * 1 multiplexer

Each of these persons has a switch to close when voting yes and to open when voting
no for his or her shares
...
Use a seven‐segment display and a decoder, as shown in Fig
...
8, to display
the required number
...
(Note
that binary input 15 into the 7447 blanks out all seven segments
...
Otherwise, the display shows a decimal number equal
to the number of shares that vote yes
...
Do not use 5 V for logic 1
...


Section 9
...
8

Experiment 7: Adders and Subtractors

455

EXPERIMENT 7: ADDERS AND SUBTRACTORS
In this experiment, you will construct and test various adder and subtractor circuits
...

Adders are discussed in Section 4
...
Subtraction with 2’s complement is explained in
Section 1
...
A four‐bit parallel adder–subtractor is shown in Fig
...
13, and the comparison of two numbers is explained in Section 4
...


Half Adder
Design, construct, and test a half‐adder circuit using one XOR gate and two NAND gates
...


Parallel Adder
IC type 7483 is a four‐bit binary parallel adder
...
9
...

The 2 four‐bit input binary numbers are A1 through A4 and B1 through B4
...
C0 is the input carry and C4 the output carry
...
Then connect the four A inputs to a fixed binary number, such as 1001, and the
B inputs and the input carry to five toggle switches
...
10
IC type 7483 four‐bit binary adder

14
15
2
6
9

456

Chapter 9

Laboratory Experiments

indicator lamps
...
Show that when the input carry is equal
to 1, it adds 1 to the output sum
...
The 2’s complement can be obtained by taking the 1’s
complement and adding 1
...
This is done as shown in Fig
...
11
...
Thus,
when the mode select M is equal to 1, the input carry C0 is equal to 1 and the sum output
is A plus the 2’s complement of B
...

Connect the adder–subtractor circuit and test it for proper operation
...
Perform

5
1
3
Data input
A

8
10
16

VCC
A4

C4

Data input
B

A2
A1

S4
S3

B4

S2
B3

11

B2

B1

C0 GND
13

Mode select M
M ϭ 0 for add
M ϭ 1 for subtract

FIGURE 9
...
9

Experiment 8: Flip‐Flops

457

the following operations and record the values of the output sum and the output
carry C4:
9 + 5
9 - 5
9 + 9
9 - 9
9 + 15 9 - 15
Show that during addition, the output carry is equal to 1 when the sum exceeds 15
...


Magnitude Comparator
The comparison of two numbers is an operation that determines whether one number is
greater than, equal to, or less than the other number
...
9
...
If the output in S is equal to zero,
then A = B
...

It is necessary to supplement the subtractor circuit of Fig
...
11 to provide the comparison logic
...

Construct the comparator circuit and test its operation
...


9
...
The internal construction of latches and flip‐flops can be found in
Sections 5
...
4
...
Connect the two inputs to
switches and the two outputs to indicator lamps
...
Obtain
the function table of the circuit
...


458

Chapter 9

Laboratory Experiments

Master–Slave Flip‐Flop
Connect a master–slave D flip‐flop using two D latches and an inverter
...
Connect the output of the master
latch to one indicator lamp and the output of the slave latch to another indicator
lamp
...
Press the push
button in the pulser and then release it to produce a single pulse
...
Press the push button again a few times while observing the
two indicator lamps
...

Disconnect the clock input from the pulser and connect it to a clock generator
...
This causes the flip‐flop to
be complemented with each clock pulse
...
Verify that the delay between
the master and the slave outputs is equal to the positive half of the clock cycle
...


7

2
4

J

1
16

PR

Q

15

9
6

CK
K

J

QЈ
CLR

14

12

PR

Q

11
VCC ϭ pin 5
GND ϭ pin 13

CK
K

QЈ
CLR

3

10

8

Function table
Outputs

Inputs
Preset

Clear

Clock

J

K

Q

QЈ

0
1
0

1
0
0

X
X
X

X
X
X

X
X
X

1
0
1

0
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

No change
1
0
1
0
Toggle

FIGURE 9
...
9

Experiment 8: Flip‐Flops

459

Edge‐Triggered Flip‐Flop
Construct a D‐type positive‐edge‐triggered flip‐flop using six NAND gates
...
Set the value of D to the complement of Q
...
Verify that the output does
not change when the clock input is logic 1, when the clock goes through a negative
transition, or when the clock input is logic 0
...

Disconnect the input from the pulser and connect it to the clock generator
...
This causes the output to be complemented
with each positive transition of the clock pulse
...
Show that
the output changes in response to a positive edge transition
...
The pin
assignment for each flip‐flop is shown in Fig
...
12
...
The first three entries in the table specify the operation of the asynchronous

4
2
3

10

PR
D

Q

5

PR

12

D

11

CK
QЈ
CLR

Q

9

CK

6

QЈ
CLR

1

8

13

Function table
Inputs

Outputs

Preset

Clear

Clock

D

Q

QЈ

0
1
0

1
0
0

X
X
X

X
X
X

1
0
1

0
1
1

1
1
1

1
1
1

0

0
1
X

1
0
1
0
No change

FIGURE 9
...
These inputs behave like a NAND SR latch and are independent
of the clock or the J and K inputs
...
) The last four
entries in the function table specify the operation of the clock with both the preset and
clear inputs maintained at logic 1
...
The positive
transition of the pulse changes the master flip‐flop, and the negative transition changes
the slave flip‐flop as well as the output of the circuit
...
The flip‐flop toggles, or is complemented, when J = K = 1
...

IC type 7474 consists of two D positive‐edge‐triggered flip‐flops with preset and
clear
...
9
...
The function table specifies the preset
and clear operations and the clock’s operation
...
Investigate the operation
of one of the flip‐flops and verify its function table
...
10

EXPERIMENT 9: SEQUENTIAL CIRCUITS
In this experiment, you will design, construct, and test three synchronous sequential circuits
...
9
...
9
...
Choose any type of gate that will minimize
the total number of ICs
...
7

...
An enable input E
determines whether the counter is on or off
...
If E = 1, the
counter is enabled and a second input, x, determines the direction of the count
...
If x = 0,
the circuit counts downward with the sequence 11, 10, 01, 00, and the count repeats
...
Design the sequential circuit with E and x as inputs
...
9
...

Designate the two flip‐flops as A and B, the input as x, and the output as y
...
Verify
the state transition and output by testing the circuit
...
Note that binary states
4, 5, 8, and 9 are not used
...


Section 9
...
14
State diagram for Experiment 9

Check the circuit’s operation for the required count sequence
...
This is done by initializing the circuit to each unused state by means of
the preset and clear inputs and then applying pulses to see whether the counter reaches
one of the valid states
...
11

EXPERIMENT 10: COUNTERS
In this experiment, you will construct and test various ripple and synchronous counter
circuits
...
3 and synchronous counters are covered in Section 6
...


Ripple Counter
Construct a four‐bit binary ripple counter using two 7476 ICs (Fig
...
12)
...
Connect the count‐pulse input to a
pulser and check the counter for proper operation
...
Check that
each input pulse decrements the counter by 1
...
Use two 7476
ICs and one 7408 IC
...
Use two 7476 ICs
and one 7408 IC
...
Determine whether the
counter is self‐starting
...
The application of pulses will transfer the
counter to one of the valid states if the counter is self‐starting
...
The internal logic is similar to that of the circuit shown in Fig
...
14
...
9
...
When the load
signal is enabled, the four data inputs are transferred into four internal flip‐flops, QA
through QD, with QD being the most significant bit
...
Both must be equal to 1 for the counter to operate
...
6, with one exception: The load input in the 74161 is enabled
when equal to 0
...
The two count inputs have don’t‐care conditions and
may be equal to either 1 or 0
...
The circuit functions as a counter when the load input is equal to
1 and both count inputs P and T are equal to 1
...
15
IC type 74161 binary counter with parallel load

Function
Clear outputs to 0
Load input data
Count to next binary value
No change in output

Section 9
...
The carry‐out output is equal to 1 when all four data outputs are
equal to 1
...

Show how the 74161 IC, together with a two‐input NAND gate, can be made to operate as a synchronous BCD counter that counts from 0000 to 1001
...
Use the NAND gate to detect the count of 1001, which then causes all 0’s to be
loaded into the counter
...
12

EXPERIMENT 11: SHIFT REGISTERS
In this experiment, you will investigate the operation of shift registers
...
Shift registers are explained in
Section 6
...


IC Shift Register
IC type 74195 is a four‐bit shift register with parallel load and asynchronous clear
...
9
...
The single control line
labeled SH>LD (shift/load) determines the synchronous operation of the register
...
When SH>LD = 1, the control
input is in the shift mode and the information in the register is shifted right from QA
toward QD
...
The two inputs behave like the J and the complement of K of a JK flip‐flop
...
If both inputs are
equal to 1, QA is set to 1 after the shift
...

The function table for the 74195 shows the mode of operation of the register
...
Synchronous operations are affected by a positive transition of the
clock
...
To shift right, SH/LD must be equal to 1
...

Perform an experiment that will verify the operation of the 74195 IC
...
Include in your function table
the two conditions for JK = 01 and 10
...
Connect the J and K input together to form the serial input
...
Rotate the single
bit with the shift condition and check the state of the register after each clock pulse
...
16
IC type 74195 shift register with parallel load

A switch‐tail ring counter uses the complement output of QD for the serial input
...
Verify your prediction by observing the state sequence after
each shift
...
Connect a feedback shift register whose serial input is

Section 9
...
Predict the sequence of states of the register,
starting from state 1000
...


Bidirectional Shift Register
The 74195 IC can shift only right from QA toward QD
...
This is accomplished by connecting the output of
each flip‐flop to the input of the flip‐flop on its left and using the load mode of the
SH/LD input as a shift‐left control
...

Connect the 74195 as a bidirectional shift register (without parallel load)
...
Construct the shift left as a
ring counter by connecting the serial output QA to the serial input D
...
Shift right three more times and insert 0’s from the serial input switch
...
The single 1 should remain visible while
shifting
...
We will use IC type 74157 for this purpose
...
 4
...
The
pin assignments to the inputs and outputs of the 74157 are shown in Fig
...
17 Note that

...

Construct a bidirectional shift register with parallel load using the 74195 register
and the 74157 multiplexer
...

2
...

4
...


Asynchronous clear
Shift right
Shift left
Parallel load
Synchronous clear

Derive a table for the five operations as a function of the clear, clock, and SH/LD inputs
of the 74195 and the strobe and select inputs of the 74157
...
Use the parallel‐load condition to provide an initial value to the
register, and connect the serial outputs to the serial inputs of both shifts in order not to
lose the binary information while shifting
...
17
IC type 74157 quadruple 2 * 1 multiplexers

9
...
Serial
addition of two binary numbers can be done by means of shift registers and a full adder,
as explained in Section 6
...


Serial Adder
Starting from the diagram of Fig
...
6, design and construct a four‐bit serial adder using
the following ICs: 74195 (two), 7408, 7486, and 7476
...
Provide a toggle switch to clear

Section 9
...
Another switch will be needed to specify whether register
B is to accept parallel data or is to be shifted during the addition
...
This is done by
first clearing the registers and the carry flip‐flop
...
Apply four pulses to add B to A serially, and check that the result in A is 0101
...
9
...
) Parallel load 0110
into B and add it to A serially
...
Parallel load 1111 into
B and add to A
...

Clear the registers and flip‐flop and try a few other numbers to verify that your serial
adder is functioning properly
...
2 for the design of a serial subtractor (that
subtracts A - B), we will find that the output difference is the same as the output sum, but
that the input to the J and K of the borrow flip‐flop needs the complement of QD (available
in the 74195)
...
When M = 0, the circuit adds A + B
...

Test the adder part of the circuit by repeating the operations recommended to ensure
that the modification did not change the operation
...
Binary 15 can be transferred to register A by first clearing it to 0 and adding 15 from B
...
Note that -7 will appear as the 2’s complement of 7 with a borrow of 1 in the flip‐flop
...
14

EXPERIMENT 13: MEMORY UNIT
In this experiment, you will investigate the behavior of a random‐access memory (RAM)
unit and its storage capability
...
The ROM simulator will then be used to implement combinational circuits, as
explained in Section 7
...
The memory unit is discussed in Sections 7
...
3
...
The internal logic is similar to the circuit shown in Fig
...
6
for a 4 * 4 RAM
...
9
...

The four address inputs select 1 of 16 words in the memory
...
The chip select (CS) input must be equal to 0
to enable the memory
...
The write enable (WE) input determines the type of operation,
as indicated in the function table
...
This

468

Chapter 9

Laboratory Experiments
16
4
Data
inputs

6
10
12

1
15
Address
inputs

Write enable

S1

D2

S2

D3

S3

D4

S4

A0

5
7
9

Data
outputs

11

74189

A1
14
13

Chip select

VCC
D1

2
3

A2
A3
CS
WE
GND
8

Function table
CS

WE

Operation

Data outputs

0
0
1

0
1
X

Write
Read
Disable

High impedance
Complement of selected word
High impedance

FIGURE 9
...
The read operation is performed when WE = 1
...
The memory
has three‐state outputs to facilitate memory expansion
...
The RAM can be tested after
making the following connections: Connect the address inputs to a binary counter using
the 7493 IC (shown in Fig
...
3)
...
15

Experiment 14: Lamp Handball

469

data outputs to four 7404 inverters
...
Connect input CS to ground and WE to a
toggle switch (or a pulser that provides a negative pulse)
...
You must be careful when using the WE switch
...
The proper way to write is first to
set the address in the counter and the inputs in the four toggle switches
...
Be careful not to change the address or the inputs when WE is in the write mode
...
The pattern
of 1’s and 0’s is first entered into the simulating RAM by placing the unit momentarily
in the write mode
...
The ROM can then be used to implement
any combinational circuit
...
6
...
Store the truth table into the 74189 memory by setting the address inputs to the binary value and the data inputs to the corresponding Gray code value
...
Check the code
converter by applying the inputs to the address lines and verifying the correct outputs
in the data output lines
...
Use the CS inputs to
select between the two ICs
...
Test
your circuit by using it as a ROM simulator that adds a three‐bit number to a two‐bit
number to produce a four‐bit sum
...
(The first three bits of the input represent 5, the last two bits represent 2, and the output sum is binary 7
...


9
...
The experiment demonstrates the application of a bidirectional shift register with parallel load
...
We will first introduce an IC that is needed for the experiment and
then present the logic diagram of the simulated lamp handball game
...
The internal logic is similar to that shown in Fig
...
7
...
9
...
The two mode‐control inputs determine the type of operation, as specified
in the function table
...
9
...
It consists
of two 74194 ICs, a dual D flip‐flop 7474 IC, and three gate ICs: the 7400, 7404, and
7408
...
SIR to QA

1

1

0

Shift left in the direction from
QD to QA
...
19
IC type 74194 bidirectional shift register with parallel load

Indicator lamps

QA

QB

QC

QD

QA
SIL

74194
CLR

A

B

C

QC

D

S1

S0

QD

SIR

74194

SIR

CK

QB

SIL

CLR
S1

S0

A

B

C

D CK

CLK

PR

PR
D

Q

Q

D
CK

CK

Pulser

QЈ
CLR

QЈ
CLR

Reset
Start

FIGURE 9
...
The rate at which the light moves is determined by the frequency of the clock
...
The start switch
starts the game by placing the ball (an indicator lamp) at the extreme right
...
The single light
shifts to the left until it reaches the leftmost position (the wall), at which time the ball
returns to the player by reversing the direction of shift of the moving light
...
If the player presses the pulser too soon or too late, the ball disappears and the light goes off
...
The start switch must be open (logic 1) during the game
...
In particular, try to answer the following questions:
1
...
How does the light in the rightmost position come on when the start switch is
grounded? Why is it necessary to place the start switch in the logic‐1 position
before the game starts?
3
...
What happens to the mode‐control inputs and to the ball if the pulser is pressed
while the ball is moving to the left? What happens if the ball is moving to the right,
but has not yet reached the rightmost position?
5
...
9
...
Test the circuit for proper operation by playing the game
...
e
...
Start with a low
clock rate, and increase the clock frequency to make the handball game more challenging
...
Use a BCD‐to‐seven‐segment decoder and a seven‐segment display, as in
Fig
...
8, to display the count from 0 through 9
...
The display should show 0 when the circuit is reset
...
If the light stays on during
the play, the number in the display should not change
...
16

Experiment 15: Clock‐Pulse Generator

473

automatic scoring circuit, with the decimal display incremented automatically each time
the player loses when the light disappears
...
9
...
Two players can
participate in this game, with each player having his or her own pulser
...
The only modification required for the Ping‐Pong game is a second pulser and a change of a few wires
...
e
...
This addition is optional
...
16

E X P E R I M E N T 1 5 : C L O C K ‐ P U L S E G E N E R AT O R
In this experiment, you will use an IC timer unit and connect it to produce clock pulses
at a given frequency
...
The cathode‐ray oscilloscope is used to observe the waveforms
and measure the frequency of the pulses
...
9
...

(The resistors, RA and RB, and the two capacitors are not part of the IC
...
The voltage division
from VCC = 5 V through the three internal resistors to ground produces 2 and 1 of VCC
3
3
(3
...
7 V, respectively) into the fixed inputs of the comparators
...
3 V, the upper comparator resets the flip‐flop and the output
goes low to about 0 V
...
7 V, the lower comparator sets the flip‐flop and the output goes high to about 5 V
...
When the
output is high, QЈ is low and the transistor is cut off
...
3
...
In this
experiment, the IC timer will be operated in the astable mode to produce clock pulses
...
21 shows the external connections for astable operation of the circuit
...
When the charging voltage across
capacitor C reaches 3
...
When the discharging voltage reaches 1
...
Thus, the output continually alternates

474

Chapter 9

Laboratory Experiments
5V

0
...
21
IC type 72555 timer connected as a clock‐pulse generator

between two voltage levels at the output of the flip‐flop
...
This duration is determined from the equation
tH = 0
...
This duration is
determined from the equation
tL = 0
...
001 μF calculate values for RA and RB to produce clock
pulses, as shown in Fig
...
22
...
17

Experiment 16: Parallel Adder and Accumulator

475

1 ␮S
10 ␮S

FIGURE 9
...
Connect the circuit and check the output in the
oscilloscope
...

Observe the waveform in the collector of the transistor at pin 7 and record all pertinent information
...

Connect a variable resistor (potentiometer) in series with RA to produce a variable‐
frequency pulse generator
...

Change the low‐level pulses to high‐level pulses with a 7404 inverter
...


9
...
The numbers to be added will be stored in a RAM
...


Block Diagram
Use the RAM circuit from the memory experiment of Section 9
...
The block diagram and the ICs to be used are shown in Fig
...
23
...
The selection is done by means of a multiplexer
...


Control of Register
Provide toggle switches to control the 74194 register and the 7476 carry flip‐flop as follows:
(a) A LOAD condition transfers the sum to the register and the output carry to the
flip‐flop upon the application of a clock pulse
...
23
Block diagram of a parallel adder for Experiment 16

(b) A SHIFT condition shifts the register right with the carry from the carry flip‐
flop transferred into the leftmost position of the register upon the application
of a clock pulse
...

(c) A NO‐CHANGE condition leaves the contents of the register and flip‐flop
unchanged even when clock pulses are applied
...

The carry flip‐flop should not change if the LOAD condition is disabled or the SHIFT
condition is enabled
...
17

Experiment 16: Parallel Adder and Accumulator

477

Detailed Circuit
Draw a detailed diagram showing all the wiring between the ICs
...


Checking the Circuit
Store the numbers 0110, 1110, 1101, 0101, and 0011 in RAM and then add them to the
register one at a time
...
Predict the values in
the output of the register and carry after each addition in the following sum, and verify
your results:
0110 + 1110 + 1101 + 0101 + 0011

Circuit Operation
Clear the register and the carry flip‐flop to zero, and store the following four‐bit numbers in RAM in the indicated addresses:
Address

Content

0
3
6
9
12

0110
1110
1101
0101
0011

Now perform the following four operations:
1
...

2
...

3
...

4
...

Check that the contents of the first three locations in RAM are as follows:
Address

Contents

0
1
2

0110
0110
0011

Repeat the foregoing four operations for each of the other four binary numbers
stored in RAM
...

,

478

Chapter 9

Laboratory Experiments

Use addresses 5, 8, 11, and 14 to store the shifted value from the register in step 4
...


9
...
An algorithm for multiplying two
binary numbers is presented in Section 8
...
The algorithm implemented in this experiment differs from the one described in Figs
...
14 and 8
...


Block Diagram
The ASMD chart and block diagram of the binary multiplier with those ICs recommended to be used are shown in Fig
...
24(a) and (b)
...
The multiplier, Q, is obtained from another set
of four switches
...
Counter P is
initialized to 0 and then incremented after each partial product is formed
...


Control of Registers
The ASMD chart for the binary multiplier in Fig
...
24(a) shows that the three registers
and the carry flip‐flop of the datapath unit are controlled with signals Load_regs,
Incr_P, Add_regs, and Shift_regs
...

Load_regs clears the product register (A) and the carry flip‐flop (C), loads the multiplicand into register B, loads the multiplier into register Q, and clears the bit counter
...
Add_regs adds the multiplicand to A, if the least significant bit of the shifted
multiplier (Q[0]) is 1
...

The concatenated register CAQ is updated by storing the result of shifting its contents
one bit to the right
...

The state diagram for the control unit is shown in Fig
...
24(c)
...
That information is apparent in Fig
...
24(d)
...
Load_regs is

Section 9
...


Multiplication Example
Before connecting the circuit, make sure that you understand the operation of the
multiplier
...
5, but with B = 1111 for the
multiplicand and Q = 1011 for the multiplier
...


Datapath Design
Draw a detailed diagram of the datapath part of the multiplier, showing all IC pin connections
...
Connect the circuit and check that
each component is functioning properly
...
Assert the control signals
manually by means of the control switches, as specified by the state diagram of
Fig
...
24(c)
...
Compare these outputs with the numbers
in your numerical example to verify that the circuit is functioning properly
...
To operate it manually, it is necessary that the
single clock pulse be a negative pulse
...
You can use any method of
control implementation discussed in Section 8
...

Choose the method that minimizes the number of ICs
...


Checking the Multiplier
Connect the outputs of the control circuit to the datapath unit, and verify the total circuit
operation by repeating the steps of multiplying 1111 by 1011
...
(Remove the manual switches
...

Generate the start signal (Start) with a pulser or any other short pulse, and operate the
multiplier with continuous clock pulses from a clock generator
...
Note that the multiplication will be repeated
as long as signal Start is enabled
...
Then set the switches
to two other four‐bit numbers and press Start again
...
Repeat the multiplication of a few numbers to verify the operation of the circuit
...
24
ASMD chart, block diagram of the datapath, control state diagram, and register
operations of the binary multiplier circuit

9
...
g
...
Circuits can be rapidly prototyped into an FPGA using an

Section 9
...
24
(Continued )

481

482

Chapter 9

Laboratory Experiments

HDL
...
FPGA vendors provide software tools for synthesizing the HDL description
of a circuit into an optimized gate‐level description and mapping (fitting) the resulting
netlist into the resources of their FPGA
...

Most of the hardware experiments outlined in this chapter can be supplemented by
a corresponding software procedure using the Verilog hardware description language
(HDL)
...
The
supplemental experiments have two levels of engagement
...
In the second, if a suitable FPGA prototyping
board is available (e
...
, see www
...
com), the hardware experiments can be
done by synthesizing the Verilog descriptions and implementing the circuits in an FPGA
...
g
...

Prototyping a circuit with an FPGA requires synthesizing a Verilog description to
produce a bit stream that can be downloaded to configure the internal resources
(e
...
, CLBS of a Xilinx FPGA) and connectivity of the FPGA
...


Supplement to Experiment 1 (Section 9
...
Note that the circuit shown in Fig
...
3
uses a push‐button pulser or a clock to cause the count to increment in a circuit built
with standard ICs
...

The software pulser has the ASM chart shown in Fig
...
25, where the external input
(Pushed) is obtained from a mechanical switch or pushbutton
...
19

Verilog HDL Simulation Experiments

483

reset_b

S_idle

pushed
1
S_ pulse
Start
S_wait
A2

Pushed

1

FIGURE 9
...
If the counter, or a state machine, is in the reset state (S_idle) when
the switch is closed, the pulse will launch the activity of the counter or state machine
...
Using the software pulser will allow each value of the count to be observed
...


Supplement to Experiment 2 (Section 9
...
In Section 3
...
As an
introduction to the laboratory Verilog program, compile the circuit described in HDL
Example 3
...
3
...

Assign the following delays to the exclusive‐OR circuit shown in Fig
...
32(a): 10 ns
for an inverter, 20 ns for an AND gate, and 30 ns for an OR gate
...

(a) Determine the signals at the output of each gate from t = 0 to t = 50 ns
...


484

Chapter 9

Laboratory Experiments

(c) Write a stimulus module (similar to HDL Example 3
...

(d) Implement the circuit with an FPGA and test its operation
...
5)
The operation of a combinational circuit is verified by checking the output and comparing it with the truth table for the circuit
...
10 (Section 4
...

(a) In order to get acquainted with this procedure, compile and simulate HDL
Example 4
...

(b) In Experiment 4, you designed a majority logic circuit
...
Compile and simulate the circuit and check the output response
...


Supplement to Experiment 5 (Section 9
...
A BCD‐to‐excess‐3 converter was designed
in Section 4
...
Use the result of the design to check it with an HDL simulator
...
4
...

Write a dataflow description using the Boolean expressions listed in Fig
...
3
...

Write a test bench to simulate and test the BCD‐to‐excess‐3 converter circuit in
order to verify the truth table
...

(e) Implement the behavioral description with an FPGA and test the operation of the
circuit
...
8)
A four‐bit adder–subtractor is developed in this experiment
...
5
...

(b) Write a behavioral description of the adder–subtractor circuit shown in Fig
...
11
...
4
...
This can be done by instantiating a modified version of the
four‐bit adder described in HDL Example 4
...
12)
...
Check and
verify the values that cause an overflow with V = 1
...


Section 9
...
9)
The edge‐triggered D flip‐flop 7474 is shown in Fig
...
13
...

(a) Write an HDL behavioral description of the 7474 D flip‐flop, using only the Q
output
...
Thus, Preset takes precedence over Clear
...

Label the second output Q_not, and note that this is not always the complement
of Q
...
)

Supplement to Experiment 9 (Section 9
...
9
...
This is a Mealy model sequential circuit similar to the
one described in HDL Example 5
...
6)
...
9
...

(b) Write the HDL structural description of the sequential circuit obtained from the
design
...
7 in Section 5
...
)
(c) Figure 9
...
18) shows a control state diagram
...
9 in
Section 5
...

(d) Write a behavioral model of the datapath unit, and verify that the interconnected
control unit and datapath unit operate correctly
...


Supplement to Experiment 10 (Section 9
...
9
...
This
circuit is similar to the one described in HDL Example 6
...
6), with two exceptions: The load input is enabled when equal to 0, and there are two inputs (P and T) that
control the count
...
Implement the counter
with an FPGA and test its operation
...
12)
A bidirectional shift register with parallel load is designed in this experiment by using
the 74195 and 74157 IC types
...
Assume that inputs J and K
are connected together to form the serial input
...


486

Chapter 9

Laboratory Experiments

(c) Obtain the HDL description of the four‐bit bidirectional shift register that has
been designed in this experiment
...

(d) Implement the circuit with an FPGA and test its operation
...
14)
This experiment investigates the operation of a random‐access memory (RAM)
...
2 in conjunction with HDL
Example 7
...

(a) Write the HDL description of IC type 74189 RAM, shown in Fig
...
18
...
Then read the stored numbers from
the two addresses to check whether the numbers were stored correctly
...


Supplement to Experiment 14 (Section 9
...
9
...

(b) Implement the shift register with an FPGA and test its operation
...
17)
A parallel adder with an accumulator register and a memory unit is shown in the block
diagram of Fig
...
23
...
The HDL structural description of this circuit can be obtained by
instantiating the various components
...
4 in Section 8
...
First, it is necessary to write
the behavioral description of each component
...
The block diagram of
the various components can be found from the list in Table 9
...
Write a test bench for
each model, and then write a test bench to verify the entire design
...


Supplement to Experiment 17 (Section 9
...
9
...
The multiplier
can be described in one of two ways: (1) by using the register transfer level statements
listed in part (b) of the figure or (2) by using the block diagram shown in part (a) of the

Section 9
...
The description of the multiplier in terms of the register transfer level (RTL)
format is carried out in HDL Example 8
...
7)
...
The structural description is
obtained by using the module description of each component and then instantiating
all the components to show how they are interconnected
...
5 for an
example
...
The 7483 is described with a solution to
Experiment 7(a), the 7474 with Experiment 8(a), the 74161 with Experiment 10,
and the 74194 with Experiment 14
...
Be sure to verify each structural unit before
attempting to verify the multiplier
...
Use the pulser described in the
supplement to Experiment 1
...
1

R E C TA N G U L A R ‐ S H A P E S Y M B O L S
Digital components such as gates, decoders, multiplexers, and registers are available
commercially in integrated circuits and are classified as SSI or MSI circuits
...
This standard, known as ANSI/IEEE Std
...

The standard uses a rectangular‐shape outline to represent each particular logic function
...
For example, the general qualifying symbol for a multiplexer is
MUX
...
Input lines are placed on the left and output lines are
placed on the right
...

The rectangular‐shape graphic symbols for SSI gates are shown in Fig
...
1
...
The OR gate has the qualifying symbol that designates greater than or equal to 1, indicating that at least one input
must be active for the output to be active
...
The exclusive‐OR symbol designates the fact that only
one input must be active for the output to be active
...
Although the
rectangular‐shape symbols for the gates are recommended, the standard also recognizes
the distinctive‐shape symbols for the gates shown in Fig
...
5
...
10
...
The qualifying symbol for an adder is the Greek letter ⌺
...
1

Rectangular‐Shape Symbols

&

Ն1

1

ϭ1

AND

OR

Buffer

XOR

&

Ն1

1

ϭ1

NAND

NOR

Inverter

489

XNOR

FIGURE 10
...
2
Standard graphic symbol for a four‐bit parallel adder, IC type 7483

letters for the arithmetic operands are P and Q
...
Thus, the input labeled 3 corresponds to the value of 23 = 8
...
When the digital component represented by the outline is also a commercial integrated circuit, it is customary
to write the IC pin number along each input and output
...
It is enclosed in a package with 16 pins
...
10
...
The other two pins are for
the power supply
...
As mentioned in Section 2
...
Negative logic assumes the opposite assignment
...
At any point in the circuit, the user is
allowed to define the logic polarity by assigning logic 1 to either the H or L signal
...
(See Fig
...
10(f)
...
When an input or output is considered in terms of positive logic, it is defined
as active high
...

Active‐low inputs or outputs are recognized by the presence of the small‐triangle polarity‐
indicator symbol
...
In
this book, we have assumed positive logic throughout and employed the small circle when
drawing logic diagrams
...
An input or output that includes the small‐circle symbol
is considered active if it is in the logic‐0 state
...
This will conform with integrated‐circuit data books, where the polarity symbol
is usually employed
...
 10
...

Another example of a graphic symbol for an MSI circuit is shown in Fig
...
3
...
Inputs are on the left
and outputs on the right
...
Data inputs A and B are assigned binary weights 1 and 2
equivalent to 20 and 21, respectively
...
The decoder has one active‐low
input E1 and one active‐high input E2
...
3
Standard graphic symbol for a 2‐to‐4‐line decoder (one‐half of IC type 74155)

Section 10
...
The output of the AND gate is labeled EN (enable) and is
activated when E1 is at a low‐level state and E2 at a high‐level state
...
2

QUALIFYING SYMBOLS
The IEEE standard graphic symbols for logic functions provide a list of qualifying symbols
to be used in conjunction with the outline
...
Table 10
...
A general qualifying symbol defines the basic function performed by the
device represented in the diagram
...
The general qualifying symbols for the gates, decoder, and adder were
shown in previous diagrams
...

Some of the qualifying symbols associated with inputs and outputs are shown in
Fig
...
4
...
Symbols associated with outputs are placed on the right side of the
column
...
As mentioned
Table 10
...
4
Qualifying symbols associated with inputs and outputs

Section 10
...
The
dynamic input is associated with the clock input in flip‐flop circuits
...
The three‐state output has
a third high‐impedance state, which has no logic significance
...
This state is equivalent to an open circuit
...
An
externally connected resistor is sometimes required in order to produce the proper logic
level
...
The high or low type specifies the logic level when the output is not in
the high‐impedance state
...
These outputs are recognized by a diamond‐shape symbol
with a bar under it
...
When used as part of a distribution function, two or more open‐
collector NAND gates when connected to a common resistor perform a positive‐logic
AND function or a negative‐logic OR function
...
Such gates are employed in components such as clock drivers or bus‐oriented
transmitters
...
It has the effect of enabling all
outputs when it is active
...
The symbols for flip‐flop inputs have the usual meaning
...

The symbols for shift right and shift left are arrows pointing to the right or the left,
respectively
...
An output designated by CT = 15 will be active when the contents
of the register reach the binary count of 15
...


10
...

Dependency notation is used to provide the means of denoting the relationship between
different inputs or outputs without actually showing all the elements and interconnections
between them
...

The AND dependency is represented with the letter G followed by a number
...
For example, if one input in the diagram has the label G1 and
another input is labeled with the number 1, then the two inputs labeled G1 and 1 are
considered to be ANDed together internally
...
10
...
In (a), we have a portion of
a graphic symbol with two AND dependency labels, G1 and G2
...
The equivalent

494

Chapter 10

Standard Graphic Symbols

X
Y
&
X

G1

Y

G2

A

1

B

1

C

2

A

&
B

&
(a) Block with G1 and G2
C

(b) Equivalent interpretation

FIGURE 10
...
Input X associated with G1 is considered
to be ANDed with inputs A and B, which are labeled with a 1
...

The standard defines 10 other dependencies
...
The letter appears at the input or output and is followed by a
number
...
The 11 dependencies and their corresponding letter designation are as follows:
G

Denotes an AND (gate) relationship

V

Denotes an OR relationship

N

Denotes a negate (exclusive-OR) relationship

EN

Specifies an enable action

C

Identifies a control dependency

S

Specifies a setting action

R

Specifies a resetting action

M

Identifies a mode dependency

A

Identifies an address dependency

Section 10
...
The EN dependency is
similar to the qualifying symbol EN except that a number follows it (for example, EN 2)
...

The control dependency C is used to identify a clock input in a sequential element
and to indicate which input is controlled by it
...
The C, S, and R dependencies
are explained in Section 10
...
The mode M
dependency is used to identify inputs that select the mode of operation of the unit
...
6 in conjunction with registers and counters
...
It is
introduced in Section 10
...

The Z dependency is used to indicate interconnections inside the unit
...
The X dependency is used to indicate the controlled
transmission path in a CMOS transmission gate
...
4

S Y M B O L S F O R C O M B I N AT I O N A L E L E M E N T S
The examples in this section and the rest of this chapter illustrate the use of the standard
in representing various digital components with graphic symbols
...
Most of the ICs presented in this chapter are included with the suggested
experiments outlined in Chapter 9
...
2
...
10
...
(The truth table of this
decoder is shown in Fig
...
7 There are two C and two G inputs in the IC
...
)
be connected together as shown in the diagram
...
The outputs are all active low
...
The outputs are assigned numbers from 0
to 7 The sum of the weights of the inputs determines the output that is active
...

two input lines with weights 1 and 4 are activated, the total weight is 1 + 4 = 5 and output
5 is activated
...

The decoder is a special case of a more general component referred to as a coder
...
Instead of using the qualifying symbol
X/Y, the coder can be specified by the code name
...
10
...


496

Chapter 10

Standard Graphic Symbols
X/Y

9
D0

0
A
B
C

13
3

1

2

2

1
15

G

10

1

12
4

3
7
4

2
14

11

EN

5
6

6

D1
D2
D3
D4
D5

5
D6
4

7

D7

FIGURE 10
...
The AND dependency is sometimes represented by
a shorthand notation like G 0
...
The active AND
gate is determined from the inputs associated with the G symbol
...
For the eight AND gates just listed,
the weights are 0, 1, and 2, corresponding to the numbers 20, 21, and 22, respectively
...
Thus, if inputs 0 and 2 are active, then the AND gate that
is active has the number 20 + 22 = 5
...

The standard graphic symbol for a 8 * 1 multiplexer is shown in Fig
...
7(a)
...
The symbols inside the
block are part of the standard notation, but the symbols marked outside are user‐
defined symbols
...
9
...
The AND
dependency is marked with G 0 and is associated with the inputs enclosed in brackets
...
They are actually what we have called the
selection inputs
...
The net
weight of the active inputs associated with the G symbol specifies the number in the
data input that is active
...
This gives a numerical value for the AND dependency
of 22 + 21 = 6, which makes G 6 active
...
Thus, the output will be equal to data input D6 provided that
the enable input is active
...
5

Strobe
S
A
B
C

7
11

MUX

G

0
7

A1

2

B1
D0
D1
D2
D3
D4
D5
D6
D7

4
3
2
1
15
14
13
12

1

497

EN
G1

0

10
9

Select

EN

15

Symbols for Flip‐Flops

0
1
2

5
6

Y
W

A2
B2

3

2
3

5

MUX
1

4

7

6

A3

11

B3

10

4

Y1

1

9

Y2

Y3

5
6
7

A4
B4

(a) IC type 74151 8 ϫ 1 MUX

14

12

13

Y4

(b) IC type 74157 quadruple 2 ϫ 1 MUX

FIGURE 10
...
7(b) represents the quadruple 2 * 1 multiplexer IC type 74157 whose function table is listed in Fig
...
17
...
This is indicated in the standard notation by the indented box at the top
of the diagram, which represents a common control block
...
The common enable input EN
is active when in the low‐level state
...
When G1 = 0, the A inputs marked with 1 are active
...
The active inputs are applied to
the corresponding outputs if EN is active
...


10
...
10
...

A flip‐flop is represented by a rectangular‐shaped block with inputs on the left and
outputs on the right
...
8
Standard graphic symbols for flip‐flops

other output with a small‐circle negation symbol (or polarity indicator) designates the
complement output
...
6
...
6
...
6
...
The graphic
symbol for the D latch or D flip‐flop has inputs D and C indicated inside the block
...
The notation C1, 1D,
1J, and 1K are examples of control dependency
...

The D latch has no other symbols besides the 1D and C1 inputs
...
The dynamic indicator symbol denotes that the flip‐flop
responds to the positive‐edge transition of the input clock pulses
...
The master–slave is considered to be a pulse‐triggered flip‐flop and is

Section 10
...
9
IC flip‐flops with direct set and reset

indicated as such with an upside‐down L symbol in front of the outputs
...
Note that the master–
slave flip‐flop is drawn without the dynamic indicator
...
These inputs are usually called direct set and
direct reset
...
The graphic symbol of a master–slave JK flip‐flop with direct set and reset is
shown in Fig
...
9(a)
...
S and R have no 1 in front of
the letters and, therefore, they are not controlled by the clock at C1
...
The function table for the 7476 flip‐flop is shown in Fig
...
12
...
10
...
The positive‐edge transition of the clock at input C1 controls
input 1D
...
This is IC type 7474, whose
function table is listed in Fig
...
13
...
6

SYMBOLS FOR REGISTERS
The standard graphic symbol for a register is equivalent to the symbol used for a group
of flip‐flops with a common clock input
...
10
...

The clock input C1 and the clear input R appear in the common control block
...
The notation C1 is the control dependency that controls all the
1D inputs
...
The dynamic
input symbol associated with C1 indicates that the flip‐flops are triggered on the positive
edge of the input clock
...
The 1D symbol is placed only once in the upper section instead of

500

Chapter 10

Standard Graphic Symbols

Clear
Clock

1
9

R
C1

2
4

1D

3

Q
QЈ

7
5
6

10
12
11

15
13
14

FIGURE 10
...
The complement outputs of the flip‐flops in this diagram
are marked with the polarity symbol rather than the negation symbol
...
  10
...
This is IC type 74195, whose function table can be found in Fig
...
16
...
Thus, SRG4 denotes a four‐bit shift register
...
Note that the IC has a single input labeled SH/LD (shift/load), which is split into
two lines to show the two modes
...
M2 is recognized as active low from the polarity
indicator along its input line
...
The control dependency C3 is for the clock input
...
The symbol /1 S following C3 indicates that the register shifts to the
right or in the downward direction when mode M1 is active
...
Flip‐
flop QA has three inputs: Two are associated with the serial (shift) operation and one

Section 10
...
11
Graphic symbol for a shift register with parallel load, IC type 74195

with the parallel (load) operation
...
The other serial input with label 1, 3K has a polarity symbol in its input line
corresponding to the complement of input K in a JK flip‐flop
...
Each input is denoted
by the label 2, 3D
...
If the input in pin
number 9 is in the low level, M1 is active, and a positive transition of the clock at C3
causes a parallel transfer from the four inputs, A through D, into the four flip‐flops, QA
through QD
...

It is assumed to be in the other two sections below
...
12 shows the graphic symbol for the bidirectional shift register with parallel load, IC type 74194
...
9
...
The common
control block shows an R input for resetting all flip‐flops to 0 asynchronously
...

This is indicated by the symbol M 0 , which stands for M0, M1, M2, M3, and is similar
3
to the notation for the G dependency in multiplexers
...
The /1 S symbol indicates that the register
shifts right (down in this case) when the mode is M1 (S1 S0 = 10)
...
12
Graphic symbol for a bidirectional shift register with parallel load, IC type 74194

indicates that the register shifts left (up in this case) when the mode is M2 (S1 S0 = 10)
...

The sections below the common control block represent the four flip‐flops
...
The last flip‐flop has a serial input for shift left, denoted by 2, 4D (mode M2,
clock C4, input D)
...
Thus, M3 (S1 S0 = 11) is for parallel load
...


10
...
10
...
The
qualifying symbol for a ripple counter is RCTR
...
The DIV8 designation
is for the divide‐by‐8 counter obtained from the other three flip‐flops
...
9
...
The common control block has an internal AND gate, with inputs R1 and R2
...
This is indicated by

Section 10
...
13
Graphic symbol for ripple counter, IC type 7493

the symbol CT = 0
...

The dynamic symbol next to the + together with the polarity symbol along the input
line signify that the count is affected with a negative‐edge transition of the input signal
...
Thus, 0 represents the value of 20 = 1 and 2 represents the value 22 = 4
...
10
...
The qualifying symbol for a synchronous counter is CTR followed
by the symbol DIV16 (divide by 16), which gives the cycle length of the counter
...
M1 is active
when the load input at pin 9 is low and M2 is active when the load input at pin 9 is high
...
The count‐
enable inputs use the G dependencies
...
The label associated with the clock is
C5>2, 3, 4 +
This means that the circuit counts up (the + symbol) when M2, G3, and G4 are active
(load = 1, ENT = 1, and ENP = 1) and the clock in C5 goes through a positive transition
...
9
...
The parallel inputs have the label 1, 5D, meaning that the D inputs are active when M1 is active
(load = 0) and the clock goes through a positive transition
...
Note that the outputs

504

Chapter 10

Standard Graphic Symbols

Clear
Load

1
9

CTR DIV16
CT ϭ 0
M1
M2

ENT
ENP
Clock

A
B
C
D

10
7
2

3
4
5
6

3CT ϭ 15

G3

15

Output carry

G4
C5/2, 3, 4 ϩ

1, 5D

[1]
[2]
[4]
[8]

14
13
12
11

QA
QB
QC
QD

FIGURE 10
...

The polarity symbol in the C5 input designates an inverted pulse for the input clock
...
Thus, the output changes on the positive transition of the clock pulse
...


10
...
10
...
The numbers 16 * 4 that follow the qualifying symbol RAM designate
the number of words and the number of bits per word
...
Each bit of the word is shown in
a separate section with an input and output data line
...
Data inputs and outputs affected
by the address are labeled with the letter A
...
The inverted triangle signifies
three‐state outputs
...

The operation of the memory is specified by means of the dependency notation
...
Input G1 is to be considered ANDed with 1EN and 1C2 because G1 has a
1 after the letter G and the other two have a 1 in their label
...
15
Graphic symbol for 16×4 RAM, IC type 74189

to identify an enable input that controls the data outputs
...
Thus, for a write operation, we have the G1 and
1C2 dependency (CS = 0), the C2 and 2D dependency (WE = 0), and the A dependency,
which specifies the binary address in the four address inputs
...
The interpretation of these dependencies results in the operation of the memory
as listed in the function table of the 74189 RAM (see Web Search Topics)
...
1

Figure 9
...
Using this
information, draw the rectangular‐shaped graphic symbols for the 7400, 7404, and 7486 ICs
...
2

Define the following in your own words:
(a) Positive and negative logic
...

(e) Dependency notation
...

(d) Dynamic indicator
...
3

Show an example of a graphic symbol that has the three Boolean dependencies—G, V,
and N
...


10
...
This is similar to a decoder with
4 inputs and 10 outputs
...
5

Draw the graphic symbol for a binary‐to‐octal decoder with three enable inputs, E1, E2,
and E3
...


10
...


10
...

(b) Master–slave RS flip‐flop
...


10
...


10
...


10
...
10
...


10
...
Show the output carries
for the up count and the down count
...
12

Draw the graphic symbol of a 256 * 1 RAM
...


REFERENCES
1
...

3
...


IEEE Standard Graphic Symbols for Logic Functions (ANSI/IEEE Std
...
1984
...

Kampel, I
...
A Practical Introduction to the New Logic Symbols
...

Mann, F
...
1984
...
Dallas: Texas Instruments
...
1985
...


WEB SEARCH TOPICS
Bidirectional shift register
Three-state inverter
Three-state buffer
Universal shift register
7483 adder
74151 multiplexer
74155 decoder
74157 multiplexer
7476 flip-flop
7474 flip-flop

74161 flip-flop
74194 shift register
74175 quad flip-flops
74195 shift register
7494 counter
74161 counter
74LS161 flip-flop
74189 RAM
BCD-to-decimal decoder
Random access memory

Appendix

Semiconductors and CMOS
Integrated Circuits

Semiconductors are formed by doping a thin slice of a pure silicon crystal with a small
amount of a dopant that fits relatively easily into the crystalline structure of the silicon
...
A silicon crystalline structure is such that each silicon
atom shares its four valence electrons with its four nearest neighbors, thereby completing
its valence structure
...
Consequently, an applied
electric field can cause such electrons to flow as a current
...
Under
the influence of an applied electric field, an electron from a neighboring silicon atom in
the bonded structure can jump from its host and fill a vacant dopant site, leaving behind
a vacancy at its host
...

Current is due to the movement of electrons, which are negative charge carriers
...
(Think of current as being the motion of an equivalent
positive charge moving in the opposite direction of an electron, whose charge is negative)
...
Thermal agitation causes both types of charge
carriers to be present in a semiconductor
...
Bipolar transistors rely on both types of carriers
...
The
type and relative amount of dopant determine the type of a semiconductor material
...
1
Basic structure of MOS transistor

The basic structure of a metal‐oxide semiconductor (MOS) transistor is shown in
Fig
...
1
...
Two regions are heavily doped with p‐type impurities by a diffusion process to form the source and drain
...
The region
between the two p‐type sections serves as the channel
...

A negative voltage (with respect to the substrate) at the gate terminal causes an induced
electric field in the channel that attracts p‐type carriers (holes) from the substrate
...

There are four basic types of MOS structures
...
The mode of operation can
be enhancement or depletion, depending on the state of the channel region at zero gate
voltage
...
In this mode, current flows unless the
channel is depleted by an applied gate field
...
Thus,
the channel current is enhanced by the gate voltage, and such a device is said to operate
in the enhancement mode
...
If
the majority carrier is a hole (p‐type channel), the source terminal supplies current to
the circuit; if the majority carrier is an electron (n‐type channel), the source removes
current from the circuit
...
In a p‐channel MOS, the source terminal is connected to the substrate
and a negative voltage is applied to the drain terminal
...
When the gate voltage is sufficiently negative below
VT, a channel is formed and p‐type carriers flow from source to drain
...


Appendix

Semiconductors and CMOS Integrated Circuits
D

drain
gate

substrate

G

source
(a) p-channel

S

D

drain
gate

substrate
source

509

G
S

(b) n-channel

FIGURE A
...
When the gate voltage is below the
threshold voltage VT (about 2 V), no current flows in the channel
...
n‐type carriers are negative and correspond to a positive current flow
from drain to source
...

The graphic symbols for the MOS transistors are shown in Fig
...
2
...
In this symbol, the substrate can be identified and is shown connected to the
source
...

Because of the symmetrical construction of source and drain, the MOS transistor can
be operated as a bilateral device
...

One advantage of the MOS device is that it can be used not only as a transistor, but
as a resistor as well
...
The ratio of the source–drain voltage to the channel
current then determines the value of the resistance
...

Three logic circuits using MOS devices are shown in Fig
...
3
...
The two voltage levels are a function of the threshold voltage VT
...
The n‐channel
gates usually employ positive logic
...
The two voltage levels are
both negative above and below the negative threshold voltage VT
...

The inverter circuit shown in Fig
...
3(a) uses two MOS devices
...
The load‐resistor MOS has its gate connected to VDD,

510

Appendix

Semiconductors and CMOS Integrated Circuits
VDD

VDD
VDD
Y ϭ (AB)Ј
Q1

A
Y ϭ (A ϩ B)Ј
Y ϭ AЈ
A

A

Q2

(a) Inverter

B

B

(b) NAND gate

(c) NOR gate

FIGURE A
...
When the input voltage is low (below VT ), Q2
turns off
...
When the input voltage
is high (aboveVT ), Q2 turns on
...
The geometry of the two MOS devices must be such that the resistance of Q2,
when conducting, is much less than the resistance of Q1 to maintain the output Y at a
voltage below VT
...
A
...
Inputs A and B must
both be high for all transistors to conduct and cause the output to go low
...
Again, the series
resistance formed by the two active MOS devices must be much less than the resistance
of the load‐resistor MOS
...
A
...

If either input is high, the corresponding transistor conducts and the output is low
...


A
...
CMOS circuits consist
of both types of MOS devices, interconnected to form logic functions
...
A
...
The source terminal of the p‐channel device is at
VDD, and the source terminal of the n‐channel device is at ground
...
1

Complementary MOS

511

VDD

VDD
Y ϭ (AB)Ј
p
A
Y ϭ AЈ

A

n
B

(a) Inverter

(b) NAND gate

VDD

A

B

Y ϭ (A ϩ B)Ј

(c) NOR gate

FIGURE A
...
The two voltage levels are 0 V for the low level
and VDD for the high level (typically, 5 V)
...
The n‐channel MOS conducts when its gate‐to‐source voltage is positive
...
The p‐channel MOS conducts when its gate‐to‐source voltage is negative
...
Either type of device is turned off if its gate‐to‐source voltage is zero
...
When the input is low, both gates are at
zero potential
...
The result is that the p‐channel
device is turned on and the n‐channel device is turned off
...
Therefore, the output voltage approaches the high level VDD under
normal loading conditions
...
The result is
that the output approaches the low level of 0 V
...
A
...
A two‐input NAND gate consists
of two p‐type units in parallel and two n‐type units in series, as shown in Fig
...
4(b)
...
The output has a low impedance to ground and produces a low state
...
The output is coupled to VDD and goes to the high state
...
A
...

A two‐input NOR gate consists of two n‐type units in parallel and two p‐type units in
series, as shown in Fig
...
4(c)
...
The output is coupled to VDD and goes to the high state
...

MOS transistors can be considered to be electronic switches that either conduct
or are open
...
A
...
Applying a low voltage to the input causes the upper
switch (p) to close, supplying a high voltage to the output
...

Thus, the output Vout is the complement of the input Vin
...
The arrows showing the direction of current flow are omitted
...
The inverter circuit
is redrawn with these symbols in Fig
...
5(b)
...
A logic 1 in the input enables the
lower transistor, making the output logic 0
...
1

Complementary MOS

513

VDD ϭ 5 V
VDD

Vin

Vout
A

(a) Switch model

Y

(b) Logical model

FIGURE A
...
This is
because at least one transistor is always off in the path between the power supply and
ground when the state of the circuit is not changing
...
01 mW
...

CMOS logic is usually specified for a single power‐supply operation over a voltage
range from 3 to 18 V with a typical VDD value of 5 V
...
The propagation delay time with VDD = 5 V ranges
from 5 to 20 ns, depending on the type of CMOS used
...
The fan‐out of CMOS gates is about 30 when they are
operated at a frequency of 1 MHz
...

There are several series of the CMOS digital logic family
...
For example, CMOS
IC type 74C04 has six inverters with the same pin configuration as TTL type 7404
...
The 74HCT series is electrically compatible with TTL ICs
...
Newer versions of CMOS are the
high‐speed series 74VHC and its TTL‐compatible version 74VHCT
...
Thus, more circuits can be placed on a given area of silicon at a reduced
cost per function
...


514

Appendix

Semiconductors and CMOS Integrated Circuits

A
...
The transmission gate is essentially an electronic switch that is controlled by an input logic level
...

Figure A
...
Whereas a CMOS
inverter consists of a p‐channel transistor connected in series with an n‐channel transistor, a transmission gate is formed by one n‐channel and one p‐channel MOS transistor
connected in parallel
...
When the N gate is at VDD and the P gate is at ground, both transistors
conduct and there is a closed path between input X and output Y
...
Figure A
...
Note
that the terminal of the p‐channel gate is marked with the negation symbol
...
4(c)
demonstrates the behavior of the switch in terms of positive‐logic assignment with VDD
equivalent to logic 1 and ground equivalent to logic 0
...
A
...
This
type of arrangement is referred to as a bilateral switch
...
When C = 1, the
N

N

X

Y

Y

TG

X

VDD

P

P

(a)

(b)

Closed switch
X

Nϭ1
Pϭ0

Open switch
X

Y

(c)

FIGURE A
...
2

CMOS Transmission Gate Circuits

515

C

X

Y

TG

FIGURE A
...
When C = 0, the switch is open,
disconnecting the path between X and Y
...
To demonstrate its
usefulness as a component in the CMOS family, we will show three examples
...
A
...
Input A controls the paths in the transmission gates and
input B is connected to output Y through the gates
...
When input A is equal to 1,
TG2 is closed and output Y is equal to the complement of input B
...
A
...

Another circuit that can be constructed with transmission gates is the multiplexer
...
 A
...
The TG circuit provides a transmission path between its horizontal input and
A

B

TG1
A
Y

TG2

FIGURE A
...
9
Multiplexer with transmission gates

output lines when the two vertical control inputs have the value of 1 in the uncircled terminal and 0 in the circled terminal
...
The two selection inputs, S1and S0,
control the transmission path in the TG circuits
...
Thus, if S0 = 0 and S1 = 0, there is a closed
path from input I0 to output Y through the two TGs marked with S0 = 0 and S1 = 0
...


Section A
...
10
Gated D latch with transmission gates

The level‐sensitive D flip‐flop commonly referred to as the gated D latch can be
constructed with transmission gates, as shown in Fig
...
10
...
When C = 1, the TG connected to input D has a closed path
and the one connected to output Q has an open path
...
Thus, the output follows the data input as long as C remains active
...
Thus, the value that was present at input D at the time
that C went from 1 to 0 is retained at the Q output
...
A
...
The first circuit is the master and the second is the slave
...


A
...
By definition,
CMOS is a complementary connection of an NMOS and a PMOS transistor
...

By specifying the connections among MOS switches, the designer can describe a digital
circuit constructed with CMOS
...

The two types of MOS switches are specified in Verilog HDL with the keywords nmos
and pmos
...
A
...


518

Appendix

Semiconductors and CMOS Integrated Circuits

The connections to a power source (V ) and to ground must be specified when MOS
DD
circuits are designed
...
They are specified, for example, with the following statements:
supply1 PWR;
supply0 GRD;
Sources of type supply1 are equivalent to V and have a value of logic 1
...

The description of the CMOS inverter of Fig
...
4(a) is shown in HDL Example A
...

The input, the output, and the two supply sources are declared first
...
The output Y is common to both transistors
at their drain terminals
...
The source terminal of the PMOS transistor is connected to PWR and the
source terminal of the NMOS transistor is connected to GRD
...
1
// CMOS inverter of Fig
...
4(a)
module inverter (Y, A);
input A;
output Y;
supply1 PWR;
supply0 GRD;
pmos (Y, PWR, A);
// (Drain, source, gate)
nmos (Y, GRD, A);
// (Drain, source, gate)
endmodule

The second module, set forth in HDL Example A
...
A
...
There are two PMOS transistors connected in parallel,
with their source terminals connected to PWR
...
The drain of the first NMOS is
connected to the output, and the source of the second NMOS is connected to GRD
...
2
// CMOS two-input NAND of Fig
...
4(b)
module NAND2 (Y, A, B);
input A, B;
output Y;
supply1 PWR;
supply0 GRD;
wire W1;
// terminal between two nmos
pmos (Y, PWR, A);
// source connected to Vdd
pmos (Y, PWR, B);
// parallel connection

Section A
...
It has an
output, an input, and two control signals, as shown in Fig
...
6
...
The relevant code is as follows:
cmos (output, input, ncontrol, pcontrol); // general description
cmos (Y, X, N, P); // transmission gate of Fig
...
6(b)
Normally, ncontrol and pcontrol are the complement of each other
...
Transmission gates are useful for building multiplexers and flip‐
flops with CMOS circuits
...
3 describes a circuit with cmos switches
...
A
...
The two inverters are instantiated within the module describing a CMOS inverter
...
A test
module is included to test the circuit’s operation
...
The output of the simulation is as follows:
A
A
A
A

=
=
=
=

0
0
1
1

B
B
B
B

=
=
=
=

0
1
0
1

Y
Y
Y
Y

=
=
=
=

0
1
1
0

HDL Example A
...
A
...
A
...
2

(a) 32,768

(b)

1
...
5

(a) 6

1
...
7

(62315)8

1
...
3125 (all three)

1
...
19

(a) 010087

1
...
29

Steve Jobs

1
...
32

bit 6 from the right

1
...
2

(a) x

(b)

x

y

2
...
4

(a) AB + CЈ

2
...
11

F(x, y, z) = ⌺(1, 4, 5, 6, 7)

2
...
14

(b) (xЈ + yЈ)Ј + (x + y)Ј + (y + zЈ)Ј

2
...
17

(a) ⌺(3, 5, 6, 7) = ⌸(0, 1, 2, 4)

2
...
19

⌺(1, 3, 5, 7, 9, 11, 13, 15) = ⌸(0, 2, 4, 6, 8, 10, 12, 14)

2
...
1

(a)

xyЈ + xЈzЈ

3
...
3

(a)

xy + xЈzЈ

3
...
5

(a)

xzЈ + wЈyЈz + wxy

3
...
7

(a)

xЈy + z

3
...
9

(a) Essential: xz and xЈzЈ; Nonessential: wЈx and wЈzЈ

3
...
11

(a) F = AЈBЈDЈ + ADЈE + BЈCЈDЈ

3
...
13

(a) F = xy + zЈ = (x + zЈ)(y + zЈ)

3
...
17

FЈ = ACЈ + BCЈ + BD

3
...
30

F = (A { B)(C { D)

3
...

Line 1: Dash not allowed, use underscore: Exmpl_3
...

Line 2: inputs should be input (no s at the end)
...
Output is declared but does not
appear in the port list, and should be followed by a comma if it is intended to be in the list of inputs
...

Line 3: B cannot be declared as input (Line 2) and output (Line 3)
...

Line 4: A cannot be an output of the primitive if it is an input to the module
Line 5: Too many entries for the not gate (only two allowed)
...

Line 7: endmodule is mispelled
...


CHAPTER 4
4
...
2

F = ABC + AЈD
G = ABC + AЈDЈ

4
...
4

(a) F = xЈyЈ + xЈzЈ

4
...
7

(a) w = A

4
...
10

Inputs: A, B, C, D; Outputs: w, x, y, z
z = D
y = C{D
x = B { (C + D)
w = A { (B + C + D)

4
...
13

Sum
1101
0001
0100
1011
1111

(a)
(b)
(c)
(d)
(e)
4
...
18

C
0
1
1
0
0

w = AЈBЈCЈ
x = B{C
y = C
z = DЈ

4
...
28

(a)

F1 = ⌺(0, 5, 7)
F2 = ⌺(2, 3, 4)
F3 = ⌺(1, 6, 7)

4
...
34

F(A, B, C, D) = ⌺(1, 6, 7, 9, 10, 11, 12)

4
...
39
4
...

(c) The HDL description is available on the Companion Website
...
50

The HDL description is available on the Companion Website
...
56

assign match = (A == B);

4
...


// Assumes reg [3: 0] A, B;

CHAPTER 5
5
...
7

S = x{y{Q
Q(t + 1) = xy + xQ + yQ

5
...
9

(a)

A(t + 1) = xAЈ + AB
B(t + 1) = xBЈ + AЈB

5
...
11

Present state:

00 00 01 00 01 11 00 01 11 10 00 01 11 10 10

Input:

0 0 1 0 0 1 0 0 0 1 0 0 0 0 1

Next state:
5
...
15

(a) State:
Input:
Output:

afbcedghggha
01110010011
01000111010

(b) State:
Input:
Output:

5
...
16

DA = AxЈ + Bx
DB = AЈx + BxЈ

5
...
19

(a) DA = AЈBЈx_in
DB = A + CЈx_inЈ + BCx_in
DC = Cx_inЈ + Ax_in + AЈBЈx_inЈ
y_out = AЈx_in

5
...
23

RegB = 30

(a)
Q(t + 1) = JQЈ + KЈQ
When Q = 0, Q(t + 1) = J
When Q = 1, Q(t + 1) = KЈ
module JK_Behavior (output reg Q, input J, K, CLK);
always @ (posedge CLK)
if (Q == 0)
Q <= J;
else
Q <= ~K;
endmodule

5
...

Note: The statements must be written in an order that produces the effect of concurrent assignments
...
4

0110; 0011; 0001; 1000; 1100; 1110; 0111; 1011

6
...
Carry = 1, 1, 1, 0

6
...
14

(a) 4

6
...
3 MHz

6
...
17

DA0 = A0 { E
DA1 = A1 { (A0E)
DA2 = A2 { (A1A0E)
DA3 = A3 { (A2A1A0E)

6
...
21

JA0 = LI0 + LЈC
=
KA0 = LI0 + LЈC

6
...
26

The clock generator has a period of 12
...
Use a 2‐bit counter to count four pulses
...
28

DA = A { B
DB = ABЈ + C
DC = AЈBЈCЈ

6
...
Simulations results
for Problem 6
...
35

(b) The HDL description is available on the Companion Website
...
37

The HDL description is available on the Companion Website
...
38

(a) The HDL description is available on the Companion Website
...
42

Because A is a register variable, it retains whatever value has been assigned to it
until a new value is assigned
...


6
...
Simulations results
for Problem 6
...
50

(b) The HDL description is available on the Companion Website
...
50 follow:

0

30

60

90

reset_b
clock
count[2: 0]

0

1

2

4

6

0

1

2

CHAPTER 7
7
...
3

Address: 1 0001 1011 = 011B (hex)

(b)

231

(c)

226

Data: 100 1011 1100 = 4BC (hex)

(d)

221

4

6

0

1

Answers to Selected Problems
7
...
8

(a) 8 chips

7
...
11

101 110 011 001 010

7
...
13

(a) 6

7
...
16

24 pins

7
...
25

x = 46; y = 112

0001 1011 1011 1

A = yzЈ + xzЈ + xЈyЈz

(b)

(b)

18; 15

(b)
7

(c)

(c)

(b)

529

3 * 8 decoder

1100 0110;

(c)

1111 0100

7

B = xЈyЈ + yz + yЈzЈ
C = A + xyz
D = z + xЈy

CHAPTER 8
8
...
e
...

After the transfer, R2 holds the contents that were in R1 before the clock
edge, and R2 holds its previous value incremented by 1
...

(c) If (S1 = 1), transfer content of R1 to R0
...


8
...

S1: 5 Carry, RA 6 d RA + (2>s complement of RB), go to S2
...
If (borrow = 1) then RA d (2>s complement
of RA), go to S0
...

Reg_B

...


done

Reg_A <= data_A
Reg_B <= data_B

1

S2

8
borrow
result

Reg_A <= ~Reg_A + 1

1
Convert

The HDL description is available on the Companion Website
...
7 follow:
Name

40

0

80

120

clock
reset_b
state[1: 0]

0

x

0

1

2

0

1

2

0

1

14

e2

1e
50

32

2

0

1

start
Load_A_B
Subtract
carry
borrow
Convert
data_A[7: 0]
RA[7: 0]
data_B[7: 0]
RB[7: 0]
done
borrow
result[7: 0]

50
00

20
32

1e

20
00

0

14

50

50
00

32

0

50

32

30

20 226 30

50

2

Answers to Selected Problems
8
...

S1: if (AR [15]) = 1(sign bit negative) then CR d AR (shifted right, sign
extension)
...

AR_eq_0
AR_gt_0

data_AR data_BR
16

AR_lt_0

16

Datapath
Ld_AR_BR

AR

...


...
Simulations results
for Problem 8
...
9

50

50

data_BR[15: 0]
BR[15: 0]

20

0

0064

0000

0

100

0

40

65526
fff6
10

65534
fffe
2

Design equations:
DS_idle = S_2 + S_idle Start'
DS_1 = S_idle Start + S_1(A2 A3)'
DS_2 = A2 A3 S_1
The HDL description is available on the Companion Website
...
9 follow:

Answers to Selected Problems
Name

0

60

120

533

180

240

reset_b
clock
Start
A2
A3
state[2: 0]

1

2

1

2

4 1

2

set_E
clr_E
set_F
clr_A_F
incr_A
A[3: 0]
E
F

8
...
16

RTL notation:
s0: (initial state) If start = 0 go back to state s0, If (start = 1) then
BR d multiplicand, AR d multiplier, PR d 0, go to s1
...

The internal architecture of the datapath consists of a double‐width register to
hold the product (PR), a register to hold the multiplier (AR), a register to hold
the multiplicand (BR), a double‐width parallel adder, and single‐width parallel
adder
...
Adding a word consisting entirely of 1s to the multiplier
accomplishes the 2’s complelment subtraction of 1 from the multiplier
...
16 (a) below shows the ASMD chart, block diagram, and controller of othe
circuit
...
16 (b) shows the internal architecture of the datapath
...
16 (c) shows the results of simulating the circuit
...

BR

...


1
reset_b
clock

16
PR

Note: Form Zero as the output of an OR gate whose inputs
are the bits of the register AR
...


All 0’s
32

BR

Add_decr

32

16

1
0
mux
16

Ld_regs

Note: all registers have active-low
asynchronous reset

32

16

data_AR

16

1
0
mux

PR

...



...

16

16

mux
0
1

AR

Ld_regs
32

mux
1
0

0
Add_decr

16
All 1’s
(b) Datapath

Name

0

40

80

120

160

200

reset_b
clock

start
Ld_regs
Add_decr
zero

state
data_AR[7: 0]

5

data_BR[7: 0]

20

AR[7: 0]

0

BR[7: 0]
done

0

PR[15: 0]

3

4
9

5

4

3

2

1

0

4

3

20

0

20 40 60 80

2

1

0

4

36

0

9

100

(c) Simulation results

0

9

18 27

536

Answers to Selected Problems
8
...
18

(a) The maximum product size is 32 bits available in registers A and Q
...

(c) Z (zero) detection is generated with a 5‐input NOR gate
...
20

2(n + 1)t

8
...
30

(a) E = 1

8
...

A * B = 1100
A ͉ B = 0110
A + B = 1000 A ¿B = 0100
A - B = 0100
ෂC = 1111
A & B = 0010

(b)

E = 0

A && C = 0
͉ A = 1
&A = 0 A 6 B = 0
A 7 B = 1
ෂ͉ C = 1
A != B = 1
A ͉͉ B = 1

Add_regs

1
Shift_left

Answers to Selected Problems

537

8
...


Ld_regs
Add_decr
Start

16


...


done

BR
PR

16

reset_b
Clock
PR

reset_b

S0
done

AR Ͻϭ data_A
BR Ͻϭ data_B
PR Ͻϭ 0

Start
1
Ld_regs
S1

PR Ͻϭ PR ϩ BR
AR Ͻϭ AR Ϫ 1
1
Add_decr

Zero

The HDL description is available on the Companion Website
...
39 follow:

538

Answers to Selected Problems
Name

0

30

60

90

120

reset_b
clock
start
Ld_regs
Add_decr
zero
state
data_AR[7: 0]

5

data_BR[7: 0]

20

AR[7: 0]

0

BR[7: 0]

0

5
20

3

4
9

4 0

5

4

3

2

0

1

0

80

100

20

done
PR[15: 0]

0

0

20

40

60

Index

A
ABEL, 332
Absorption theorem, 45
Abstract behavioral model, 109
Adders and subtractors (experiment)
adder–subtractor (four-bit), 456–457
full adder, 455
half adder, 455
magnitude comparator, 457
parallel adder, 455–456
Additive identity, 40
Algebraic manipulation, of Boolean
function, 48–49
Algorithmic state machine and
datapath (ASMD) charts,
370–371
controller and datapath hardware
design, 376
control logic, 379–381, 396, 398
design examples, 371–381
register transfer representation,
377–378
state table, 378–379
timing sequence, 374–376
Algorithmic state machines (ASMs),
363–371
algorithmic state machine and
datapath (ASMD) charts,
370–371
design examples, 371–381
binary code assignment, 365–366
block, 368–369

chart, 365–368
conditional box and examples, 367
control logic, 364
control unit, 364
datapath unit, 364
decision box of an ASM chart, 366
Mealy-type signals, 366–368
simplifications, 369
state and decision boxes of, 366
style of state box, 365–366
timing considerations, 369–370
always block, 358
always statement, 164, 176, 217, 219, 228,
290, 354–355, 382
American Standard Code for
Information Interchange
(ASCII), 24–26
Analog-to-digital converter, 2
ANDed with an expression, 53
AND gate, 30, 32–33, 42, 46–47, 50,
57–58, 60, 65, 90, 113, 321, 323
ANDing of maxterms, 55
AND-invert graphic symbol, 92
AND-invert symbol, 90–91
AND–NOR diagrams, 98–99
AND–OR diagrams, 90, 98–99
AND–OR–INVERT function,
97–98
Application-specific integrated circuit
(ASIC), 68
Arithmetic addition, 39
Arithmetic operations, 5

ASCII NAK (negative acknowledge)
control character, 27
assign statement, 115, 164, 171, 228,
354–355, 361
Associative law, 39
algebraic proofs of, 45
Asynchronous sequential circuit, 191

B
Backspace (BS) control, 26
Base-r system, 4, 10
Base-8 system, 4
BCD adder, 144–146
BCD code, 22–23
BCD ripple counter, 269–271
BCD synchronous counter, 275
begin keyword, 115, 177, 217
Behavioral modeling, 174–176
Bidirectional shift register, 264, 352
Bilateral switch, 514–515
Binary adder–subtractor, of
combinational circuits, 133–144
binary adder, 136–138
binary subtractor, 141–142
carry propagation, 138–141
full adder, 135–136
half adder, 134
overflow, 143–144
Binary and decimal numbers
(experiment)
BCD count, 444–445
binary count, 443

539

540

Index

Binary and decimal numbers (cont
...
)
&&, 171
∑, 53
* /, 111
+, 171
/ *, 111
= =, 171
@, 174–175, 354, 425–426
^, 171
|, 171
“| ” , 174
–, 171
?:, 171
(&), (/), and (~), 115
⊕, 58
active-low input or output, 492
adder (∑), 491
AND gate or function (&), 491
arithmetic logic unit (ALU), 491
arithmetic operators (+, –, *, /), 356
buffer gate or inverter, 491
coder, decoder, or code converter
(X/Y), 491
for combinational elements, 495–497
contents of register equals binary
15, 492
countdown, 492
counter (CTR), 491
for counters, 502–504
countup, 492
data input to a storage element, 492
demultiplexer (DMUX), 491
for digital logic circuits, 32
dynamic indicator input, 492
enable input, 492
even function or even parity element
(2k), 491
exclusive-OR gate or function
(=1), 491
exponentiation operator (**), 356
flip-flop inputs, 492
for flip-flops, 497–499
logic negation input or output, 492
magnitude comparator (COMP), 491
of MOS transistor, 509
multiplexer (MUX), 491
multiplier (∏), 491
odd function or odd parity element
(2k+1), 491
open-collector output, 492
OR gate or function (≥1), 491
output with special amplification, 492
(∏), 55
for RAM, 504–505
random-access memory (RAM), 491
read-only memory (ROM), 491

for registers, 499–502
ripple counter (RCTR), 491
semicolon (;), 112, 174
shift left, 492
shift register (SRG), 491
shift right, 492
slashes ( // ), 111
three-state output, 492
Verilog HDL operators, 356
Synchronous counter:
BCD, 275
binary, 271–272
with parallel load, 276–278
up–down, 272–275
HDL for, 287–288
Synchronous sequential circuit, 191
Synchronous sequential logic:
clocked sequential circuits, analysis
of, 204–217
design of, 236–245
D flip-flops, analysis of, 210
flip-flop input equations, 209–210
JK flip-flops, analysis of, 210–213
Mealy and Moore models of finite
state machines, 214–217
state diagram of, 207–209
state equation of, 205–206
state table of, 206–207
structural description of, 228–230
T flip-flops, analysis of, 213–214
design procedure:
excitation table, 239–241
logic diagram of three-bit binary
counter, 245
maps for three-bit binary
counter, 245
using D flip-flops, 238–239
using JK flip-flops, 241–243
using T flip-flops, 243–245
HDL models:
behavioral modeling, 217–220
flip-flops and latches, 220–223
state diagram, 223–227
sequential circuits, 190–192
state assignment, 235–236
state reduction, 231–235
storage elements:
flip-flops, 196–204
latches, 193–196
System primitives, 116

T
table, 117
Tera (T) bytes, 5
Test bench, 109
T flip-flops, analysis of, 213–214

Theorems of Boolean algebra, 43–45
proofs, 44–45
Thermal agitation, impact on
semiconductor, 507
Three-input exclusive-OR gate, 64
Three-input NAND gate, 91
Three-state buffer gate, 162
Three-state buffers, 163
Three-state gates, 162–164, 169–170
Three-variable K-map, 75–76
$time, 178
timescale compiler, 113
Timing diagrams, 32
Timing verification, 110, 181
Transfer function, 60
Transfer of information, among
registers, 28–30
Transistors, 2
Transistor–transistor logic (TTL), 67
Trigger, 196
tri keyword, 170
Truth table, 31, 46, 52–53, 86, 109, 129
and Boolean algebra, 45
for the 16 functions of two binary
variables, 58
ROM, 317
T_Simple_Circuit_prop_delay, 114
T (toggle) flip-flop, 200–201
analysis, 213–214
characteristic equation, 203
characteristic table, 202
Two-level gating structure, 57
Two-level implementation, 56–57
of Boolean function, 91–93
Two-to-one-line multiplexer, 163, 174
Two-valued Boolean algebra, 41–43
definition, 41
rules of binary operation, 41–42
Two-variable K-map, 74–75

U
Unidirectional shift register, 264
Universal gate, 90
Universal NAND gate, 447
Universal shift register, 263–266
User-defined primitives (UDPs),
116–118

V
Vectors, 166
Verification, 181
Verilog 2001, 426
Verilog 2005, 426
Verilog HDL, 68, 115, 118, 332,
354, 438

Index
flowchart, 363
logical and relational operators, 357
logic operators for binary words, 357
looping statements, 358–361
operator precedence, 359
operators, 355–358
register transfer operation, 354
switch-level modeling in, 517–520
Verilog module, 112
Verilog statements, 115
Verilog system tasks, 178–181
Very large-scale integration (VLSI)
circuits, 66–67, 126
gate array, 332
VHDL, 332

Virtex™, 333, 344–346
Voltage-operated logic circuits, 31

W
while loop, 359
Wired-AND gate, 97
Wired logic, 97
wire keyword, 112, 170, 179
$write, 178

X
XC2000, 333
XC3000, 333
XC4000, 333

Xilinx FPGA:
basic architecture, 333
configurable logic block
(CLB), 334
distributed RAM, 334
enhancements, 337–339
interconnect lines of,
334–336
I/O block (IOB), 337
series, 333
Spartan II, 340–344
Spartan XL chips, 339–340
Virtex, 344–346
XOR gate, 323
XOR operation, 315

547



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