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EMT 125/3
DIGITAL ELECTRONIC PRINCIPLES

INTRODUCTION TO
SEQUENTIAL LOGIC CIRCUIT

SITI ZARINA BINTI MD NAZIRI | SCHOOL OF MICROELECTRONIC ENGINEERING | UniMAP

Sequential Logic Circuit
 Describe and explain Latches, Gated Latches
and Edge triggered flip flops characteristic
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 Explain and demonstrate the applications of
flip flops
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 Edge triggered FF:
Bistable devices which synchronous input whose
state depend on the input only at triggering
transition of clock pulse
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 Flip-Flop:
The output of a flip-flop also depends on current inputs and its
previous output but the change of state occurs at specific times
determined by a clock input
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Edge-Triggered Flip-flops
 All the flip-flops shown have the triggering input called clock (CLK/C)
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Positive edge-triggered

Negative edge-triggered

Edge-Triggered Flip-flops
 A clock signal is a periodic square wave that indefinitely
switches values from 0 to 1 and 1 to 0 at fixed intervals
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INPUTS
S
R CLK

OUTPUTS
Q
Q’

COMMENTS

0

0

Q0

Q0’

No Change

0

1

0

1

RESET

1

0

1

0

SET

1

1

?

?

Invalid

X

Function table

Edge-Triggered S-R Flip-flop
Basic Operation of Positive Edge-Triggered S-R Flip-flop

Edge-Triggered S-R Flip-flop
REMEMBER:

 Flip-flop cannot change state except on the
triggering edge of a clock
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Edge-Triggered S-R Flip-flop
 Example 1:
Determine the Q and Q’ output waveform of FF for S-R FFs for S,R and
CLK inputs
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Edge-Triggered S-R Flip-flop
 Answer 1:

Edge-Triggered D Flip-flop

Logic Diagram
CLK

Negative edgetriggered

Positive edgetriggered

Logic Symbol

Edge-Triggered D Flip-flop
 The D flip-flop is useful when a single data bit (1 or 0) is to
be stored
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Edge-Triggered D Flip-flop
 Answer 2:

What is the output for Q’?

Edge-Triggered J-K Flip-flop
J
Logic Diagram

CLK
K

Negative edgetriggered

Positive edgetriggered

Logic Symbol

Edge-Triggered J-K Flip-flop

 The J-K flip-flop is versatile and is widely used
type of flip-flop
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 The difference is J-K has no invalid state
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Draw the
waveform for Q output
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Draw the
waveform for Q output
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Frequency Division
Example of two J-K flip-flops used to divide the clock frequency by
4
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Frequency Division
Example of two J-K flip-flops used to divide the clock
frequency by 4
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Counting

Flip-flops used to generate
a binary count sequence
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Exercises
 Two edge-triggered S-R flip-flops are shown in figures below
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The
flip-flop initially RESET
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Exercises
 Draw the Q output for the D FF
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(i)

(ii)

Exercises
 For a positive edge-triggered J-K flip-flop with inputs

shown, determine the output
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