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Microprocessor Programming
and Interfacing

EEE Department
BITS Pilani Hyderabad Campus
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Size of Microprocessor
SIZE OF A MICROPROCESSOR
• Size of Data Bus
• Size of Registers
• Size of ALU

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Microprocessor Bus
PROCESSOR BUS

ADDRESS BUS:
No of Address lines
• 20 lines –A19–A0
• 1 M Byte of memory can be addressed
DATA BUS:
No of Data lines
• 16 lines –D15–D0

CONTROL LINES:
-Active low signals
• MEMR
• MEMW
• IOR
• IOW

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Memory of Microprocessors
PROCESSOR MEMORY

• ROM
Non-Volatile
Read Only
• RAM
Volatile
Random Access Memory
MEMORY DATA SIZE

• Bit Organized
• Nibble Organized
• Byte Organized
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Add Bus

Data Bus

Memory

Memory –
Registers to hold bits

Read
Write

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Ex :
4 bits

8 Registers

Address lines : 3 (Unidirectional)
Data lines : 4 (Bidirectional)
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Processors
WHAT IS THE EFFECT ?
• If Instructions is present anywhere
• Size of Instruction varies
-Complicates Instruction Decoder
ISA
 CISC (Complex Instruction Set Computer)
Operands for Arithmetic/Logic operation can be in Register/ Memory

 RISC (Reduced Instruction Set Computer)
Operands for Arithmetic/Logic operation only in Registers
Register –Register Architecture
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16 bit Microprocessor

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32 bit Microprocessor

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Variations of 8086 - 8088

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Characteristics of the X86 family
• CISC
• Instructions broken up into micro operations
• Complex instruction decoder

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Little Endian format
• Binary data are stored as a byte (8 bits), word (16 bits),
or double word (32 bits) in a computer system
...

• Signed negative data are always stored in the two's
complement form
...

• The assembler directives DB or BYTE define bytes,
DW or WORD define words, DD or DWORD define
doublewords, and DQ or QWORD define quadwords
...

• The least significant byte always stored in the lowestnumbered memory location
...

• This method of storing a number is called the little
endian format
...

• Numbers are stored with the lowest location containing
the most significant data
...

• The big endian format is used with the Motorola family
of microprocessors
...


BIU fetches instructions, reads data
from memory and I/O ports, writes
data to memory and I/ O ports
...


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Bus Interface Unit (BIU)

Architecture

Dedicated Adder to generate
20 bit address

Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >>

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Physical Address Generation
Offset Value (16 bits)

Segment Register (16 bits)

0000

Adder

Physical Address (20 Bits)

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Physical Address Generation
20 Address lines  8086 can address up to
1M bytes of memory

220 =

However, the largest register is only 16 bits
Physical Address will have to be calculated Physical
Address : Actual address of a byte in memory
...
e
...


Memory Address represented in the form –
Offset (Eg - 89AB:F012)

Seg :

Each time the processor wants to access memory, it
takes the contents of a segment register, shifts it one
hexadecimal place to the left (same as multiplying by
1610), then add the required offset to form the 20- bit
address

16 bytes of contiguous
memory

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)
F012  0F012 (Offset is already in byte unit)
+ ------98AC2 (The absolute address)
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Bus Interface Unit (BIU)

Architecture
Segment
Registers

8086’s
1-megabyte
memory is divided into
segments of up to 64K
bytes each
...


Programs obtain access to
code and data in the
segments by changing the
segment register content to
point
to
the
desired
segments
...

BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP
...


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Bus Interface Unit (BIU)

Architecture
Segment
Registers

Data Segment Register
16-bit
Points to the current data segment; operands for most instructions are fetched
from this segment
...


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Bus Interface Unit (BIU)

Architecture
Segment
Registers

Stack Segment Register
16-bit
Points to the current stack
...

In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP)
...

String instructions use the ES and DI to determine the 20-bit physical address for
the destination
...

So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area
...


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Bus Interface Unit (BIU)

Architecture

Instruction queue

A group of First-In-First-Out
(FIFO) in which up to 6 bytes
of instruction code are pre
fetched from the memory
ahead of time
...

This mechanism is known as
pipelining
...

A decoder in the EU
control system
translates instructions
...

AL in this case contains the low order byte of the word,
and AH contains the high-order byte
...

Multiplication and Division instructions also use the AX or
AL
...

BL in this case contains the low-order byte of the word,
and BH contains the high-order byte
...

All memory references utilizing this register content for
addressing use DS as the default segment register
...

When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte
...


Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0
...

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Execution Unit (EU)

Architecture
EU
Registers

Data Register (DX)
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX
...

Used to hold the high 16-bit result (data) in 16 x 16
multiplication or the high 16-bit dividend (data) before a
32 by 16 division and the 16 bit reminder after division
...

SP is used as an offset from the current SS during
execution of instructions that involve the stack segment in
the external memory
...

BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode
...

Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses
...

Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses
...
e, bit three during
addition, or borrow for the lowest
nibble,
i
...


Flag Register

This flag is set, when there is
a carry out of MSB in case of
addition or a borrow in case
of subtraction
...


15

14

13

12

11

10

9

8

7

6

OF

DF

IF

TF

SF

5

ZF

Over flow Flag

This flag is set, if an overflow occurs, i
...
The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set
...
If this flag bit
is ‘0’, the string is processed beginning from the lowest
address to the highest address, i
...
, auto incrementing mode
...
e
...


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4
AF

3

2
PF

1

0
CF

Trap Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
36
disables these interrupts
...
No
...


•

Protected
- support multitasking
- memory management protection enabled

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8086-80486 Programmer’s Model
BIU

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Segment Registers

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Physical Address

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Advantage of Segmentation
•

Relocation

•

Program - Specify only offset

•

Program – F0000H

•

Program contents need not be changed- only
segment needs to change from F000H to 1000H

10000H

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Segmentation

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X86 -ISA
8086-80486 Programmers Model
EU

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Programmers Model

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Registers
•

Multipurpose Registers
...

- IP, SP, FLAGS

• Segment Registers

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