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Chapter No
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Digital Electronics
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(i)
...

(ii)
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Analog signals have infinite number of distinct values and are
continuous, while (ii)
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(iii)
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High (i
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‘1’) and (ii)
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e
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(iv)
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(v)
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(vi)
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(vii)
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(viii)
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Q(1)
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Number system:- It is a set of rules and symbols, used to represent number
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Base or Radix: It is defined as the number of different symbols used in the number system
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(ii)
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For e
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The largest digit in decimal number system is
(10-1)=9
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Types of Number System:- Following table shows the various, number system with their radix (r) or base (b)
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The Decimal Number System:- The number system having radix or base ‘10’ called as decimal number system
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The decimal system has the base value
of 10
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Decimal position values as
powers of 10 are as shown below,

(ii)
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As the
radix or base value of binary number system is ‘2’, so its maximum value of digit (r-1)=(2-1)=1, where r is radix or

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The two binary digits are ‘1’ and ‘0’
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Its weight is expressed as a power of 2
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Octal Number System:- The number system which make use of radix ‘8’ is known as octal number system
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It makes use of first eight digits of decimal number system i
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0, 1, 2, 3, 4, 5, 6 and 7
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Octal positions values as a power of 8 are as shown below,

(iv)
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In short these are known as hex system
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Thus the sixteen possible values are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
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The largest value or maximum value for the ‘system is (r-1)=(16-1)=15
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Convert the binary number (110)2 to its decimal equivalent?
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Swapnil Kaware (svkaware@yahoo
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in)*

Q(3)
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01)2 to its decimal equivalent?
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Convert the following: (11011
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*CONVERSION FROM OCTAL TO DECIMAL *
Q(5)
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Q(6)
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63)8=(?)10?
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Convert the following: (385
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* CONVERSION FROM HEXADECIMAL TO DECIMAL *
Q(8)
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Convert the following: (2B
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Q(10)
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2)16 =(?)10?
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Swapnil Kaware (svkaware@yahoo
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in)*

* CONVERSION FROM DECIMAL TO BINARY *
Q(11)
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LSB
2
14
2
7
0
2
3
1
2
1
1
MSB
(14)10=(1110)2
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Convert the following: (204)10=(?)2?
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(0
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* CONVERSION FROM DECIMAL TO OCTAL *
Q(14)
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Q(15)
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6234)10=(?)8?
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Swapnil Kaware (svkaware@yahoo
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in)*

Q(16)
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6875)10=(?)8?
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Q(17)
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Q(18)
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122)10=(?)16?
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122)10=(0
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Q(19)
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760)10=(?)16?
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Convert (10110)2=(?)8?
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Convert (11010010)2=(?)8?
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Swapnil Kaware (svkaware@yahoo
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in)*

Q(22)
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1011011)2=(?)8?
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1011011)2=(0
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* CONVERSION FROM BINARY TO HEXADECIMAL *
Q(23)
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(1010111)2=(57)16
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Convert (1010 1111 1011 0010)2=(?)16?
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Q(25)
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101111001)2=(?)16?
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101111001)2=(B6
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* CONVERSION FROM OCTAL TO HEXADECIMAL *
Q(26)
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1

1

E

∴(436)8=(11E)16
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Convert (1AF)16=(?)8?
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Convert (3CFB
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Convert (68
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Q(30)
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The logic gate is the most basic building block of any digital system, including computers
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Also Gates are basic circuits that have at least one (and usually more) input and
exactly one output
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In computer architecture it
is common to use ‘0’ for false and ‘1’ for true
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Q(31)
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Where X & Y are inputs & Z is the output
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Give symbol, Boolean expression & truth table for ‘OR’ gate?
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Q(33)
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Where X is the input & Z is the output
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Swapnil Kaware (svkaware@yahoo
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in)*

Q(34)
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Where X & Y are inputs & Z is the output
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Give symbol, Boolean expression & truth table for ‘NOR’ gate?
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Q(36)
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Where A & B are inputs & Y is the output
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Give symbol, Boolean expression & truth table for ‘EX-NOR (Exclusive-NOR)’ gate?
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Q(38)
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A universal gate is a device which can implement any Boolean expression without need to use any other gate
type
...
e
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The ‘NAND’ and ‘NOR’ gates are called universal gates
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Explain the basic laws/rules of Boolean algebra
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Swapnil Kaware (svkaware@yahoo
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in)*

(1)
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(A*B)=(A*B), (3)
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(4)
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A+B=A*B
Q(40)
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(i)
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As we know that the output expression for ‘NOT’ gate is, Z=X
...
As we have to implement NOT gate using NAND gate, so hence 1st we are using
expression for NAND gate, then Z=X*Y, so we have to connect inputs of NAND gate i
...
X & Y with each other
then X=Y (i
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both are equal)
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X=X (i
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X*X=X),i
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Z=X hence we
have formed expression for ‘NOT’ gate using ‘NAND’ gate
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X

Z=X
(ii)
...

As we know that the output expression for AND gate is, Z=X*Y
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As we have to implement AND gate using NAND gate, so hence 1 st we are using
expression for NAND gate, then Z=X*Y, so we are taking single inversion on R
...
S
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As we know X*Y=X*Y
...
hence we have
formed expression for ‘AND’ gate using ‘NAND’ gate
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X
Z=X*Y
Y
(iii)
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As we know that the output expression for OR gate is, Z=X+Y
...
As we have to implement OR gate using NAND gate, so hence 1st we are using expression
for NAND gate, then Z=X*Y, so by following rule number (3) we can get X*Y=X+Y, then by taking single
inversion on R
...
S
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So finally we can get X*Y=X+Y
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The equivalent circuit is as shown below
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Explain the working of ‘NOR’ gate as universal gate?
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Implementation of ‘NOT’ gate using ‘NOR’ gate
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Also we know that the output expression for
NOR gate is, Z=X+Y
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e
...
e
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Hence by putting X=Y in Z=X+Y, we get Z=X+X=X (i
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X+X=X), hence we have formed
expression for ‘NOT’ gate using ‘NOR’ gate
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X
Z=X

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Implementation of ‘AND’ gate using ‘NOR’ gate
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Also we know that the output expression for
NOR gate is, Z=X+Y
...
H
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we can get, X+Y=X+Y
...
Hence we have formed expression
for ‘AND’ gate using ‘NOR’ gate
...
Implementation of ‘OR’ gate using ‘NOR’ gate
...
Also we know that the output expression for
‘NOR’ gate is, Z=X+Y
...
H
...
we can get, X+Y=X+Y
...
Hence we have formed expression
for ‘OR’ gate using ‘NOR’ gate
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X

Z=X+Y

Y
Q(42)
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There are mainly two types of digital systems, (i)
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Sequential circuit
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Combinational circuit:- In such types of logic circuits, value of output does not depends on past inputs or
outputs
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e
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Encoder, Decoder, Multiplexer,
Demultiplexer etc
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Sequential circuit:- In such types of logic circuits, value of output depends on present inputs as well as
past outputs
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e
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Flip flops, Counters, Shift registers etc
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Define flip flop & also draw its basic symbol & types?
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Hence it is a bistable device
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e
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Flips flops are also known
as latches
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S-R flip flop, (ii)
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J-K flip flop, (iv)
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D flip
flop, (vi)
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Q(44)
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S
0
0
1
1
(a)
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Symbol,

R
0
1
0
1

Q
1
1
0
1

Q
1
0
1
1

ACTION
Race
Set
Reset
No Change

(c)
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Swapnil Kaware (svkaware@yahoo
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in)*

As seen from the above diagram for the S-R flip flop, ‘S’ stands for ‘SET’ & ‘R’ stands for ‘RESET’
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When ‘S’=0 and ‘R’=0
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e
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(2)
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Then ‘Q’=1 & ‘Q’=0
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(3)
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Then ‘Q’=0 & ‘Q’=1
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(4)
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Then there will be no change, which means there will be no change in inputs &
outputs
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e
...
e
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Race Condition:- As seen from the above truth table when input for S-R flip flop are ‘0’ &’0’, then both
outputs i
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Q & Q becomes ‘1’ & ’1’
...

No Change:- As seen from the above truth table when input for S-R flip flop are ‘1’ &’1’, then both outputs i
...

Q & Q becomes ‘1’ & ’1’, means there will be no further change in inputs & outputs hence such conditions will
also be avoided for better operation of circuit
...
Explain S-R flip flop/latch with diagram (with ‘NOR’ gate), symbol & also draw its truth table?
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S-R Flip Flop,

R
0
1
0
1

(b)
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Truth table

As seen from the above diagram for the S-R flip flop, ‘S’ stands for ‘SET’ & ‘R’ stands for ‘RESET’
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When ‘S’=0 and ‘R’=0
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(i
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values of inputs & outputs are same i
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‘0’)
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When ‘S’=0 and ‘R’=1
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This condition is known as ‘Reset’ condition
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When ‘S’=1 and ‘R’=0
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This condition is known as ‘Set’ condition
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When ‘S’=1 and ‘R’=1
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e
...

No Change:- As seen from the above truth table when input for S-R flip flop are ‘1’ &’1’, then both outputs i
...

Q & Q becomes ‘1’ & ’1’, means there will be no further change in inputs & outputs hence such conditions will
also be avoided for better operation of circuit
...
List/Give the various methods of triggering the flip flops?
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Level triggered
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Positive level triggered
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Negative level triggered
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Edge triggered
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Positive edge triggered
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Negative edge triggered
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Swapnil Kaware (svkaware@yahoo
...
in)*

Q(47)
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CLK
CLK

(a)
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Symbol,

Q
0
0
1
1

Q
0
1
0
1

ACTION
No Change
Reset
Set
Race

(c)
...
e
...
e
...

For further explanation please refer the question no
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Q(48)
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S

CLK

D
0

Q
0

Q
1

1

1

0

CLK

ACTION
Q is following
the input D
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R

(a)
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Symbol,

(c)
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The term ‘data’ refers to the fact that the ‘D’ latch stores data
...
That is, Q is equal to D
delayed by one time period
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In case of D flip flop we have used ‘NAND’
inverter hence it used for making inputs complements of each other
...
e
...
e
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Hence to avoid such condition which is appeared in S-R flip flop
we have implemented D type flip flop using NAND inverter
...
i
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there will not be any operation possible at negative edge of the clock signal
...

(1)
...
e
...

(2)
...
e
...

Q(49)
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CLK

(a)
...
Symbol,

J
0
0
1
1

K
0
1
0
1

Q
0
0
1
Q

Q
0
1
0
Q

ACTION
No Change
Reset
Set
Toggle

(c)
...
This flip flop also uses
S-R type latch
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Inputs J and K behave like inputs S and R to set
and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter Note that, there is a

Page 12 of 19
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The JK flip-flop is a positive edge-triggered device which
means that the outputs, Q and Q will only be affected by the J and K inputs when a low to high transition is
produced at the clock input
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(1)
...
Hence there will be no change, which means there will be
no change in inputs & outputs
...
e
...
e
...

(2)
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This condition is known as ‘Reset’ condition
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When CLK= & ‘J’=1 & ‘K’=0, then ‘Q’=1 & ‘Q’=0
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(4)
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This condition is known as ‘Toggle’ condition
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e
...

Q(50)
...

T

CLK

CLK

T
0
1

Q
0
Q

Q
0
Q

ACTION
No Change
Toggle

The output of a toggle flip-flop, also called a T flip-flop, this flip flop is derived from J-K flip flop
...
That is, the output becomes ‘1’ if it was ‘0’
and ‘0’ if it was ‘1’
...
e
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Following are the
observations are possible depend on ‘clock signal’ & input value of ‘T’
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When CLK= & ‘T’=0, then will not be any further change in inputs & outputs
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When CLK= & ‘T’=1, then toggling case occurs i
...
outputs will be inverted
...
What is ‘Race Around’ condition?
...
Hence such multiple toggling modes are known as race around condition
...
Draw the block diagram of Master-Slave flip flop & also describe its working?
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It consists of 2 clocked S-R flip flops
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The master flip-flop is enabled on the positive edge of the clock
pulse CLK and the slave flip-flop is disabled by the inverter (NOT gate)
...
e
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Then master sets or resets according to the state of the
input signals
...
When
the clock goes low (i
...
‘0’) then master flip flop is inactive and the slave flip flop is active
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The final O/P Q of a master-slave flip flop is O/P of the slave
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Hence by using this
concept multiple toggling i
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race around condition will be also avoided
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Swapnil Kaware (svkaware@yahoo
...
in)*

Q(53)
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Preset
r

CLK
1
0
0

Preset
1
0
1

Clear
1
1
0

ACTION
Normal flip flop
Flip Flop will Set
Flip Flop will Reset

Clear

Q(54)
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(i)
...
In timer circuit, (iii)
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In counters, (v)
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Q(55)
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Please refer the question number (50)
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Explain operating principle of shift register & give its types?
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It is used for storing
temporary data or digital data
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Most of the registers possess no characteristic internal
sequence of states
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For 2-bit shift register we required 2 number of flip flops, For 4-bit shift register we required
4 number of flip flops & For 8-bit shift register we required 8 number of flip flops & so on
...
Following
are the types of flip flops,
(i)
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SIPO:- Serial Input Parallel Output,
(iii)
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PIPO:- Parallel Input Parallel Output
...
Draw the circuit & timing diagram (waveforms) of 4-bit SISO shift register with working?
...
Assume Q0 is
the output for FF-0, assume Q1 is the output for FF-1, assume Q2 is the output for FF-2, assume Q3 is the
output for FF-3, Following are the operations are possible,

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Before the application of clock signal let Q0Q1Q2Q3=0000
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After applying clock signal, at 1st falling (negative) edge of clock signal FF-0 will be set, hence
Q0Q1Q2Q3=1000
...
At 2nd falling (negative) edge of clock signal FF-1 will be set, hence Q0Q1Q2Q3=1100
...
At 3rd falling (negative) edge of clock signal FF-2 will be set, hence Q0Q1Q2Q3=1110
...
At 4th falling (negative) edge of clock signal FF-3 will be set, hence Q0Q1Q2Q3=1111
...
Draw the circuit & timing diagram (waveforms) of 4-bit ring counter with working?
...
These registers are classified as counters because they exhibit a
specified sequence of states
...
The above 4-bit ring counter is constructed from D
flip-flops
...
If the
CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0
...
Since
the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter
...

In a ring counter, the sequence of states may follow a binary count or any other sequence of
states
...
They are used for counting the
number of occurrences of an even and are useful for generating timing sequences to control operations in a
digital system
...
Thus, the value after the clock
transition depends only on old values of the outputs
...
Draw the circuit & timing diagram (waveforms) of 4-bit ripple counter with working?
...
Swapnil Kaware (svkaware@yahoo
...
in)*

A ripple counter is a cascaded arrangement of flip-flops
...
In a ripple counter, also called an asynchronous counter or a serial counter, In this counter all the flip
flops are not under the control of a single clock
...
The clock input to any subsequent flip-flop comes from the
output of its immediately preceding flip-flop
...

That is, the second flip-flop would change state a certain time delay after the occurrence of the
input clock pulse owing to the fact that it gets its own clock input from the output of the first flip-flop and not
from the input clock
...
In general, the nth flip-flop will change state only after a delay equal to n times the
propagation delay of one flip-flop
...

It is also called an ‘asynchronous counter’ as different flip-flops comprising the counter do not
change state in synchronization with the input clock
...
The propagation delay of each flip-flop, of course, will depend
upon the logic family to which it belongs
...
Draw the circuit diagram of multiplexer (data selector) & also explain its operation?
...
Multiplexer,

Fig(b)
...


A Multiplexer (MUX) is a combinational device having multiple data inputs, select inputs & only one output
...
Hence, a multiplexer can take many data bits and put them,
one at a time, on a single output data line in a particular sequence
...
i
...
output line can be attached with only one input data line at the same
time only
...
The relation between
select inputs (i
...
‘m’) & data inputs (i
...
‘n’) can be stated as,2 =n
...
Hence by this way multiplexer circuit
reduces the number of wired connections & produces the proper digital code on single wire
...
2:1 multiplexer, (ii)
...
8:1 multiplexer, (iv)
...

Q(61)
...

E

0

Io

1

Fig
...
Circuit diagram,

Y

1

Fig
...
Logic symbol,

S
1

I1

Fig
...
Truth table

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Draw logic symbol, circuit diagram & truth table of 4:1 multiplexer?
...
(b)
...
(a)
...
(c)
...
Draw logic symbol, circuit diagram & truth table of 8:1 multiplexer?
...
(60)
...
Draw the circuit diagram of demultiplexer & also explain its operation?
...
The select input lines decide the state of output
...
Hence also called as digitally
controlled multiple pole single way switch
...
e output line can be attached with only one input data line at the
same time only
...
The relation
between select inputs (i
...
‘m’) & outputs (i
...
‘n’) can be stated as, 2 =n
...
Hence by this way demultiplexer circuit
increases the number of wired connections & produces the proper digital code on multiple wires
...
1:2 demultiplexer, (ii)
...
1:8 demultiplexer, (iv)
...


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Draw logic symbol, circuit diagram & truth table of 1:2 demultiplexer?
...
(b)
...
(a)
...
(c)
...
Draw logic symbol, circuit diagram & truth table of 1:4 demultiplexer?
...
(b)
...
(a)
...
(c)
...
Give/compare differences between Multiplexer & Demultiplxer?
...
No
...
No
...


1:2 DEMUX, 1:4 DEMUX etc
...
Switch type:(iv)
...
Examples:(vi)
...
Swapnil Kaware (svkaware@yahoo
...
in)*

Q(68)
...


Fig
...
Logic symbol,

Fig
...
Circuit diagram,

Fig
...
Truth table
...
Swapnil Kaware (svkaware@yahoo
...
in)*



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