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Homework solutions
EE3143

Resistive circuits

Problem 1
Use KVL and Ohms law to compute voltages va and vb
...
5[V]
i1= (v1-v2)/40=-1
...
5 [mA]

Thevenin & Norton

Problem 3: Find Thevenin and Norton equivalent circuit for the network shown
...
33Ω
Note: Negative vt indicates that the polarity is reversed and
as a result this circuit has a negative resistance
...
33Ω
Vt=-6 V

A

A

+
_

In=4
...
33Ω
B

B
Thevenin Equivalent

Norton Equivalent

Problem 4: Find the current i and the voltage v across LED diode
in the circuit shown on Fig
...
b)
...
Intersection of load
line and diode characteristic is the i
and v across LED diode: v ≈ 1
...
5 mA
...
Assume that the diodes are ideal and allow v to
range from -10 V to +10 V
...


i (mA)

4
3
2
1
0
-10

-5

0

5

v (V)

In a series connection voltages are added for each constant current

10

Problem 5: Sketch i versus v to scale for each of the circuits
shown below
...

(b)
+
v
_

i

1kΩ
+
_

5V

Due to the presence of the 5V
supply the diode conducts only
for v > 5, R = 1kΩ
5

i (mA)

4
3
2
1
0
-10

-5

0

5

10

v (V)

First combine diode and resistance then add the voltage source

Problem 5: Sketch i versus v to scale for each of the circuits
shown below
...

i

(c)

+
2kΩ
v
_

A

1kΩ

B

10

Diode B is on for v > 0 and R=1kΩ
...

i (mA)

5

0

-5
-10

-5

0

v (V)

5

10

Problem 5: Sketch i versus v to scale for each of the circuits
shown below
...

(d)

i
+

v
_

D
C

1kΩ

Diode D is on for v > 0 and R=1kΩ
...


10

i (mA)

5

0

-5
-10

-5

0

v (V)

5

10

Modeling a piecewise characteristic of a device
Problem 6
Sketch the transfer characteristic (vo versus vin) for the circuit shown in the
figure below
...

+

v

-

i

i
1kΩ
vx

v

In a parallel connection currents are added for each constant voltage

Modeling a piecewise characteristic of a device
Problem 6
Sketch the transfer characteristic (vo versus vin) for the circuit shown in the
figure below
...

+

v

-

i

i
1kΩ
vx

v

In a parallel connection currents are added for each constant voltage

Modeling a piecewise characteristic of a device
Problem 6
Add the voltage source
...


i

+

v

-

i
+

+
Vin
-

1kΩ
2kΩ

vo
_

v
vin

In a parallel connection currents are added for each constant voltage

Modeling a piecewise characteristic of a device
Problem 6
Add the voltage source
...

a) Find vGS(t)
...


Soln (a): In loop 1 the 1
...

The voltage drop across
200 kΩ resistor is the dc
voltage VGSQ
VGSQ = 20*0
...
8 MΩ
Zin

+
_ sin(200πt)

G
0
...
5 mA/V2, sketch its
drain characteristics to scale for VGS = 1, 2, 3, and 4 V
...

d) Find the values of VDSQ, VDSmin, and VDSmax
...

c) To get the load line apply KVL to loop 2:
20 – 2 kΩ*iD(t) = VDS(t)
The red line in the plot is the load line
...
8 MΩ

VGS = 2V

5

10

VDS (V)

15

VGS = 1V
20

Zin
+
_ sin(200πt)

G
0
...

d) VDSQ, VDSmin, and VDSmax
are the points at which the
load line intersects the
drain characteristics for VGS
= 2 V, 3 V and 1 V
respectively
...
Assume
NMOS transistor has the following parameters:
𝐾𝑃=60 𝜇𝐴∕𝑉2, 𝐿=5 𝜇𝑚, 𝑊=100 𝜇𝑚, 𝑟 𝑑=∞, and 𝑉 𝑡𝑜=1
...

a) Find the values of 𝐼 𝐷𝑄, 𝑉 𝐷𝑆𝑄and 𝑔 𝑚

The 72 kΩ and 28 kΩ
resistors act as a voltage
divider
...
8V
R1  R2
72  28

1
W 
KP   0
...
93V

I DQ  K VGSQ  Vto   1
...
56mS

K

2

Problem 9 b): - Assuming that the coupling capacitors are short circuits
for the ac signal, determine the following: voltage gain, input
resistance and output resistance
...
3
'

Rin 

1
1

R1

 1

R1 =
72 kΩ

 833
...
16 kW
R2

Ro  RD  5kW

+
vin
_

RD = 5 kΩ
C2

R2 =
28 kΩ

+
vo
_

RL=
1 kΩ

Problem 10: - Consider the common source amplifier shown below
...

a) If Rin = 250 kΩ, find the values for R1 and R2 to achieve 𝐼 𝐷𝑄=2 𝑚𝐴
...
5 kΩ

vo
_

RL =
5 kΩ

+15 V
Rin

R1

C1

R

C2

+
+
v(t) _

vin(t)

RS =
0
...
5mA / V 2
2
L

I DQ  K VGSQ  Vto   2mA
2

VS  RS I DQ  1V

• Solve for

+

R2

_

• We have:
• Given:

RD =
2 kΩ

VGSQ  Vto  I DQ K  2
...
155V
R2
1
VG  VDD
 VDD Rin
R1  R2
R1
1
1
R1  VDD
Rin  15 *
* 250 *10 3  1
...
155

• We have Rin = 250 kΩ and R1 = 1
...
19 M * R2
 R2  316
...
19 M  R2

b) Determine the voltage gain
RL 
'

1
 454
...
46mS

Av 

v0
'
  g m RL  1
...

If VBE = -0
...


Soln (a): From KVL:

5V  I E * RE  1V

4V  I E * 5000
From KVL:
Ohm’s law:

I E  0
...
6  0
...
4V  I B * 20 kW

I C  I E  I B  0
...
975
IE

IE

VBE = -0
...
Determine:
a) IC1, VC1,
VCE1
...


• Soln:
Assume VBE= VBE1 =VBE2 = 0
...


 30  I B1 * RB1  VBE1  0
30  0
...
07A
3
750 *10

I C1   * I B1  3
...
: - Apply KVL along the path (red line)
...
2234  I B 2 RC1  0
...
0766  I B 2 RC1  101 * RE 2   0

I B 2  10
...
907  0
...
2
 5
...
7111V

VBE1

IB2

IC1
VCE1

IC2

VBE2
IE2

RC2

VCE2

RE2

• Part (b): - Apply KVL along the path (red line)
...
559 A  1
...
0556 mA

VC 2  30  I C 2 RC 2
VC 2  30  1
...
888V
VE 2  I E 2 RE 2  5
...
8769 V

IB1

RB1

R
IC2
IC1 + IB2 C1
IB2
VC1
IC1 V
BE2

VBE1

VCE1

IE2

RC2
VC2
VCE2
VE2
RE2

Problem BJT P3: - Design the bias circuit (find R C and RB) to give a Qpoint of IC = 20µA and VCE = 0
...
65V
...


I C  I B RC  VCE  1
...
9  1
...
6
 


1 
6 
20 *10 1   RC  0
...
6
RC 
 29
...
4 *10

IB

IC = 20µA
VCE = 0
...
65V

• Soln contd
...
9V
...


I C  I B RC  I B RB  VBE  1
...
65  1
...
6  
 50  RB  0
...
5



0
...
25

0
...
4 *10

IB

IC = 20µA
VCE = 0
...
65V

• Soln contd
...

We have RC=29
...

• Apply KVL along the path (red line)
...
5
I B  I B  29
...
85
126 * 29
...
85
0
...
196A
6
4
...
196 *10

6

 24
...
65V

• Soln contd
...


I C  I B RC  VCE  1
...
53  0
...
41 k  VCE  1
...
5  0
...
773V
• The Q-Point is:

I C ,VCE   24
...
773V 

IC + IB

IB

IC
VCE
VBE = 0
...
If 𝑣 𝑖𝑛
(𝑡) = 6 + 9𝑐𝑜𝑠(500𝜋𝑡), calculate the value of R2 required to generate a
output, vo(t), with zero DC component
...
We can use
superposition theorem to solve for
the output voltage: connect inputs
to ground (0 V), one at a time, and
solve for output voltage
...
Assume
the maximum output voltage of the op-amp ranges from – 12 V to + 12 V;
the maximum output current magnitude is 25 mA; and the slew-rate limit
is 1
...
If 𝑣 𝑖𝑛 (𝑡)=𝑣 𝑚 𝑠𝑖𝑛(𝜔𝑡), R1 = 5 kΩ, and R2 = 25 kΩ
...

• Soln: The full-power bandwidth of
the op-amp is given by
SR
f FP 
2Vom
• Slew-rate, SR = 1
...


f FP

1
...
9kHz
2 (12 )

R2
R1
+
vin(t)
_

+

+
vo(t)
_

RL

b) Find the peak output voltage possible without distortion for the following
cases:

• Case a: Frequency of 5 kHz and RL = 20 Ω
– Soln
...

Since RL is very small compared to R2 the current through R2 can be
neglected
...
5V
• Case b: Frequency of 5 kHz and RL = 2
...
:
Vom = 12 V (The maximum voltage that the op-amp can
achieve
...
5 kΩ
– Soln
...

6

Vom

SR
1
...
7V
3
2f 2 (50 *10 )

Problem Logic Gates P1: - Express the following functions in canonical
SOP form
...

• Soln:a) F(A, B, C) = (A + B’)C’ + A’C
F(A, B, C) = AC’ + B’C’ + A’C=
A’B’C’+A’B’C+A’BC+AB’C’+ABC’

A

B

C

F

0

0

0

1

0

0

1

1

0

1

0

0

0

1

1

1

X

Y

Z

F

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

1

1

1

0

1

0

1

0

0

1

1

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

b) F(X, Y, Z) = (X + Y’)(X’ + Z) + ZY’
0
F(X, Y, Z) = XX’ + XZ + X’Y’ + Y’Z + ZY’
0
F(X, Y, Z) = XZ + X’Y’ + Y’Z
1
=
=X’Y’Z’+X’Y’Z+XY’Z+XYZ
0
1

c) F(A, B, C, D) = AB’C + A’BC’D + A’BCD’ + B’D’
F(A, B, C, D) =AB’CD+AB’CD’+ A’BC’D + A’BCD’ +
+AB’C’D’+A’B’CD’+A’B’C’D’
d) F(W, X, Y, Z) = WX’ + Z’(Y’ + W’) + W’Z’Y’
F(W, X, Y, Z) = WX’ + Y’Z’ + W’Z’ + W’Z’Y’
F(W, X, Y, Z) = W’X’YZ’+W’X’YZ’+WX’YZ’+WX’Y’Z’+
+WX’YZ+WX’Y’Z+WXY’Z’+W’XY’Z’+W’XYZ’

Karnaugh Map instead of truth table:
C

Y
D

1

1

1

A

1

Z
1

1

1

W

B

X
1

1

1
1

1
1

1

1

1

Problem Logic Gates P2: - Realize AND, OR and NOT functions
using: a) NOR, b) NAND
• Soln
...
b:- Using NAND Gates

Problem Logic Gates P3: - a) Use Karnaugh-map to find the SOP
form of the following function:
F = BC’D’ + BC’D + A’C’D’ + BCD’ + A’B’CD’
• Soln:F = BC’D’ + BC’D + A’C’D’ + BCD’ + A’B’CD’
C
1

1

1

1

1

1

1

1

A

D

SOP: F = BD’ + BC’ + A’D’

B

Problem Logic Gates P3: - b) Find the minimum POS form of the
function above and draw a logic circuit representing the same
...
That is consider locations with zero (0) and then
invert the result
...
(A’ + B)

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