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EE577b Cadence Tutorial
Cadence Tutorial 7
Generating HSPICE Netlist from Schematic
EE577b Spring2000
In this tutorial, I will show how to generate HSPICE netlist from schematic
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Tutorial Setup
Tutorial 1,2,4 are necessary to start this tutorial
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Open adder8 Schematic
As usual!!
3
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sch:Tools->Other
2
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3
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run1 or use default (spice
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Click OK
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5
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Use default for others
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Click OK
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EDU
EE577b Cadence Tutorial
4
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sch:Simulation->Option
2
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- Click Use Hierarchical Netlister option if you want hierarchical netlist which includes
all sub blocks as sub circuits call
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- We don’t run hspice simulation directly from cadence tools so other options regarding
simulation are not important
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- I will choose Hierarchical Netlister
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5
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sch:Simulation-> Netlist/Simulate
2
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3
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4
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2
jsmoon@ISI
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Check Output
1
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2
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run1 directory, you will get netlist file as follows
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global vdd gnd
$****************************************************************************
$ MODEL Declarations
$****************************************************************************
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7 gamma=0
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model pmos pmos level=2 vto=-0
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4 kp=1
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3 tox=6e-07
$****************************************************************************
$ Sub-Circuit Netlist:
$
$ Block: inverter
$ Last Time Saved: Nov 16 16:01:31 1998
$****************************************************************************
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ends inverter
$****************************************************************************
$ Sub-Circuit Netlist:
$
$ Block: nor2
$ Last Time Saved: Nov 16 19:42:44 1998
$****************************************************************************
3
jsmoon@ISI
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subckt nor2 a b x pl=2 pw=16 nl=2 nw=3
mxn1 x b gnd gnd nmos w=nw l=nl
mxn0 x a gnd gnd nmos w=nw l=nl
mxp1 x b net38 vdd pmos w=pw l=pl
mxp0 net38 a vdd vdd pmos w=pw l=pl
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subckt nand2 a b x pl=2 pw=8 nl=2 nw=6
mxn1 net6 b gnd gnd nmos w=nw l=nl
mxn0 x a net6 gnd nmos w=nw l=nl
mxp1 x b vdd vdd pmos w=pw l=pl
mxp0 x a vdd vdd pmos w=pw l=pl
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subckt nor2 a b x pl=2 pw=16 nl=2 nw=3
mxn1 x b gnd gnd nmos w=nw l=nl
mxn0 x a gnd gnd nmos w=nw l=nl
mxp1 x b net38 vdd pmos w=pw l=pl
mxp0 net38 a vdd vdd pmos w=pw l=pl
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subckt nand2 a b x pl=2 pw=8 nl=2 nw=6
mxn1 net6 b gnd gnd nmos w=nw l=nl
mxn0 x a net6 gnd nmos w=nw l=nl
mxp1 x b vdd vdd pmos w=pw l=pl
mxp0 x a vdd vdd pmos w=pw l=pl
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EDU
EE577b Cadence Tutorial
$****************************************************************************
$ Sub-Circuit Netlist:
$
$ Block: half_adder
$ Last Time Saved: Dec 2 13:39:21 1998
$****************************************************************************
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ends adder8@sheet002
$****************************************************************************
$ Sub-Circuit Netlist:
$
$ Block: adder8@sheet001
$ Last Time Saved: Dec 2 13:39:08 1998
$****************************************************************************
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ends adder8@sheet001
$****************************************************************************
$ Main Circuit Netlist:
$
$ Block: adder8
$ Last Time Saved: Dec 2 13:39:38 1998
$****************************************************************************
xsh2 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c3 cout s7 s6 s5 s4 s3 s2
+s1 s0 adder8@sheet002
xsh1 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c3 cin s3 s2 s1 s0
+adder8@sheet001
3
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Run HSPICE
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Copy ~ee577/cad/lib/spice/hp14b
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3
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spice, change "nfet to nmos" and "pfet to pmos"
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Create adder8
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include 'hp14b
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EDU