Notesale: Turn your study into money

Document Preview

Extracts from the notes are below, to see the PDF you'll receive please use the links above

---

8086 ARCHITECTURE
For More Contents, do subscribe to my channel
on you tube as,

”Tech_Guru Swapnil Kaware”
Microprocessor Notes by Er
...
Kaware (svkaware@yahoo
...
in)

8086 ARCHITECTURE

Presented By,
Er
...
Kaware
(Assistant Professor)
svkaware@yahoo
...
in
B
...
(Electronics), M
...
( Electronics)

8086 Overview
•
•
•
•
•
•
•
•
•
•
•

Introduced in 1978
...

Having Address Bus of 20 bit
...

HMOS Microprocessor
...
e
...

Clock Frequencies of 5,8 & 10 MHz
...

Can Address up to 1 Mbytes of Memory
...

Microprocessor Notes By, Er
...


8086 Architecture

Microprocessor Notes By, Er
...

• (1)
...

• (2)
...

• BIU contains Instruction queue, Segment
registers,Instruction pointer,etc
...

Microprocessor Notes By, Er
...
It provides a full 16 bit bidirectional data bus and 20 bit address bus
...
It sends address of memory or I/O
...
It fetches instruction from memory
...
It reads data from port/memory
...
It writes data into port/memory
...
It supports instruction queuing
...
It makes 8086’s interface to the outside world
...
Swapnil
Kaware

Bus Interface Unit (BIU)
(8)
...

(9)
...


(10)
...

Microprocessor Notes By, Er
...
The Execution unit is responsible for decoding and
executing all instructions
...
The EU extracts instructions from the top of the
queue in the BIU
...
During the execution of the instruction, the EU
tests the status and control flags and updates them
based on the results of executing the instruction
...
Swapnil
Kaware

Execution Unit (EU)
(4)
...

(5)
...
It
reads one instruction byte after the other from the
output of the queue
...
It tells BIU from where to fetch instructions or
data,decodes instructions & execute instructions
...
Swapnil
Kaware

8086’s Fourteen 16-Bit Registers
ES
CS
SS
DS
IP

BIU registers
(20 bit adder)

AX
BX
CX
DX

EU registers
16 bit arithmetic

AH
BH
CH
DH

Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
AL
BL
CL
DL

SP
BP
SI
DI
FLAGS
Microprocessor Notes By, Er
...

• To increase the execution speed, BIU fetches as
many as six instruction bytes ahead to time from
memory
...

• Then all bytes are given to EU one by one
...

• It improves the execution speed of the instruction
...
Swapnil
Kaware

Registers of 8086
• Intel 8086 contains following registers:

•
•
•
•
•

General Purpose Registers
Pointer and Index Registers
Segment Registers
Instruction Pointer
Status Flags
Microprocessor Notes By, Er
...
Swapnil
Kaware

General Purpose Registers
• Each of these 16-bit registers are further
subdivided into two 8-bit registers
...
Swapnil
Kaware

General Purpose Registers
• AX Register: AX register is also known as accumulator
register that stores operands for arithmetic operation
like divided, rotate
...
It holds the starting base location of a memory
region within a data segment
...
It is primarily used
in loop instruction to store loop counter
...

Microprocessor Notes By, Er
...
Stack Pointer (SP),
(2)
...
Source Index (SI),
(4)
...


Microprocessor Notes By, Er
...

(1)
...


(2)
...
BP
register is usually used for based indexed or register indirect addressing
...
Source Index (SI) is a 16-bit register
...
Destination Index (DI) is a 16-bit register
...

Microprocessor Notes By, Er
...
Code Segment Register (CS),
(2)
...
Stack Segment Register (SS),
(4)
...

Microprocessor Notes By, Er
...

• For e
...
:
• The code segment register points to the starting address
of the code segment
...

• The maximum capacity of a segment may be up to 64 KB
...
Swapnil
Kaware

Segment Register
• Code segment (CS):• It is a 16-bit register containing address of 64 KB
segment with processor instructions
...

• CS register cannot be changed directly
...
Swapnil
Kaware

Segment Register
• Stack segment (SS):• it is a 16-bit register containing address of 64KB
segment with program stack
...

• SS register can be changed directly using POP
instruction
...
Swapnil
Kaware

Segment Register
• Data segment (DS):• It is a 16-bit register containing address of 64KB segment
with program data
...

• DS register can be changed directly using POP and LDS
instructions
...
Swapnil
Kaware

Segment Register
• Extra segment (ES):• It is a 16-bit register containing address of 64KB segment, usually with
program data
...

• ES register can be changed directly using POP and LES instructions
...


Microprocessor Notes By, Er
...


• It allows instruction code,data,stack and portion of
program to be more than 64KB long
...


• It permits a program or its data to be put in different
areas of memory
...
e
...

Microprocessor Notes By, Er
...
Swapnil
Kaware

Instruction Pointer
• The Instruction Pointer (IP) in 8086 acts as a Program
Counter
...

• Its content is automatically incremented when the
execution of a program proceeds further
...

• This is done during the Fetch Cycle
...
Swapnil
Kaware

Status Flags
• Status Flags determines the current state of the
accumulator
...

• This allows to determine the type of the result
...

• It is also called Flag Register or Program Status Word (PSW)
...

Microprocessor Notes By, Er
...
Swapnil
Kaware

Flag Register (PSW)
• 8086 has 9 flags and they are divided into
two categories:
• (1)
...
Control Flags
...
Swapnil
Kaware

Flag Register (PSW)
• Following are the nine flags:
Condition Flags

Control Flags

1
...
Auxiliary Carry Flag

1
...
Interrupt Flag

3
...
Directional Flag

4
...
Parity Flag
6
...
Swapnil
Kaware

Flag Register (PSW)
• Carry Flag (CY): This flag indicates an overflow condition for
unsigned integer arithmetic
...

• Auxiliary Flag (AC): If an operation performed in ALU generates
a carry/barrow from lower nibble (i
...
D0 – D3) to upper nibble
(i
...
D4 – D7), the AC flag is set i
...
carry given by D3 bit to D4 is
AC flag
...


• Parity Flag (PF): This flag is used to indicate the parity of result
...
Swapnil
is reset
...


• Sign Flag (SF): In sign magnitude format the sign of
number is indicated by MSB bit
...

• Trap Flag (TF): It is used for single step control
...
When trap flag is set, program
can be run in single step mode
Microprocessor Notes By, Er
...

If it is set, the maskable interrupt of 8086 is enabled
and if it is reset, the interrupt is disabled
...


• Direction Flag (DF): It is used in string operation
...
When it is reset,
the string bytes are accessed from lower memory
address to higherMicroprocessor
memory
address
...
Swapnil
Kaware

Pin Diagram of 8086

8086
Pin Diagram

Microprocessor Notes By, Er
...
The lines AD0-AD7 carries low order byte
of data & AD8-AD15 carries high order byte of data
...

• During T1 these are the most significant address lines for
memory operations
...

• The S4 and S3 combination indicates which segment register is
presently being used for memory accesses
...
Swapnil
Kaware

Function Of Pins of 8086
S4 Pin

S3 Pin

Indication

0
0
1

0
1
0

Extra Segment
Stack Segment
Code or None

1

1

Data Segment

BHE (Bus High Enable) /S7: The bus high enable is used to indicate the transfer of data
over the higher order ( D15-D8 ) data bus as shown in table
...
Swapnil
Kaware

Function Of Pins of 8086
(1)
...

(2)
...

(3)
...
If any
interrupt request is pending, the processor enters the
interrupt acknowledge cycle
...

• This signal is active high
and internally synchronized
...
Swapnil
Kaware

Function Of Pins of 8086
(4)
...

If the TEST pin goes low, execution will continue, else
the processor remains in an idle state
...
CLK- Clock Input: The clock input provides the basic
timing pulses for processor operation and bus control
activity
...
MN/MX: The logic level at this pin decides whether
the processor is to operate in either minimum mode or
maximum mode
...
Swapnil
Kaware

Operating Modes Of 8086
• 8086 microprocessors can be configured to work in either of
the two modes:
• (1)
...
Maximum Mode
...

– Typically smaller systems and contains a single microprocessor
...

– Larger systems with more than one microprocessor
...
Swapnil
Kaware

Common Signals In Both Mode

Microprocessor Notes By, Er
...
Address Latch Enable (ALE): is a pulse to logic 1 that gives
signal to external circuitry there is a valid address available
on the bus (AD0-AD15)
...
IO/M line: When low indicates I/O device is accessed &
When high indicates memory device is accessed
...
DT/R line: indicates direction of data to be select
...
e
...

(4)
...
Microprocessor Notes By, Er
...
RD line: when goes low indicates the processor to
read data from memory or I/O devices
...
WR line: when goes low indicates the processor to
write data to memory or I/O devices
...
DEN line: when goes low indicates that there is
availability of valid data on AD0-AD15
...
Ready line: when goes high indicates that the
peripheral device is ready to transfer data
...
Swapnil
Kaware

Signals In Minimum Mode
(9)
...

(10)
...


(11)
...
It is used to synchronize
the processor to external events
...
NMI: (Non Maskable interrupt): it can not be delayed or

rejected i
...
can not be recognized
...
RESET: when goes low processor terminates the current
activity & goes to reset state
...
Swapnil
Kaware

Signals In Maximum Mode
(14)
...
e
...

(15)
...
e
...

QS1

QS0

Indication

0
0

0
1

No operation

1

0

Empty queue

1

1

Subsequent byte from the queue

First byte of the opcode from the queue

(16)
...
Swapnil
bus cycle
...
S2, S1, S0 – Status Lines: These are the status lines
which reflect the type of operation, being carried out by
the processor
...
Swapnil
Kaware

Concept of Pipelining
• In this technique we can execute more than one instruction at the
same time
...

• In 8086 microprocessor pipelining concept is introduced with the help
of 6-Byte instruction queue
...


• Execution process of instructions becomes fast as compared to other
processors
...

Microprocessor Notes By, Er
...
Swapnil
Kaware

For More Contents, do subscribe
to my channel on you tube as,

”Tech_Guru Swapnil
Kaware”
(Thanks For Watching)
Microprocessor Notes by Er
...
Kaware (svkaware@yahoo
...
in)



---