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Digital Sequential Circuits
We covered numerous combinational circuits in earlier chapters
...
The accompanying
graphic shows the block diagram for a sequential circuit
...
The
sum of the current inputs and the previous outputs have an
impact on the sequential circuit's outputs
...
As a result,
sequential circuits have both combinational circuits and memory
storage components
...
The differences between sequential and combinational circuits
are shown in the following table
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Outputs depend on both
present inputs and present
state
...
Feedback path is present
...
Memory elements are required
...
Clock signal is required
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Difficult to design
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That implies that
asynchronous sequential circuits' outputs do not all change
simultaneously
...
•
Synchronous sequential circuits
If every output of a sequential circuit changes in response to the
active transition of the clock signal, the circuit is said to be
synchronized
...
As a result, the
clock signal's positive or negative edges are synced with the
outputs of synchronous sequential circuits
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Clock signal
Clock signal is a periodic signal and its ON time and OFF time
need not be the same
...
This clock signal is shown in the following figure
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This signal stays at logic High 5V5V for some time and stays at
logic Low 0V0V for equal amount of time
...
In this case, the time period will be equal
to either twice of ON time or twice of OFF time
...
This clock signal is shown in the
following figure
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This signal stays at logic High 5V5V for some time and stays at
logic Low 0V0V for some other time
...
In this case, the time period will be equal to
sum of ON time and OFF time
...
All sequential circuits are
operated with clock signal
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Types of Triggering
Following are the two possible types of triggering that are used
in sequential circuits
...
Following are the two types of level triggering
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It is highlighted in below figure
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It is highlighted in the following figure
...
This indicates that the clock signal changes from logic
low to logic high or vice versa
...
•
•
Positive edge triggering
Negative edge triggering
If the sequential circuit is operated with the clock signal that is
transitioning from Logic Low to Logic High, then that type of
triggering is known as Positive edge triggering
...
It is shown in the following figure
...
It is also called
as falling edge triggering
...
In coming chapters, we will discuss about various sequential
circuits based on the type of triggering that can be used in it
...
•
Latches
•
Flip-flops
Latches operate with enable signal, which is level sensitive
...
We will discuss about flipflops in next chapter
...
SR Latch
SR Latch is also called as Set Reset Latch
...
The circuit
diagram of SR Latch is shown in the following figure
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The upper NOR gate has two inputs R & complement of present
state, Qtt’ and produces next state, Qt+1t+1 when enable, E is
‘1’
...
We know that a 2-input NOR gate produces an output, which is
the complement of another input when one of the input is ‘0’
...
If S = 1, then next state Qt+1t+1 will be equal to ‘1’
irrespective of present state, Qtt values
...
At any time, only of those two inputs should be ‘1’
...
•
The following table shows the state table of SR latch
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D Latch
There is one drawback of SR Latch
...
So, we
can overcome this difficulty by D Latch
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The circuit diagram of D Latch is shown in the following
figure
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D Latch
is obtained from SR Latch by placing an inverter between S
amp;& R inputs and connect D input to S
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• If D = 0 → S = 0 & R = 1, then next state Qt+1t+1 will be
equal to ‘0’ irrespective of present state, Qtt values
...
• If D = 1 → S = 1 & R = 0, then next state Qt+1t+1 will be
equal to ‘1’ irrespective of present state, Qtt values
...
The following table shows the state table of D latch
...
That means the output of D Latch is sensitive to the
changes in the input, D as long as the enable is High
...
Similarly, you can
implement these Latches using NAND gates
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Those are the
basic building blocks of flip-flops
...
In first method, cascade two latches in such a way that the first
latch is enabled for every positive clock pulse and second latch is
enabled for every negative clock pulse
...
In second method, we can directly implement the flip-flop, which
is edge sensitive
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•
•
•
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop
SR Flip-Flop
•
SR flip-flop operates with only positive clock transitions or
negative clock transitions
...
The circuit diagram of SR flip-flop is shown in the
following figure
...
The
operation of SR flipflop is similar to SR Latch
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The following table shows the state table of SR flip-flop
...
So, SR flip-flop can be used for one of these three functions such
as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied
...
Present
Inputs
Present
State
Next
State
S
R
Qtt
Qt+1t+1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
x
1
1
1
x
By using three variable K-Map, we can get the simplified
expression for next state, Qt+1t+1
...
The maximum possible groupings of adjacent ones are already
shown in the figure
...
Whereas, D latch operates with
enable signal
...
The circuit diagram of D flip-flop is shown in the
following figure
...
The
operation of D flip-flop is similar to D Latch
...
The following table shows the state table of D flip-flop
...
From the above state table, we can directly write the next
state equation as
Qt+1t+1 = D
Next state of D flip-flop is always equal to data input, D for every
positive transition of the clock signal
...
JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop
...
The circuit diagram of JK flip-flop is shown in the following figure
...
The
operation of JK flip-flop is similar to SR flip-flop
...
The following table shows the state table of JK flip-flop
...
So, JK flip-flop can be used for one of these four functions such
as Hold, Reset, Set & Complement of present state based on the
input conditions, when positive transition of clock signal is
applied
...
Present
Inputs
Present
State
Next
State
J
K
Qtt
Qt+1t+1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
By using three variable K-Map, we can get the simplified
expression for next state, Qt+1t+1
...
The maximum possible groupings of adjacent ones are already
shown in the figure
...
It is obtained by
connecting the same input ‘T’ to both inputs of JK flip-flop
...
The circuit diagram of T flip-flop is shown in the
following figure
...
The
operation of T flip-flop is same as that of JK flip-flop
...
So,
we eliminated the other two combinations of J & K, for which
those two values are complement to each other in T flip-flop
...
D
Qt+1t+1
0
Qtt
1
Qtt’
Here, Qtt & Qt+1t+1 are present state & next state respectively
...
The following table shows the characteristic table of T flip-flop
...
Hence, T flip-flop can be used in counters
...
Similarly, you can
implement these flip-flops by using NAND gates
...
We can convert one
flip-flop into the remaining three flip-flops by including some
additional logic
...
Follow these steps for converting one flip-flop to the other
...
Fill the excitation values inputsinputs of given flip-flop
for each combination of present state and next state
...
Present
State
Next
State
SR flipflop
inputs
D flipflop
input
JK flipflop
inputs
T flipflop
input
Qtt
Qt+1t+1
S
R
D
J
K
T
0
0
0
x
0
0
x
0
0
1
1
0
1
1
x
1
1
0
0
1
0
x
1
1
1
1
x
0
1
x
0
0
•
•
Get the simplified expressions for each excitation
input
...
Draw the circuit diagram of desired flip-flop according
to the simplified expressions using given flip-flop and
necessary logic gates
...
Follow the same
process for remaining flipflop conversions
...
SR flip-flop to D flip-flop
• SR flip-flop to JK flip-flop
• SR flip-flop to T flip-flop
SR flip-flop to D flip-flop conversion
•
Here, the given flip-flop is SR flip-flop and the desired flip-flop is
D flip-flop
...
D flip-flop
input
Present
State
Next
State
D
Qtt
Qt+1t+1
0
0
0
0
1
0
1
0
1
1
1
1
We know that SR flip-flop has two inputs S & R
...
The following table shows
the characteristic table of D flip-flop along with the excitation
inputs of SR flip-flop
...
S=m2+d3S=m2+d3
R=m1+d0R=m1+d0
We can use 2 variable K-Maps for getting simplified expressions
for these inputs
...
So, we got S = D & R = D' after simplifying
...
This circuit consists of SR flip-flop and an inverter
...
So, the
overall circuit has single input, D and two outputs Qtt & Qtt'
...
Similarly, you can do other two
conversions
...
D flip-flop to T flip-flop
• D flip-flop to SR flip-flop
• D flip-flop to JK flip-flop
D flip-flop to T flip-flop conversion
•
Here, the given flip-flop is D flip-flop and the desired flip-flop is
T flip-flop
...
T flip-flop
input
Present
State
Next
State
T
Qtt
Qt+1t+1
0
0
0
0
1
1
1
0
1
1
1
0
We know that D flip-flop has single input D
...
The following table shows the
characteristic table of T flip-flop along with the excitation
input of D flip-flop
...
D=T⊕Q(t)D=T⊕Q(t)
So, we require a two input Exclusive-OR gate along with D flipflop
...
This circuit consists of D flip-flop and an Exclusive-OR gate
...
So, the overall circuit has single input, T and two outputs
Qtt & Qtt’
...
Similarly, you can do other
two conversions
...
JK flip-flop to T flip-flop
• JK flip-flop to D flip-flop
• JK flip-flop to SR flip-flop
JK flip-flop to T flip-flop conversion
•
Here, the given flip-flop is JK flip-flop and the desired flip-flop is
T flip-flop
...
T flip-flop
input
Present
State
Next
State
T
Qtt
Qt+1t+1
0
0
0
0
1
1
1
0
1
1
1
0
We know that JK flip-flop has two inputs J & K
...
The following table shows
the characteristic table of T flip-flop along with the excitation
inputs of JK flipflop
...
J=m2+d1+d3J=m2+d1+d3
K=m3+d0+d2K=m3+d0+d2
We can use 2 variable K-Maps for getting simplified expressions
for these two inputs
...
So, we got, J = T & K = T after simplifying
...
This circuit consists of JK flip-flop only
...
Just connect the same input T to both J & K
...
Hence, it is a T flip-flop
...
T Flip-Flop to other Flip-Flop Conversions
Following are the three possible conversions of T flip-flop to
other flip-flops
...
Therefore, consider the characteristic table of D flipflop and write down the excitation values of T flip-flop for each
combination of present state and next state values
...
D flip-flop
input
Present
State
Next
State
T flip-flop
input
D
Qtt
Qt+1t+1
T
0
0
0
0
0
1
0
1
1
0
1
1
1
1
1
0
From the above table, we can directly write the Boolean function
of T as below
...
The circuit diagram of D flip-flop is shown in the following
figure
...
This
Exclusive-OR gate produces an output, which is Ex-OR of D and
Qtt
...
Hence, it is a D flip-flop
...