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Digital Circuits - De-Multiplexers
The opposite function of the multiplexer is performed by a
combinational circuit known as a de-multiplexer
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One of
these outputs will be coupled to the input based on the values
of the selection lines
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Thus, each combination allows for the
selection of a single output
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1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 &
s0 and four outputs Y3, Y2, Y1 &Y0
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The single input ‘I’ will be connected to one of the four outputs,
Y3 to Y0 based on the values of selection lines s1 & s0
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Selection Inputs

Outputs

S1

S0

Y3

Y2

Y1

Y0

0

0

0

0

0

I

0

1

0

0

I

0

1

0

0

I

0

0

1

1

I

0

0

0

From the above Truth table, we can directly write the Boolean
functions for each output as
Y3=s1s0IY3=s1s0I
Y2=s1s0′IY2=s1s0′I
Y1=s1′s0IY1=s1′s0I
Y0=s1′s0′IY0=s1′s0′I
We can implement these Boolean functions using Inverters & 3input AND gates
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The aforementioned circuit's functionality is simple to
comprehend
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Implementation of Higher-order De-Multiplexers
Now, let us implement the following two higher-order DeMultiplexers using lower-order De-Multiplexers
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We are aware of
the one input, two selection lines, and four outputs of the 1x4
De-Multiplexer
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Therefore, in order to achieve the final eight outputs, the second
stage needs two 1x4 De-Multiplexers
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The total input for the 1x8 DeMultiplexer will be used as the input for this 1x2 De-Multiplexer
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The Truth table of 1x8 DeMultiplexer is shown below
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The block diagram of 1x8 De-Multiplexer is shown in the
following figure
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The outputs of upper 1x4 De-Multiplexer are Y7 to
Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to Y0
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If
s2 is zero, then one of the four outputs of lower 1x4 DeMultiplexer will be equal to input, I based on the values of
selection lines s1 & s0
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1x16 De-Multiplexer
In this section, let us implement 1x16 De-Multiplexer using 1x8
De-Multiplexers and 1x2 De-Multiplexer
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Whereas, 1x16 De-Multiplexer has single input, four
selection lines and sixteen outputs
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Since, the number of inputs in
second stage is two, we require 1x2 DeMultiplexer in first stage
so that the outputs of first stage will be the inputs of second
stage
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Let the 1x16 De-Multiplexer has one input I, four selection lines
s3, s2, s1 & s0 and outputs Y15 to Y0
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The common selection lines s2, s1 & s0 are applied to both 1x8
De-Multiplexers
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The other selection line, s3 is applied to 1x2 De-Multiplexer
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Similarly, if s3 is one, then one of the 8
outputs of upper 1x8 De-Multiplexer will be equal to input, I
based on the values of selection lines s2, s1 & s0
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They contain an array of AND gates & another array of
OR gates
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• Programmable Read Only Memory
• Programmable Array Logic
• Programmable Logic Array
The process of entering the information into these devices is
known as programming
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Here, the term
programming refers to hardware programming but not software
programming
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That means, we can’t
change that stored information by any means later
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The user has the flexibility to program the

binary information
programmer
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The block diagram of PROM is shown
in the following figure
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So,
we have to generate 2n product terms by using 2n AND gates
having n inputs each
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So, this decoder generates ‘n’ min terms
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That means, we
can program any number of required product terms, since all the
outputs of AND gates are applied as inputs to each OR gate
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Example
Let us implement the following Boolean functions using PROM
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So, we require a 3 to

8 decoder and two programmable OR gates for producing these
two functions
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Here, 3 to 8 decoder generates eight min terms
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But, only the required min terms are programmed in order to
produce the respective Boolean functions by each OR gate
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Programmable Array Logic PALPAL
PAL is a programmable logic device that has Programmable AND
array & fixed OR array
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The block diagram of PAL is shown in the following
figure
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That means
each AND gate has both normal and complemented inputs of
variables
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So, we can generate only the required product
terms by using these AND gates
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So,
the number of inputs to each OR gate will be of fixed type
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Therefore, the outputs of PAL will be in the form of sum
of products form
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A=XY+XZ′A=XY+XZ′
A=XY′+YZ′A=XY′+YZ′
The given two functions are in sum of products form
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So, we
require four programmable AND gates & two fixed OR gates for

producing those two functions
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The programmable AND gates have the access of both normal
and complemented inputs of variables
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So, program only the required literals in order to
generate one product term by each AND gate
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Here, the inputs of OR gates are of fixed type
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So that
the OR gates produce the respective Boolean functions
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’ is used for fixed connections
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Hence, it is the most
flexible PLD
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Here, the inputs of AND gates are programmable
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So, based on the requirement, we can program any of
those inputs
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Here, the inputs of OR gates are also programmable
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Therefore, the outputs of PAL will be in the form of sum of
products form
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A=XY+XZ′A=XY+XZ′
B=XY′+YZ+XZ′B=XY′+YZ+XZ′

The given two functions are in sum of products form
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One product term, Z′XZ′X is
common in each function
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The
corresponding PLA is shown in the following figure
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In the above figure, the
inputs X, X′X′, Y, Y′Y′, Z & Z′Z′, are available at the inputs of each
AND gate
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All these product terms are available at the inputs of
each programmable OR gate
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The symbol ‘X’ is used for
programmable connections
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Except NOT gate, the
remaining all logic gates have at least two inputs and single
output
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Additionally, it contains the respective weights to each input and
a threshold value
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Basics of Threshold gate
Let the inputs of threshold gate are X1, X2, X3,…, Xn
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The symbol of Threshold gate is shown in the following figure
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This circle is made into two
parts
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The sum of products of inputs with corresponding weights is
known as weighted sum
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Otherwise, the output, Y will be equal to zero
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Y=1,ifW1X1+W2X2+W3X3+
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WnXn≥T
𝑌 = 0, otherwise
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Example
Let us find the simplified Boolean function for the following
Threshold gate
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The weights corresponding to the inputs X1, X2 & X3 are W1 = 2,
W2 = 1 & W3 = -4 respectively
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The weighted sum of Threshold gate is
W=W1X1+W2X2+W3X3W=W1X1+W2X2+W3X3
Substitute the given weights in the above equation
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The following table shows the relationship between the input
and output for all possible combination of inputs
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Therefore, the simplified Boolean function for given Threshold
gate is Y=X′3+X1X2Y=X3′+X1X2
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Sometimes, it may not possible to implement few logic gates and
Boolean functions by using single Threshold gate
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Follow these steps for implementing a Boolean function using
single Threshold gate
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Step 2 − In the above Truth table, add includeinclude one more
column, which gives the relation between weighted
sums and Threshold value
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•

If the output of Boolean function is 1, then the
weighted sum will be greater than or equal to
Threshold value for those combination of inputs
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Step 4 − Choose the values of weights & Threshold in such a way
that they should satisfy all the relations present in last column of
the above table
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Example
Let us implement the following Boolean function using single
Threshold gate
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The Truth table of this
function is shown below
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This last column contains the relations
between weighted sums WW and Threshold value TT for each
combination of inputs
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•

•

•

•

The value of Threshold should be either zero or
negative based on first relation
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The values of W1 and W2 should be greater than or
equal Threshold value based on fifth and third
relations
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We can choose the following values for weights and Threshold
based on the above conclusions
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Therefore, this Threshold gate implements the given Boolean
function, Y(X1,X2,X3)=∑m(0,2,4,6,7)Y(X1,X2,X3)=∑m(0,2,4,6,7)

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