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Digital Circuits - Decoders
A decoder is a type of combinational circuit that can have up to
2n output lines and 'n' input lines
...
This shows that a certain code has
been discovered by the decoder
...
2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3,
Y2, Y1 & Y0
...
One of these four outputs will be ‘1’ for each combination of
inputs when enable, E is ‘1’
...
Enable
Inputs
Outputs
E
A1
A0
Y3
Y2
Y1
Y0
0
x
x
0
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
1
1
0
0
0
From Truth table, we can write the Boolean functions for each
output as
Y3=E
...
A0Y3=E
...
A0
Y2=E
...
A0′Y2=E
...
A0′
Y1=E
...
A0Y1=E
...
A0
Y0=E
...
A0′Y0=E
...
A0′
Each output only contains one product phrase
...
Four AND gates with
three inputs and two inverters each can be used to implement
these four product phrases
...
Therefore, the outputs of 2 to 4 decoder are nothing but the min
terms of two input variables A1 & A0, when enable, E is equal to
one
...
Similarly, 3 to 8 decoder produces eight min terms of three input
variables A2, A1 & A0 and 4 to 16 decoder produces sixteen min
terms of four input variables A3, A2, A1 & A0
...
3 to 8 decoder
• 4 to 16 decoder
3 to 8 Decoder
•
In this section, let us implement 3 to 8 decoder using 2 to 4
decoders
...
Whereas, 3 to 8 Decoder has three
inputs A2, A1 & A0 and eight outputs, Y7 to Y0
...
Requirednumberoflowerorderdecoders=m2m1Requirednumbe
roflowerorderdecoders=m2m1
Where,
m1m1 is the number of outputs of lower order decoder
...
Here, m1m1 = 4 and m2m2 = 8
...
Requirednumberof2to4decoders=84=2Requirednumberof2to4
decoders=84=2
Therefore, we require two 2 to 4 decoders for implementing one
3 to 8 decoder
...
The parallel inputs A1 & A0 are applied to each 2 to 4 decoder
...
These are
the lower four min terms
...
These are the higher four min terms
...
We know that 3 to 8 Decoder has three inputs A2, A1 &
A0 and eight outputs, Y7 to Y0
...
Requirednumberoflowerorderdecoders=m2m1Requirednumbe
roflowerorderdecoders=m2m1
Substitute, m1m1 = 8 and m2m2 = 16 in the above formula
...
The block diagram of 4 to 16 decoder using 3 to
8 decoders is shown in the following figure
...
The complement of input, A3 is connected to Enable, E of lower
3 to 8 decoder in order to get the outputs, Y7 to Y0
...
The input, A3 is directly connected to
Enable, E of upper 3 to 8 decoder in order to get the outputs,
Y15 to Y8
...
Digital Circuits - Encoders
A combinational circuit known as an encoder executes the
opposite function of a decoder
...
It will generate a binary code with
the same active High value as the input
...
The enable signal
representation in encoders is optional
...
The block diagram of 4 to 2 Encoder is shown in the
following figure
...
The Truth table of 4 to
2 encoder is shown below
...
The circuit diagram of 4 to 2 encoder is
shown in the following figure
...
These OR gates
encode the four inputs with two bits
Octal to Binary Encoder
Octal to binary Encoder has eight inputs, Y7 to Y0 and three
outputs A2, A1 & A0
...
The block diagram of octal to binary Encoder is shown
in the following figure
...
The Truth table of octal to binary
encoder is shown below
...
The circuit diagram of octal to binary encoder is
shown in the following figure
...
These
OR gates encode the eight inputs with three bits
...
•
•
There is an ambiguity, when all outputs of encoder are
equal to zero
...
If more than one input is active High, then the encoder
produces an output, which may not be the correct
code
...
This is neither
equivalent code corresponding to Y3, when it is ‘1’ nor
the equivalent code corresponding to Y6, when it is ‘1’
...
Then, the output of encoder will be
the binarybinary code corresponding to the active High inputss,
which has higher priority
...
Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two
outputs A1 & A0
...
In this case, even if
more than one input is ‘1’ at the same time, the output will be
the binarybinary code corresponding to the input, which is
having higher priority
...
•
•
If at least one input of the encoder is ‘1’, then the code
available at outputs is a valid one
...
If all the inputs of encoder are ‘0’, then the code
available at outputs is not a valid one
...
The Truth table of 4 to 2 priority encoder is shown below
...
The simplified Boolean functions are
A1=Y3+Y2A1=Y3+Y2
A0=Y3+Y2′Y1A0=Y3+Y2′Y1
Similarly, we will get the Boolean function of output, V as
V=Y3+Y2+Y1+Y0V=Y3+Y2+Y1+Y0
We can implement the above Boolean functions using logic
gates
...
Two 2-input OR gates, a 4-input OR gate, a 2-input AND gate, and
an inverter are all included in the circuit diagram above
...
Therefore, based on the priority given to
each input, this circuit encodes the four inputs with two bits
...
One of
these data inputs will be connected to the output based on the
values of selection lines
...
So, each combination will select
only one data input
...
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection
lines s1 & s0 and one output Y
...
One of these 4 inputs will be connected to the output based on
the combination of inputs present at these two selection
lines
...
Selection Lines
Output
S1
S0
Y
0
0
I0
0
1
I1
1
0
I2
1
1
I3
From Truth table, we can directly write the Boolean function for
output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+
S1S0I3
We can implement this Boolean function using Inverters, AND
gates & OR gate
...
We can easily understand the operation of the above circuit
...
Implementation of Higher-order Multiplexers
...
8x1 Multiplexer
• 16x1 Multiplexer
8x1 Multiplexer
•
In this section, let us implement 8x1 Multiplexer using 4x1
Multiplexers and 2x1 Multiplexer
...
Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output
...
Since, each 4x1 Multiplexer produces one
output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce
the final output
...
The Truth table of
8x1 Multiplexer is shown below
...
The block diagram of 8x1 Multiplexer is shown in the following
figure
...
The data inputs of upper 4x1 Multiplexer are I7 to
I4 and the data inputs of lower 4x1 Multiplexer are I3 to I0
...
The outputs of first stage 4x1 Multiplexers are applied as inputs
of 2x1 Multiplexer that is present in second stage
...
•
•
If s2 is zero, then the output of 2x1 Multiplexer will be
one of the 4 inputs I3 to I0 based on the values of
selection lines s1 & s0
...
Therefore, the overall combination of two 4x1 Multiplexers and
one 2x1 Multiplexer performs as one 8x1 Multiplexer
...
We know that 8x1 Multiplexer
has 8 data inputs, 3 selection lines and one output
...
So, we require two 8x1 Multiplexers in first stage in order to get
the 16 data inputs
...
Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four
selection lines s3 to s0 and one output Y
...
Selection Inputs
Output
S3
S2
S1
S0
Y
0
0
0
0
I0
0
0
0
1
I1
0
0
1
0
I2
0
0
1
1
I3
0
1
0
0
I4
0
1
0
1
I5
0
1
1
0
I6
0
1
1
1
I7
1
0
0
0
I8
1
0
0
1
I9
1
0
1
0
I10
1
0
1
1
I11
1
1
0
0
I12
1
1
0
1
I13
1
1
1
0
I14
1
1
1
1
I15
We can implement 16x1 Multiplexer using lower order
Multiplexers easily by considering the above Truth table
...
The same selection lines, s2, s1 & s0 are applied to both 8x1
Multiplexers
...
Therefore, each 8x1 Multiplexer produces an output based on
the values of selection lines, s2, s1 & s0
...
The
other selection line, s3 is applied to 2x1 Multiplexer
...
If s3 is one, then the output of 2x1 Multiplexer will be
one of the 8 inputs I15 to I8 based on the values of
selection lines s2, s1 & s0
...