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Introduction
Analog-to-digital conversion is the process of converting analog signals (signals which
vary over a continuous range of values) to digital form (a binary code), while digital to analog conversion is the process of converting a digital signals into an analog
form
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g
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To process such information using digital devices, these signals
have to be converted to digital form
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To store this information in a digital computer, it has to be converted into digital form using an analogto-digital converter
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For the sound signals, analog-to-digital and
digital-to-analog conversion is normally done in the sound card
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The last two decades have seen an exponential increase in the computing power and speed of digital computers as well as the
dramatic fall in their prices, factors which have led to their widespread use in process
control
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This chapter examines the devices used for analog-to-digital and digital-to-analog
conversion
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verter in their circuitry, hence, digital-to-analog converters are considered first
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Digital-to-Analog Conversion

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1 Introduction
Digital to analog conversion is the process of taking a value represented in a binary
code and converting it to a voltage or current that is proportional to the digital value
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The device which performs this conversion is known as a Digital to
Analog Converter (DAC)
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For
an unsigned binary code bn bn−1
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+ b1 × 21 + b0 × 20
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+ b1 × 21 + b0 × 20
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The output voltage can
thus be considered to be the weighted sum of the digital inputs
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This weighting factors are the basis on which Digital-to-Analog Converters (DACs) are made
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The resistors are weighted so that the resistors are inversely
proportional to the numerical significance of the corresponding numerical digit
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An operational amplifier is employed as a summing amplifier which produces a weighted sum
of the input voltages
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DCBA is a four-bit digital word
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MSB

D
C
B

LSB A

R
R

2R
4R

−

8R

+

VOU T

Figure 1: Weighted resistor DAC
For VREF = 5V , the outputs from the above equation can be tabulated as below:
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

VOU T
0
-0
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250
-1
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500
-3
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750
-4
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000
-5
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250
-6
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500
-8
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750
-9
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From the table above, we can see
that the resolution of the DAC is 0
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375V
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2V
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5R then




B
C
D R
A
B C D
A
+
+
+
= −VREF
+ + +
(4)
VOU T = −VREF
8R 4R 2R R 2
16
8
4
2
In this case, the resolution is 0
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4M Ω
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temperature range are difficult to produce
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An 8-bit modified weighted resistor
DAC is shown on Figure 2
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The portion of the circuit corresponding
to this is shown in Figure 3
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Again noting that resistors
the current I as:

8R
7

and r are in parallel, we can write the expression for



VREF 8R
+r
VREF
7

= 15rR 8R2

I=
R + r// 8R
+ 7
7
7

(5)

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We can therefore write

1
16

of this

VREF
VREF 8R
=
2
15rR + 8R
16R

(7)

r = 8R

(8)

which simplifies to:
Exercise
Given the circuit shown on Figure 2, assuming that the code b
BCD code, show that r = 4
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7 b6 b5 b4 b3 b2 b1 b0

is in

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4 The R-2R Ladder Network
The R-2R ladder network uses resistors of only two sizes, R and 2R
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Bits are weighted by providing paths for current division with consequent successive attenuations for bits of lower significance
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An example of a 4-bit R-2R ladder network is shown in Figure 5
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In the example shown in Figure 5, the input code
DCBA = 0001
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As such, it is the R-2R ratio of the resistors that is important and not the absolute value of the resistors
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The op-amp therefore converts binary-scaled currents to an output voltage
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R

R

2R

R

2R

2R

2R

A

B

C

LSB

RF

2R

−

2R

+

VOU T

D

MSB

VREF

Figure 5: R-2R ladder network
Making RF adjustable allows the output voltage to be set to any desired range within
the saturation limits of the operational amplifier
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The equivalent circuit is shown in Figure 6
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5I

0
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25I

0
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0625I

0
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125I

0
...

0
...
5I
I

2R

2R

2R

VREF

Figure 7: R-2R ladder network: simplified circuit

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I
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0625I
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125I, 0
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5I
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(10)
VOU T = − D × + C × + B × + A ×
2
4
8
16
Substituting (9) into (10) gives
VOU T

VREF
=−
3R




D C B
A
+ + +
RF
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2
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DIGITAL
INPUTS

ANALOG
OUTPUT

Figure 8: DAC symbol

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6 Specifications of DACs
Resolution The smallest change that can occur in the analog output as a result of a
change in the digital input
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An ideal DAC should have an infinitely small resolution
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In an actual circuit, the inputoutput relationship is not linear
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The linearity of a converter is a measure of
the precision with which the linear input-output relationship is satisfied
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It is usually specified as a percentage of the
full-scale output voltage
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It is the time
required for the output to go from zero to full-scale as the binary inputs are
varied from all zeros to all ones
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Temperature sensitivity specifies by how much the output
changes per unit change in temperature
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In practice, there will be a small output voltage caused by
the offset error in the output op-amp
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Examples of DAC ICs are 12-bit AD767, 8-bit AD557JN (these two ICs are microprocessorcompatible), 8-bit ZN425E, 8-bit ZN435E, 8-bit ZN428E etc
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There are many methods of analog
to digital conversion and in this course, we shall look at the most common methods
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(For the comparator
shown in the figure, if VA > VB , EOC = HIGH, and VA < VB , EOC = LOW
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When the START pulse
is HIGH, it inhibits the AND gate so that no clock pulses get through to the counter
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When the START pulse returns LOW, the AND gate is enabled and pulses allowed into
the counter
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When VB reaches VA , the comparator output goes LOW,
inhibiting pulses to the counter so that the counter stops and holds the desired digital

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The HIGH to LOW transition at the comparator output signals
the End Of Conversion (EOC)
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The conversion time
is the interval between t0 and t1
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Exercise
A ramp ADC has a clock running at a frequency of 1MHz
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95V for a 12-bit output
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828V
iii) The conversion time for VA = 7
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(10mV, 001100001111, 783 µsec, 4095 µsec)

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It works by trying various binary codes
and feeding them into a DAC and comparing the result with the analog input via a
comparator
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(For the comparator shown
in the figure, if VA > VB , COMP = HIGH, and if VA < VB , COMP = LOW
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This produces a value of VB at the DAC output that is equal to the weight of
the MSB
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Otherwise the MSB is
kept HIGH
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This produces a new
value of VB
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Otherwise the bit is kept
at 1
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After all the bits have
been tried, the register holds the digital equivalent of VA
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(In other words for
a given number of bits, the conversion time is constant)
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If an input voltage of 37
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STEP
1
2
3
4
5
6

ACTION
Initial State
Set MSB to 1
Set 2N D bit to 1
Set 3RD bit to 1
Set 4T H bit to 1
Set 5T H bit to 1
Set 6T H bit to 1

REGISTER CONTENTS
000000
100000
110000
101000
100100
100110
100101

VB
0
32
48
40
36
38
37

VA
37
...
4
37
...
4
37
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4
37
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4V is the final value in the register, which is 100101
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CODE

VB

111111 (=63V)

110000

101000
100110
100101

100100
100000 (=32V)

VA

100000

000000 (=0V)
1st Iteration

2nd Iteration

3rd Iteration

4th Iteration

Figure 12: Profile of voltage V

B

5th Iteration

6th Iteration

time

during the conversion

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3 Dual Slope Integration ADC (the integrating converter)
The block diagram of the dual-slope integration converter is shown in Figure 13
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The input voltage causes the capacitor connected to the op-amp to charge at a rate dependent on the magnitude of the
input voltage
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Substituting these values and integrating gives
VOU T = −

VIN t
RC

(13)

Equation (13) is the equation of a straight line starting at the origin and with a
IN

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SWITCH

V

IN
ANALOG
INPUT

T1

C

R

VOUT

T2

−

−VREF

−

+

+

INTEGRATOR

COMPARATOR

CLOCK

CONTROL
LOGIC
COUNTER
DIGITAL OUTPUT

Figure 13: Dual-Slope ADC
For a fixed time T1 ,
VOU T = −

VIN T1
RC

(14)

Hence
integrator output for a fixed time T1 ∝ input voltage VIN
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The
higher the input voltage VIN , the greater the charge stored in the capacitor during
T1
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The control logic also starts the counter the moment
the switch is moved to T2
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The value in the counter is directly
proportional to the input voltage VIN
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During the discharge phase, the input voltT1

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(16)
VOU T = −
RC 0
RC
Integrating,
VOU T =

VREF t VIN T1
−
RC
RC

This is an equation of a straight line with a gradient

VREF
RC

(17)

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Substituting this in equation
(17) gives
VIN T1

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e
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The charging and discharging graphs are shown on Figure 14
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T1
0

t

V1
V2

V3
VOUT

Figure 15: Dual-Slope ADC with analog inputs V

1,

V2 and V3 where V1 < V2 < V3

Dual-slope converters are very accurate , but they are slow as they are essentially
counting converters
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Advantages of dual slope
ADCs compared to other ADCs are simplicity, low cost and relative immunity to noise
due to the long conversion time
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4 Flash ADCs
These are the fastest ADCs, where the conversion time equals the sum of the comparator plus encoder propagation delays
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A 3-bit flash ADC is illustrated in Figure 16
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10V
3K

C7

−
+

1K

−

C6

−

C5

+

1K

+

1K

C4

−
+

1K

C3

−
+

1K

C2

−
+

1K

C1

−
+

1K

I7

I6
C

MSB

I5
PRIORITY

B DIGITAL

ENCODER

A

I4
I3

OUTPUTS
LSB

I2
I1
I0

VIN
ANALOG
INPUT

Figure 16: Flash ADC
The operation of this converter can be summarized in the table shown below:
VIN
< 1V
≥ 1V , < 2V
≥ 2V , < 3V
≥ 3V , < 4V
≥ 4V , < 5V
≥ 5V , < 6V
≥ 6V , < 7V
≥ 7V

C!
1
0
0
0
0
0
0
0

C2
1
1
0
0
0
0
0
0

C3
1
1
1
0
0
0
0
0

C4
1
1
1
1
0
0
0
0

C5
1
1
1
1
1
0
0
0

C6
1
1
1
1
1
1
0
0

C7
1
1
1
1
1
1
1
0

C
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

The main disadvantage of this converter is the large number of comparators required
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The use of flash ADCs is restricted to applications
where speed is the prime requirement
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5 ADC symbol
The symbol for an ADC is shown in Figure 17
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• Input impedance 1KΩ to 1M Ω
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• Format of the output digital code - 2s complement, unsigned binary, BCD etc
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More information about these ICs can be obtained from data books

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