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VLSI DESIGN
Dr
...
Abirami
Assistant Professor / EEE
BSACIST
1

EED 3104 – VLSI DESIGN (LIT)
COURSE OBJECTIVES:
COB 1: To apply the concepts of modeling in digital system using Verilog HDL
...

COB 3: To understand the design procedures of digital logic circuits
...

MODULE II TRANSISTOR THEORY
Introduction to MOS Transistors - NMOS & PMOS Characteristics,
Current Equations, Complementary CMOS Inverter - DC
Characteristics, Static Load MOS Inverters, Differential inverters
...

MODULE IV BUILDING BLOCKS OF DIGITAL VLSI SYSTEMS
Data Path Circuit, Adders – Types of fast adders, Multipliers – array
multipliers, Shifters, Memory Elements, Programmable logic elements
and AND-OR arrays, FPGA and CPLD
...
Study of simulation tools and synthesis tools
2
...

3
...

4
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5
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Design, simulation and synthesis of flip flops using Xilinx Software and
FPGA
...
Design, simulation and synthesis of Counters using Xilinx Software and
FPGA
5

TEXT BOOKS: 1
...
Sinha ,
“Digital VLSI Design and Simulation with Verilog”, John Wiley & Sons, 9 March 2022
...
Samir Palnitkar, “Verilog HDL, A guide to digital design and synthesis”, PHI, 2010
...
D
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Kothari and J
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4
...
E Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design – A Circuits and Systems
Perspective”, 4th Ed, Pearson Education, Noida, India, 2014
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John P
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Wiley, 2nd Edition, New
York, 2009
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Charles H
...
S
...

2
...

3
...

6

COURSE OUTCOMES: At the end of the course, the students will be
able to
CO1: apply the basic concepts and different levels of abstraction in
Verilog HDL
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CO3: design and Illustrate CMOS based digital circuit designs, data
path and arithmetic circuits for processor design
...

Assignment 1
Quiz

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INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining thousands
of transistors into a single chip
...
The microprocessor is a VLSI device
...

These include programming languages like Perl and TCL, VHDL,
Verilog, and System Verilog
...
The Verilog language describes a digital
system as a set of modules
...

➢ It is a language used for describing a digital system like a
network switch or a microprocessor or a memory or a
flip−flop
...

➢ Designs, which are described in HDL are independent of
technology, very easy for designing and debugging, and are
normally more useful than schematics, particularly for large
circuits
...

Any Program in Verilog starts with the
reserved word module
...

$finish is a Verilog system task that tells
the simulator to terminate the current
simulation
...

❑ This just means that, by using a HDL, one can describe any (digital) hardware at
any level
...

reg - used for memory elements, can store values, needs
procedural assignments, and defined in combinatorial logic
(always, initial, task, function blocks)
...

❑ Verilog is one of the HDL languages available in the industry
for hardware designing
...

❑ Verilog allows hardware designers to express their designs
with behavioral constructs, deferring the details of
implementation to a later stage in the final design
...


Bottom-Up Design
The traditional method of electronic design is bottom-up
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With the increasing complexity of new designs this approach is nearly impossible to
maintain
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These traditional bottom-up designs have to give way to new structural, hierarchical
design methods
...

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❑ In a bottom-up design methodology, we first identify the building
blocks that are available to us
...

❑ These cells are then used for higher-level blocks until we build the
top-level block in the design
...

❑ A real top-down design allows early testing, easy change of
different technologies, a structured system design and
offers many other advantages
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❑ Due to this fact most designs are a mix of both methods,
implementing some key elements of both design styles
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❑ We further subdivide the sub-blocks until we come to leaf cells,
which are the cells that cannot further be divided
...


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Verilog supports designing at many different levels of abstraction
...


❑The order of abstraction mentioned above are from highest to lowest level of
abstraction
...

Every algorithm is sequential, which means it consists of a set of
instructions that are executed one by one
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There is no regard to the structural realization of the design
...

Modern definition of an RTL code is "Any code that is synthesizable is
called RTL code“ - Synthesis in VLSI is the process of converting our code

(program) into a circuit
...


Gate Level or Structural Level
Within the logical level, the characteristics of a system are described by
logical links and their timing properties
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They can only have definite logical values (`0', `1', `X', `Z`)
...
Gate
level modelling may not be a right idea for logic design
...

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Behavioural Modeling
This is the highest level of abstraction in Verilog modeling in which we
describe hardware like an algorithm or any algorithm can be described
using behavioral modeling
...
For AND gate, output is 1 only when both inputs are 1
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1
...
output that we are assigning something must be reg
(Register) type
...
We use assign keyword in data flow
modeling
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module and_gate_dataflow (
input a,b,
output y
);
assign y = a & b;
endmodule
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Structural Modeling

Structural modeling is also known as gate level modeling
...

1
...
and(out,in1,in2)
3
...
nand(out,in1,in2)
5
...
xor(out,in1,in2)
7
...

Behavioral level or Algorithmic Level

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❑ This is the highest level of abstraction provided by Verilog
HDL
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❑ It specifies the circuit in terms of its expected behavior
...

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Register−Transfer Level or Data Flow Level

❑ At this level, the module is designed by specifying the data flow
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❑ This style is similar to logical equations
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❑ In most cases, such an approach can be quite easily translated
into a structure and then implemented
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❑ It resembles a schematic drawing with components
connected with signals
...
If two or
more components are activated concurrently, they
will perform their actions concurrently as well
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❑ Since logic gate is most popular component, Verilog
has a predefined set of logic gates known
as primitives
...

41

Half Adder Using Verilog
A half adder is a digital logic circuit that performs binary addition of two single-bit
binary numbers
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❑ Sum is the XOR of inputs A&B
❑ Carry is the AND of inputs A&B

Truth Table

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K-Map

S= A B' + A' B
S= A XOR B

Carry= A
...

➢ Verilog language source text files are a stream of lexical
tokens
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➢ All lines should be terminated by a semicolon(;)
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➢ All the key words are in lower case
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Comments
2
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Operators
4
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Strings
6
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Keywords
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DATA TYPES IN VERILOG HDL
A storage format having a specific range or type is called data type
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1
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Ex
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2
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They are used as variables
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reg, integer
Verilog supports 4 types of logic values as
Logic values

Description

1

Logic one, true condition

0

Logic zero, false condition

x

Unknown value

z

High impedance
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Nets

Nets represent physical connections between the digital
circuits
...
The term
net is not a keyword, it is a group of data types such as
wire, wand, wor, tri, etc
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wire [5:0] a; //net as a vector

Note:
1
...

2
...

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Registers

The registers represent data storage elements
...
The registers are like a placeholder, so they do not
require a driver
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reg a; // single bit register
reg [5:0] a; // 6 bit register as a vector

Note:
1
...

2
...

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Scalars and Vectors

Scalars: Single bit wire or register is known as a scalar
...
If bit width is not specified, it is a scalar
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It is read-only in nature
...
They are declared
by the ‘integer’ keyword
...
They are declared using the ‘real’
keyword
...
14;

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String

An ordered collection of characters is called a string
...
Each character in
a string requires 1 byte (8 bits) for storage and is typically mentioned within double-quotes (” “)
...

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Identifiers
❑ Identifiers are names used to give an object, such as a register or a function or
a module, a name so that it can be referenced from other places in a
description
...

Examples of legal identifiers

data_input mu
clk_input my$clk
i386 A
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65

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Escaped Identifiers
Verilog HDL allows any character to be used in an identifier by escaping
the identifier
...


❑Escaped identifiers begin with the back slash ( \ )
❑Entire identifier is escaped by the back slash
...

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Examples of escape identifiers
Verilog does not allow to identifier to start with a numeric character
...

// There must be white space after the string which uses escape character
module \1dff (
q, // Q output
\q~ , // Q_out output
d, // D input
cl$k, // CLOCK input
\reset* // Reset input
);
input d, cl$k, \reset* ;
output q, \q~ ;

endmodule
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69

Verilog code for full adder – Using case statement
The case statement in Verilog is much similar to switch- case
statement in C language
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The expressions are executed once it fulfills the case_expression to
its case_item value
...

case(case_expression)
case_item1:procedural_expression;
case_item2: begin
procedural_statements;
end

...

default: expression;
endcase
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timescale 1ns / 1ps
module full_adder(input wire A, B, Cin, output reg S,
output reg Cout);
always @(A or B or Cin)
begin
case (A | B | Cin)
3'b000: begin S = 0; Cout = 0; end
3'b001: begin S = 1; Cout = 0; end
3'b010: begin S = 1; Cout = 0; end
3'b011: begin S = 0; Cout = 1; end
3'b100: begin S = 1; Cout = 0; end
3'b101: begin S = 0; Cout = 1; end
3'b110: begin S = 0; Cout = 1; end
3'b111: begin S = 1; Cout = 1; end
endcase
end
endmodule
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Test Bench
//timescale directive
`timescale 1ns / 1ps
module top;
//declare testbench variables
reg A_input, B_input, C_input;
wire Sum, C_output;
//instantiate the design module and connect to the testbench variables
full_adder instantiation(
...
B(B_input),
...
S(Sum),

...

We use Full Adder module to add two single bit binary numbers with an initial
input carry
...
The diagram below shows the block diagram of n Bit Parallel Adder using
number of full-adder circuits connected in cascade, i
...
the carry output of each
adder is connected to the carry input of the next higher-order adder
...

Some key applications of a 4-bit parallel adder include:
1
...

2
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