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Title: electronics questions
Description: test your electronics skill if you think you are smart in electronics ....
Description: test your electronics skill if you think you are smart in electronics ....
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AE05
BASIC ELECTRONICS
TYPICAL QUESTIONS & ANSWERS
PART - I
OBJECTIVE TYPE QUESTIONS
Each Question carries 2 marks
...
1
The breakdown mechanism in a lightly doped p-n junction under reverse biased condition is called
(A) avalanche breakdown
...
(C) breakdown by tunnelling
...
Ans: A
Q
...
3
For a large values of |VDS|, a FET – behaves as
(A) Voltage controlled resistor
...
(C) Voltage controlled current source
...
Ans: C
Q
...
(B) decrease in current gain
...
(D)decrease in voltage gain
...
5
For an op-amp having differential gain Av and common-mode gain Ac the CMRR is given by
A
(A) A v + A c
(B) v
Ac
A
Ac
(C) v + 1
(D)
Av
A
c
Ans: B
1
AE05
Q
...
(B) a sinusoidal wave
...
(D) a triangular wave with dc bias
...
7
Hysteresis is desirable in Schmitt-trigger, because
(A) energy is to be stored/discharged in parasitic capacitances
...
(C) devices in the circuit should be allowed time for saturation and desaturation
...
Ans: C
Q
...
482
(B) 1
...
79
(D) 2
...
9
A minterm of the Boolean-function, f(x, y, x) is
(A) x ′ + y + z
(B) x y z′
(C) x z
(D) (y +z) x
Ans: B
Q
...
11
Space charge region around a p-n junction
(A) does not contain mobile carriers
(B) contains both free electrons and holes
(C) contains one type of mobile carriers depending on the level of doping of the p or n
regions
(D) contains electrons only as free carriers
Ans: A
Q
...
13
In a JFET, at pinch-off voltage applied on the gate
(A) the drain current becomes almost zero
(B) the drain current begins to decrease
(C) the drain current is almost at saturation value
...
Ans: C
Q
...
15
The frequency of oscillation of a tunnel-collector oscillator having L= 30µH and C = 300pf is
nearby
(A) 267 kHz
(B) 1677 kHz
(C) 1
...
67 MHz
Ans: B
Q
...
42 KHz
The open-loop gain of an op-amp available in the market may be around
...
17
The control terminal (pin5) of 555 timer IC is normally connected to ground through a capacitor
(~ 0
...
This is to
(A) protect the IC from inadvertent application of high voltage
(B) prevent false triggering by noise coupled onto the pin
(C) convert the trigger input to sharp pulse by differentiation
(D) suppress any negative triggering pulse
Ans: B
Q
...
19
The value of ripple factor of a half-wave rectifier without filter is approximately
(A) 1
...
2
(C) 2
...
0
Ans: A
The three variable Boolean expression xy + xyz + x y + x y z
3
AE05
BASIC ELECTRONICS
(A) y + x z
(B) x + yz
(C) y + xz
(D) y + xz
Ans: C
y ( x + x) + xz ( y + y ) = y + xz
Q
...
21
In an intrinsic semiconductor, the Fermi-level is
(A) closer to the valence band
(B) midway between conduction and valence band
(C) closer to the conduction band
(D) within the valence band
Ans: C
Q
...
5 times for every 2°C increment in temperature
Ans: A
Q
...
24
In class–A amplifier, the output current flows for
(A)
(B)
(C)
(D)
a part of the cycle or the input signal
...
half the cycle of the input signal
...
Ans: B
Q
...
26
Wien bridge oscillator can typically generate frequencies in the range of
(A) 1KHz – 1MHz
(B) 1 MHz – 10MHz
(C) 10MHz – 100MHz
(D) 100MHz – 150MHz
Ans: A
Q
...
28
The transformer utilization factor of a half-wave rectifier is approximately
(A) 0
...
3
(C) 0
...
1
Ans: B
0
...
3
Q
...
y + z
(B) x + yz
(C) x
...
z
(D) x
...
z
Ans: C
x + y + z = x
...
z
Q
...
The minimum number of flipflops required to construct the counter is
(A) 8
(C) 6
Q
...
(A) (Load power + supply power) / supply power
(B) (Load power + supply power) / (load power-supply power)
(C) Load power / supply power
(D) Supply power / load power
5
AE05
BASIC ELECTRONICS
Ans
...
Q
...
(A) Hartley
(B) Colpitts
(C) Crystal
(D) Weinbridge
Ans
...
33
The gate that assumes the 1 state, if and only if the input does not take a 1 state is
called________
...
(D)
Y=
Q
...
The width of depleted region of a PN junction is of the order of a few tenths of a
___________
...
(B)
Q
...
(A) S=0, R=0
...
(C) S=1, R=1
...
Ans
...
Q
...
(A) 0
(B) 1
(C) greater than 0
(D) greater than 1
Ans
...
Q
...
(A) LC tuning
(B) Piezoelectric crystal
(C) Balanced bridge
(D) Variable frequency operation
Ans
...
38
The voltage gain of basic CMOS is approximately _________
...
(A)
Q
...
(B) Current controlled voltage device
...
(D) Voltage controlled voltage device
...
(A)
The output current depends on the input current
...
40
A bistable multivibrator is a
(A) Free running oscillator
...
(B) Triggered oscillator
...
Ans
...
Q
...
(D)
Peak inverse voltage = max secondary voltage
Vdc=2Vm/ π =100
Vm=100 π /2
Q
...
(B) The current through R1 will decrease
...
(D) zener diode current will decrease
...
(C)
Q
...
(A)
A
...
44
For a JFET, when VDS is increased beyond the pinch off voltage, the drain current
(A) Increases
(B) decreases
(C) remains constant
...
Ans
...
Now if we further increase
VDS above Vp the depletion layer expands at the top of the channel
...
45
The type of power amplifier which exhibits crossover distortion in its output is
(A) Class A
(B) Class B
(C) Class AB
(D) Class C
Ans
...
In class B, the devices being biased at cut-off, one device stops conducting
before the other device starts conducting leaving to Cross-over distortion
...
46
The main advantage of a crystal oscillator is that its output is
(A) 50Hz to 60Hz
(B) variable frequency
(C) a constant frequency
...
c
Ans
...
Hence frequency of a crystal oscillator is highly stable
...
47
The lowest output impedance is obtained in case of BJT amplifiers for
(A) CB configuration
...
(C) CC configuration
...
Ans
...
(In case of CB ≈ 450k and in case of CE ≈ 45k )
Q
...
(D)
Q
...
(D)
Q
...
(D)
Q
...
The signal needs to be amplified
...
(C)
We need to amplify 3 signal frequencies i
...
, 870 kHz, 875 kHz and 880 kHz
...
Q
...
(B)
We have two capacitors in the tank circuit, which serve as a simple ac voltage divider
...
53
The function of a bleeder resistor in a power supply is
(A) the same as that of load resistor
(B) to ensure a minimum current drain in the circuit
(C) to increase the output dc voltage
(D) to increase the output current
Ans
...
54
BASIC ELECTRONICS
In a bistable multivibrator circuit, commutating capacitor is used
(A) to increase the base storage charge
(B) to provide ac coupling
(C) to increase the speed of response
(D) to provide the speed of oscillations
Ans
...
Q
...
This excess free electron provides the n
type conductivity
...
56
The forward characteristic of a diode has a slope of approximately 50mA/V at a desired
point
...
57
Two stages of BJT amplifiers are cascaded by RC coupling
...
The overall gain of the coupled amplifier is
(A) 10x20
(B) 10+20
(C) (10+20)2
(D) (10x20)/2
Q
...
In the voltage range, Vp < VDS < BVDSS of an ideal JFET or MOSFET
(A) The drain current varies linearly with VDS
...
(C) The drain current varies nonlinearly with VDS
...
Ans: (B)
10
AE05
BASIC ELECTRONICS
It is the saturation region or pinch off region, and drain current remains almost constant
at its maximum value, provided VGS is kept constant
...
59
In a voltage shunt negative feedback amplifier system, the input resistance Ri and the output
resistance Ro of the basic amplifier are modified as follows:
(A) Ri is decreased and Ro increased
...
(C) Both Ri and Ro are increased
(D) Ri is increased and Ro is decreased
...
Q
...
(B) Increases the gain of the oscillator
...
(D) Facilitates generation of wide range of frequencies
...
The crystal is made of quartz
material and provides a high degree of frequency stability
...
61
The large signal bandwidth of an opamp is limited by its
(A) Loop gain
(B) slew rate
(C) output impedance
(D) input frequency
Ans: (B)
Q
...
Q
...
(B) increases
...
(D) increases or decreases depending on whether it is p- or n-type
...
64 The main characteristics of a Darlington Amplifier are
(A) High input impedance, high output impedance and high current gain
...
(C) High input impedance, low output impedance and high current gain
...
Ans: C
Q
...
66 The feedback factor β at the frequency of oscillation of a Wien bridge oscillator is
1
(A) 3
(B)
3
1
3
(C)
(D) −
29
29
Ans: B
Q
...
68 The ‘slew rate’ of an operational amplifier indicates
(A) how fast its output current can change
(B) how fast its output impedance can change
(C) how fast its output power can change
(D) how fast its output voltage can change
when a step input signal is given
...
69 In a clamping circuit, the peak-to peak voltage of the waveform being clamped is
(A) affected by the clamping
(B) not affected by the clamping
(C) determined by the clamping voltage value
(D) determined by the ratio of rms voltage of the waveform and the clamping voltage
Ans: B
12
AE05
BASIC ELECTRONICS
Q
...
d
...
power supply is given by
(A) product of no-load output voltage and full-load current
(B) ratio of full-load output voltage and full-load current
(C) change in output voltage from no-load to full-load
(D) change in output impedance from no-load to full-load
Ans: D
Q
...
72 In an unclocked R-S flip-flop made of NOR gates, the forbidden input condition is
(A) R = 0, S = 0
(B) R = 1, S = 0
(C) R = 0, S = 1
(D) R = 1, S = 1
Ans: D
Q
...
74 A zener diode
(A) Has a high forward voltage rating
...
(C) Is useful as an amplifier
...
Ans: B
Q
...
(B) They have high switching time
...
(D) Mobility of electrons is greater than that of holes
...
76 The maximum possible collector circuit efficiency of an ideal class A power amplifier is
(A) 15%
(B) 25%
(C) 50%
(D) 75%
13
AE05
BASIC ELECTRONICS
Ans: C
Q
...
(B) Increases the voltage gain
...
(D) Converts the amplifier into an oscillator
...
78 For generating 1 kHz signal, the most suitable circuit is
(A) Colpitts oscillator
...
(C) Tuned collector oscillator
...
Ans: D
Q
...
(B) Transformer coupled class B amplifier
...
(D) Class B amplifier
...
80 When a sinusoidal voltage wave is fed to a Schmitt trigger, the output will be
(A) triangular wave
...
(C) rectangular wave
...
Ans: B
Q
...
28 volts and no filter is use,
the maximum dc voltage across the load will be
(A) 20 2V
...
(C) 9 V
...
14 V
...
82 The logic gate which detects equality of two bits is
(A) EX-OR
(B) EX-NOR
(C) NOR
(D) NAND
Ans: B
Q
...
7 × 10 −4 s, that of B is 1
...
The ratio of
resistivity of B to resistivity of A will be
(A) 4
...
0
...
5
...
25
...
84 The overall bandwidth of two identical voltage amplifiers connected in cascade will
(A) Remain the same as that of a single stage
...
(C) Be better than that of a single stage
...
Ans: B
Q
...
(C) large power gain
...
(D) large votage gain
...
86 Which of the following parameters is used for distinguishing between a small signal and a
large-signal amplifier?
(A) Voltage gain
(B) Frequency response
(C) Harmonic Distortion
(D) Input/output impedances
Ans: D
Q
...
88 If the feedback signal is returned to the input in series with the applied voltage, the input
impedance ______
...
89 Most of linear ICs are based on the two transistor differential amplifier because of its
(A) input voltage dependent linear transfer characteristic
...
(C) High input resistance
...
90 The waveform of the output voltage for the circuit shown in Fig
...
Ans: D
Q
...
The load current can be
assumed to be ripple free
...
(C) square
(D) triangular
Ans: C
Q
...
A
(D) A + AB = A + B
Ans: B
Q
...
The load current can be
assumed to be ripple free
...
(C) square
(D) triangular
Ans: C
Q
...
A
(D) A + AB = A + B
Ans: B
16
AE05
BASIC ELECTRONICS
PART – II
NUMERICALS
Q
...
In a transformer-coupled amplifier, the transformer used has a turns ratio N1:N2 = 10:1
...
(6)
Ans: p
...
ZS = 8KΩ, Z L = ? Vin = 10V; Vo = ?
N1
ZS
=
N2
ZL
N
V
Turns ration and voltages: 1 = 1
N 2 V2
Turns ratio and impedances:
2
2
N
ZS N1
1
; i
...
Z L = ZS 2 = 8 × 103 ×
=
= 80Ω
N
N
Z1 2
100
1
N
1
Load voltage = V2 ; V2 = V1 2 = 10 × = 1 volt
...
2
The FET circuit given below in Fig
...
5M , R2 = 1
...
5mS
...
(8)
17
AE05
BASIC ELECTRONICS
Ans:
(i) Z in = R 1 || R 2 = 3
...
5MΩ = 1
...
33Ω
gm
2
...
5 × 10 −3 (2 || 20) × 103
(iii) Voltage gain A v =
=
= 0
...
82
1 + g m (R S || R L ) 1 + 2
...
3
In an amplifier with negative feedback, the gain of the basic amplifier is 100 and it employs a
feedback factor of 0
...
If the input signal is 40mV, determine
(i) voltage gain with feedback and
(ii) value of output voltage
...
33
1 + AB 1 + 100 × 0
...
33 × 40 × 10 −3 = 1
...
4
In the circuit shown below in Fig
...
The inputs
(4)
are: V1 = 9V, V2 = -3V and V3 = -1V
...
Ans:
V V
V
9 − 3 − 1
Vo = − R F 1 + 2 + 3 = −12 +
+
8
12 5
R1 R 2 R 3
= - 12(0
...
6 – 0
...
3 V
...
5
BASIC ELECTRONICS
A half-wave rectifier has a load resistance of 3
...
If the diode and secondary of the
transformer have a total resistance of 800K and the ac input voltage has 240 V (peak value),
determine:
(i)
peak, rms and average values of current through load
(ii)
DC power output
(iii) AC power input
(iv) rectification efficiency
(7)
Ans:
(i) Im = Vm
=
240
= 55
...
RL + Rf
3
...
77 mA = average current
...
91mA
...
1 watts
...
35 watts
...
1W
(iv) Rectification Effect = η =
=
= 32
...
Pac(in ) 3
...
6
A BJT has a base current of 250 µA and emitter current of 15mA Determine the collector
current gain and β
...
e
...
25 mA
IE = 15 mA
∴ IC = 15 − 0
...
75 mA
And
Q
...
75
β= C =
= 59
...
25
In the circuit shown in Fig
...
Find the quiescent values of 1D, VGS and
VDS of the FET
...
1
Ans:
The potential divider bias circuit can be replaced by Thevenin equivalent as shown, where
200 × 1300
R TH = 200K || 1
...
5K
200 + 1300
200K
VTH =
(30) = 4V
1500K
Applying Kirchoff’s Voltage law to gate–source circuit gives VGS = VTH − 4I D as there is
no gate current flow
...
substituting these values in the equation for IP
2
1 − VGS
I D = 4
4
Forming the quadratic equation in VGS
...
Solving for ID, ID = (1 – ¾) = 0
...
25(18 + 4) = 24
...
Q
...
2 below, the transistor has hFE = β =
40 and hie = 25
...
Determine values of R1 and R2 to obtain quiescent current ICQ = 100mA
...
Transformer turns ratio is primary 1:6 secondary
...
e
...
7 +
I CQ
β
RB
100 × 10 −3
R B = 0
...
0025(2 − 2k )
40
……
...
Hence, choosing a reasonable value of
2
...
7 + 0
...
2 × 103 ) = 6
...
Use equations (1) and (2) to find R1 and R2
From (1) R B (R1 + R 2 ) = R1R 2 or R1R 2 − R B R1 − R B R 2 = 0
R B R2
i
...
R1 ( R2 − RB ) − RB R2 = 0, or R1 =
R2 − R B
……
...
e
...
(5)
2
R2
R BR 2
R BR 2 + (R 2 ) − R BR 2
R − R + R2
B
2
R BVCC
simplifying, R 2 =
………(6)
(VCC − VBB )
From (4) and (6), we get
R B VCC
RB
VCC − VBB
(R B ) 2 VCC
V R
R1 =
=
= CC B
………(7)
R BVCC
VBB
− R B R B VCC
...
2 × 12
using equation (6), R 2 =
= 4
...
2
12 × 2
...
23k
6
...
2
1
i
...
R ac = a R L = (2
...
4Ω
6
As ic swings ± 80 mA either side of ICQ = 100 mA on the Rac load line, and VCEQ = 12V
(DC load line being almost vertical)
2
VCE max = VCEQ + I Cm R ac = 12 + 80 × 10 −3 × 69
...
55 = 17
...
Hence, Maximum Load voltage(secondary):
1
VL max = I cm R ac = 6 × (80 × 10 −3 )(69
...
31V
a
Hence, Maximum Load current:
1
I L max = aIcm = (80 × 10 −3 ) = 13
...
6
22
AE05
Q
...
5 x 10-3 is applied to an amplifier of open loop gain 1000
...
(4)
Ans:
If A is the gain of the basic amplifier, the overall gain Af of the amplifier with negative f
...
is
A
Af =
given A = 1000 and β = 2
...
7
1 + 1000 + 2
...
5
When A is reduced by 20%, the new A, say An = 1000 – 0
...
b
...
67
...
5 × 10 − 2
Q
...
Its load resistance is 400
...
Compute the
(i) average and rms values of load current,
(ii) ripple factor and
(iii) efficiency of rectification
...
1163 Amp
400 + 30
Average current Iavg = 2 Imax for a FWR
π
i
...
Iavg = 2 X 0
...
074A or 74 mA = Idc
λ
The r
...
s value of load current is
I
0
...
0822A or 82
...
0822) 2
Ripple factor γ = rms − 1 =
− 1 = 0
...
074) 2
dc
Efficiency of rectification in a FWR is given by
23
AE05
BASIC ELECTRONICS
η=
Q
...
812
0
...
e
...
755 or 75
...
RF
30
1+
1+
RL
400
For the circuit shown in Fig
...
(8)
Fig
...
0mA
...
12
The parameters of the transistor in the circuit shown in Fig
...
1kΩ, h re = h oe = 0
...
(8)
Fig
...
26
Q
...
567 Mf
(iii) 16
...
4, determine voltage gain, input impedance, output impedance,
common-mode gain and CMRR if VCC = 15v , VEE = −15v , R C = R E = 1MΩ and
transistors Q1 and Q2 are identical with βdc = 100
...
(8)
24
AE05
BASIC ELECTRONICS
Fig
...
66M , Zout = 1M
Acm = 0
...
5V and 0
...
14
A class B push-pull amplifier is supplied with Vcc = 40V
...
The dissipation in both the transistors
totals 30 W
...
As Pd = Pin(dc) – Pout(ac)
2
I
30 = Vcc I c max − c max (Vcc − Vc max )
π
2
2Vcc Vcc − Vc min
30 = I c max
−
2
π
2 × 40 40 − 8
= I c max
−
2
π
= I c max [25
...
46 I c max
30
or I c max =
= 3
...
46
2
2
∴ Pin ( dc) = Vcc I c max = × 40 × 3
...
712
...
17 (40 − 8)
2
2
= 50
...
72
×100
80
...
84%
Q
...
If the values of differentiating components are given as R = 40 k Ω and
C = 3µF , determine the output voltage
...
2000
...
12
dV
d
∴ Vout = −CR c = −0
...
12 × 10 × (sin 4000π t ) µv
dt
Vout = 1
...
cos 4000π t ) µv
Vout = 15
...
16
Draw the circuit of a monostable multivibrator using two transistors
...
2V , B VBE(sat ) = 0
...
The resistor and capacitor connected to the base of Q 2 have values
R B = 20 kΩ and C = 0
...
Determine the monostable pulse width
...
8
T = 20 × 103 × 0
...
8
T = 1
...
Monostable Multivibrator Circuit
26
AE05
Q
...
2 K Ω , Vz =10V and VBE = 0
...
Calculate (i) output voltage (ii) load current (iii)
the base current in the transistor (iv) zener current
...
4v, B = 50, RL = 1
...
4 = 9
...
025 A
R 200
Q
...
98 when its base current is 60µA
...
98 3 × 10 −6
+
1 − 0
...
98
−3
I C = 2
...
15 ×10 −3
Ic =
I C = 3
...
09 × 10 −3 + 50 ×10 −6
I E = 3
...
Q
...
2 K ,
hfe=52, hoe= 25µ mhos and hre is negligible
...
Determine the power gain of the amplifier using its equivalent circuit
...
(8)
+ Vcc
12K
70K
C
5K
B
CC
E
CC
Ans:
Z b = hie = 2
...
2k =
Z in =
70k × 2
...
2)k
154 × 10 6
= 2
...
2 × 103
Input impedance to E, Z S = RS + Z in
Z S = 5k + 2
...
132kΩ
Power drawn from the source, Pin =
E2
E2
=
mw
...
95
RB
RB + hie
E
70
=
m×
6
...
2
Base current, I b = I S ×
I b = 0
...
23kΩ
AC-load resistance,
Rac = Z out || RL = 9
...
23 × 10 3 × 10 × 10 3
(9
...
8kΩ
Output voltage,
Vout = − h fe I b Rac
Rac =
Vout = −52 × 0
...
8 × 103
Vout = 34
...
94 E ) 2
= 9mw
RL
10 × 10 3
1220
...
80
E = 0
...
95
Pout
Ap =
=
6
...
95 × 9
Ap =
(0
...
55
Ap =
= 848
...
0
...
20
The collector voltage of a Class B push pull amplifier with VCC=40 Volts swings down to a
minimum of 4 volts
...
Compute
the total dc power input and conversion efficiency of the amplifier
...
46 − 18]
36
= 4
...
46
2
2
∴ Pin (dc) = Vcc I c max = × 40 × 4
...
85w
I
Pout (ac) = c max (Vcc − Vc min )
2
4
...
85w
2
P (ac)
86
...
65%
Pin (dc)
122
...
21
The transistor in the feedback circuit shown below has β=200
...
In the transistor, under the conditions of
operation, VBE may be assumed to be negligible
...
8M
VO
Vin
CC
Cin
1K
Ans:
Vcc = 24V , RB = 3
...
8×10 + 1× 103
β
200
I E = 1
...
2mA
re ' = 20
...
83
AC Emitter resistance, re ' =
30
AE05
BASIC ELECTRONICS
A = 1008
...
0476
Feedback factor = β A = 0
...
16
Feedback factor = 48
...
16
Af =
=
1 + βA 1 + 48
...
57
Feedback ratio β =
Q
...
Determine the (i) output voltage (ii) the base currents and
(iii) the base voltages taking into account the effect of the RB and VBE
...
7 Volts
...
5mA
RE
8k
The collector current in transistor Q2 is half thus tail current (i
...
0
...
∴ Vout = Vcc − I c
...
75)(10k )
Tail current, IT =
Vout = 4
...
7
=
RE
8k
IT = 1
...
41m
Vout = Vcc − T XRc = 12 −
X 12k
2
2
Vout = 3
...
7
8k + 225k
×100
IT = 1
...
Rc
2
1 1
...
66v
If the results obtained are compared, we find that the results obtained improve with each
refinement, but the improvement is not significant
...
41mA
I
0
...
5µA
β
100
∴ VB = − I B
...
5µ )(25k )
VB = −0
...
23
Design a series voltage regulator to supply 1A to a load at a constant voltage of 9V
...
The minimum zener current is 12mA
...
6V and β=50
...
6
Vz = 9
...
6 = 5
...
4
∴ R=
=
I
32mA
R = 168
...
Q
...
(4)
Ans:
f ( A, B, C ) = A + BC
f ( A, B, C , ) = A( B + B )(C + C ) + BC ( A + A)
32
AE05
BASIC ELECTRONICS
= AB + A B )(C + C ) + BCA + A BC )
= ABC + ABC + ABC + ABC + BCA + ABC
Q
...
Calculate the diode resistance at the point Q
...
R=
Q
...
5mA peak
...
7V
...
25 A
Rc 16
VcE = Vcc = 20v
Now dc – load line is drawn joining points (20v, 0) and (0, 1
...
7
I B = cc
=
= 19
...
3m = 0
...
579 × 16 = 10
...
I b peak = 30 × 8
...
255 A
Pin( dc ) = Vcc I cQ = 20 × 0
...
58w
...
255 × 16
Pout (ac) =
2
2
= 0
...
Power delivered to the transistor,
2
P tr ( dc) = Vcc I cQ − I cQ Rc
= 20(0
...
579)2
...
216w
Power lost in transistor = P tr ( dc ) − Pout ( ac)
= 6
...
5202
= 5
...
5202
× 100
6
...
368 %
...
736 × 0
...
216w
...
27
Find the period of the output pulse in the circuit shown below:
34
(4)
AE05
BASIC ELECTRONICS
Ans:
TIMERS
The pulse width = 1
...
1× 2 K × 0
...
1mSec
...
28
Analyze half-wave and full-wave rectifier circuits (without filter) to deduce the values of
rectification efficiency assuming ideal diodes
...
Pac
2
I
Now, Pdc =
RL = max
...
35
AE05
BASIC ELECTRONICS
2
2
2
= I rms RF + I rms RL = I rms ( RF + RL )
2
I max
(R F + R L )
=
4
2
I max RL 2
Pdc
4
RL
π
= 2
= 2
η=
Pac I max (RF + RL ) / 4 π RF + RL
0
...
e
...
6 % if RF is neglected
...
RL = I max RL = 2 I max RL
π
π
2
I
2
Pac = I rms
...
2 %
Q
...
812
1 + RF R
L
if RF is neglected
...
At 300K, find the electric field intensity in the bar and voltage across the bar
when a steady state current of 1µA is measured
...
3 x 103 Ω−m
(7)
Ans:
Length=4mm
A=60 x 100 (µm) 2
Current I =1µA
Resistivity r = 2
...
3 x103
= 383
...
33 x 103 x 4mm =1
...
30
The resistivity of doped silicon material is 9 x 10-3ohm-m
...
6 x 10-4m3 columb-1
...
6 x 10-19 coulomb)
(7)
Ans:
RH = 3
...
6x10-4 = 400 cm2/V-s
Density of charge carriers = σµ
36
AE05
BASIC ELECTRONICS
= (1/9x10-3) 400 = 44
...
31
A single tuned amplifier with capacitive coupling consists tuned circuit having R=10,
L=20mH and C=0
...
Determine the (i) Resonant frequency (ii) Q-factor of the tank circuit
(7)
(iii) Bandwidth of the amplifier
...
05x10-6) = 5032 Hz
(ii) Q-factor of the tank circuit: Q = XL / R = 2 π frL / R
...
23
Q = 63
...
32
(iii) Band width of the amplifier: As Q = fr / BW
∴ 6
...
20Hz
Q
...
Then
VO = - [(2R) V1/R + (2R) V2/R]
= - [2(V1 + V2)]
= - [2(2 -1) ] = -2 V
Q
...
15µA
...
12V
...
15 x 10-6A
...
12V, VT = 0
...
e
...
15 x 10-6 (e (0
...
026)) - 1)
= 1
...
34
In a transistor amplifier, change of 0
...
2 mA
...
025/15 x 10-6 =
1
...
2mA/15 x 10-6 = 80
iii) AC load = Rc || RL = 6k x 12k/(6k+12k) = 4k
iv) Voltage gain: output voltage = 1
...
8V = Vo
input voltage = 0
...
8 / 0
...
35
What is a load line and how is it used in the calculation of current and voltage gains for a
single stage amplifier?
(7)
Ans:
In a transistor, the collector current IC depends on base current IB
...
This line for a fixed load
is called as dc load line
...
13a
...
Fig
...
Therefore
iB = IBQ + Ib = 40 + 20 sinωt µA
From the figure, we see that variation in IB causes both IC and VCE to vary sinusoidally about
their quiescent levels
...
36 The transconductance of a FET used in an amplifier circuit is 4000 micro-siemens
...
Calculate the voltage gain of the
amplifier circuit
...
37 An output waveform displayed on an oscilloscope provided the following measured values
i) VCE min=1
...
Ans:
D2 = (|B2| / |B1|) x 100%
i) B2 = (Imax + I min – 2IcQ) / 4
= (VCE max + VCE min – 2VCEQ) / 4
= (22+1
...
2 / 4 = 0
...
2) / 2 = 10
...
8 / 10
...
69%
ii) B2 = (2+18-20) / 4 = 0
B1 = (18-2) / 2 = 8
D2 = 2
...
38 A sample of pure silicon has electrical resistivity of 3000 m
...
1x1016/m3
...
The electronic charge is equal to 1
...
(6)
Ans:
39
AE05
BASIC ELECTRONICS
For pure Silicon, ni = n = p = 1
...
1x1016 (µp + 3µp) 1
...
04 x 10-3 µp
= (3000 Ωm)-1
Thus µpx7
...
e
...
047 m2 V-1 S-1 and µn = 3 µp =0
...
39 Explain ‘Zener breakdown’
...
The supply voltage V = 150V
...
What is Imax?
(8)
Ans:
Zener break down takes place in diodes having heavily doped p and n regions with essentially
narrow depletion region
...
This breakdown is reversible
...
e 2
...
5 KΩ, Is = 40 mA
...
40 Draw a figure to show the output V-I characteristic curves of a BJT in CE configuration
...
Explain how, using these
characteristics, one can determine the value of hfe or βF
...
18b
Fig
...
shows the characteristics of BJT in CE configuration
...
Choose constant IB lines suitably, which cut
the constant Vce line at X and Y
...
From fig hfe = (IC2-IC1) / (IB4-IB2)
= (6-2) mA / (60-20) µΑ =100
...
41
Draw a small signal h-parameter equivalent circuit for the CE amplifier shown
in fig below
...
Compute the value of voltage gain, if RC =
RL = 800 , R1 = 1
...
(9)
Ans:
Fig
...
19
Voltage gain of amplifier is Av = VL / Vi
Rb = R1R2 / (R1 + R2) in the equivalent circuit
...
h ie
Vo = (− h ge ⋅ i b )(R c R L /[ R c + R L + h oe R L R c ])
∴ A v = V0 / Vi = −(h fe R cR L ) /[h ie (R c R L + h oe R L R c )]
Rb = (R1R2) / (R1+R2) = (1
...
5+3)103 = 1k
Av = (-90x800x800) / [150(800+800+100x10-6x800x800) = -230
...
42 The circuit of a common source FET amplifier is shown in the figure below
...
Find also the input resistance Rin for the amplifier
...
(8)
42
AE05
BASIC ELECTRONICS
Ans:
Using voltage source model of the FET, the equivalent circuit is as in Fig
...
20 a
Vo = (-RDµVgs) / (RD+rds)
Vgs = Vi
Av = Vo / Vi = (-µRD) / (RD+rds)
id = (µVgs) / (rds+RD)
Vgs = iiRG
Av = (-60x3x103) / (3x103+30x103) = -5
...
e Ai = µRG / (RD+rds) = [60x500x103] / [30x103+3x103] = 909
It is obvious that Rin = RG = 500k
Q
...
The capacitance
values of the two capacitors C1 and C2 of the resonant circuit of a colpitt oscillator are C1 =
20pF and C2 = 70pF
...
What is the operating frequency of
(5)
oscillator?
Ans:
Consider a basic inverting amplifier with an open loop gain ‘A’
...
The basic amplifier produces a phase shift of 180o
between input and output
...
This ensures
positive feedback
...
The total phase shift around the loop, as the signal proceeds from input through the
amplifier, feedback network and back to input again, is precisely 0o or 360o
...
The magnitude of the product of the open loop gain of the amplifier, ‘A’ and the feedback
factor ‘ß’ is unity, i
...
|Aß| = 1
...
56pF
...
56 x 10-9} = 272
...
44
Suggest modification in the given circuit of Opamp to make it (i) inverting (ii)
(7)
non inverting
...
For an inverting amplifier, the input is to be applied
to the inverting terminal
...
Fig 24 a (i)
Fig 24 a (ii)
Fig 24 a (ii) shows a non-inverting amplifier
...
Therefore point P1 is connected to the source
...
45
In the circuit of Q44, if input offset voltage is 0,
(i) Find the output voltage Vo due to input bias current, when IB=100nA (3)
(ii) How can, the effect of bias current be eliminated so that output voltage is zero?
(4)
Ans:
(i) When the voltage gain of op-amp is very large, no current flows into the op-amp
...
Let Rp=R1 || R2
Then voltage from inverting terminal to ground is
VI = -IB2 x Rp
Let R1 = Rp = (R1 x R2) / (R1 + R2) = 90
...
9k to make the output voltage as zero
...
r
...
ground
and VN : Voltage at the non-inverting terminal w
...
t
...
46 A differential amplifier has inputs Vs1=10mV, Vs2 = 9mV
...
Find the percentage error in the output voltage and error voltage
...
(14)
Ans:
In an ideal differential amplifier output Vo is given by
Vo = Ad (V1-V2)
Ad = gain of differential amplifier
But in practical differential amplifiers, the output depends on difference signal Vd as well as on
common mode signal VC
...
Therefore from 1 and 2
V1 = Vc + 0
...
5Vd
Vo = AdVd + AcVc
Where Ad = 0
...
5(A1+A2)
the voltage gain of difference signal is Ad and voltage gain of common mode signal is Ac
...
The equation for output voltage can be written as
Vo = AdVd (1+ (Ad/Ac) (Vc/Vd))
Vo = AdVd (1+ (1 / ρ) (Vc/Vd))
Vs1=10mV = V1 , Vs2=9mV = V2
Ad=60dB,
CMRR=80dB
Vd = V1-V2=10mV-9mV=1mV
Ad = 60dB = 20log10 Ad, since Ad =1000
Vc = (V1+V2)/2 = (10+9) / 2 = 9
...
1
Vo = AdVd + AcVc = 1000 x 10-3 + 0
...
5 x 10-6
= 1
...
47
Prove the following postulate of Boolean algebra using truth tables
x + y + z = (x + y)
...
48
y
0
0
1
1
0
0
1
1
z (x+y) (x+z) (x+y)(x+z) x+y+z
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
Simplify the following Boolean function using K-map:
_
_
_
f(a,b,c) = a c + a b + a b c + b c Give the logic implementation of the simplified function in
SOP form using suitable gates
...
Assuming the
availability of complements, the logic implementation is as in Fig
...
Fig
...
1
A triangular wave shown in fig(1) is applied to the circuit in fig(2)
...
Sketch the output waveform
...
Thus up to +12v of the applied signal there would be output
47
AE05
BASIC ELECTRONICS
voltage across the output terminals and the triangular signal will be clipped off above 12v
level
...
Q
...
Obtain an expression for the same
...
This type of capacitance is called the diffusion
capacitance, CD
...
If τ is the mean life-time of charge carriers, then a flow of charge Q yields a diode current I
given as
Q
I=
or Q = τ I
τ
We know that
So,
So diffusion capacitance
For a forward bias,
Thus the diffusion capacitance is directly proportional to the forward current through the
diode
...
CT: Transition capacitance
...
Hence in a reverse
biased diode CD is neglected and only CT is considered
...
3
Draw the circuit of h-parameter equivalent of a CE amplifier with un by-passed emitter
resistor
...
Ans:
Ib
Ie
VS
CE – amplifier AC – Equivalent Circuit with an un-bypassed Emitter Resistor (RE)
...
Input Impedance:
Zin (base) or Zb = hie
With an un-bypassed emitter register RE in the circuit,
Vin = hie I b + I e RE = hie I b + RE (I b + I c )
= I b hie + I b RE + I c RE
...
∴Vin = I b (hie + RE ) + h fe I b
...
hie
− h fe I b ( Rc || RL ) − h fe
Av =
=
( RG || RL )
I b hie
hie
The minus sign indicates that output voltage Vout is 1800 out of phase with input voltage Vin
...
4
BASIC ELECTRONICS
What is a ‘multistage amplifier’? Give the requirements to be fulfilled for an ideal coupling
network
...
Hence, several amplifier stages are usually employed to achieve
greater voltage or current amplification or both
...
In a multistage amplifier, the output of first-stage is combined to next stage through a
coupling device
...
1
...
2
...
3
...
4
...
Q
...
Explain its
operation
...
In enhancement mosfet drain (ID) current flows only
when VGS exceeds gate-to-source threshold voltage
...
As the gate voltage increased, more and more electrons accumulate under
the gate, these accumulated electrons i
...
, minority charge carriers make N-type channel
stretching from drain to source
...
The strength of the drain current depends upon the
channel resistance which, in turn, depends on the number of charge carriers attracted to the
positive gate
...
Q
...
(6)
Ans:
When the feedback voltage (or current) is applied to weaken the input signal, it is called
negative feedback
β
For an open-loop amplifier,
V
Voltage again, A = out
Vin
Let a fraction (say β) of the output voltage Vout, be supplied back to the input and A be the
open-loop gain
...
Vout
∴ Vout = A
...
Vout )
Vout
A
=
VS 1 + β A
V
A
A f = out =
VS
1 + βA
Q
...
the input impedance increases with negative feedback
...
the output impedance decreases due to negative feedback
...
Vin
= S
Z in
Or I in Z in = VS − β
...
Vin
VS = I in Z in + β
...
Vin
= I in Z in + β AI in
...
VS
= Z in + ( β A) Z in = Z in (1 + β A)
I in
∴ Z inf = Z in (1 + β A)
The effect of negative feedback on the output impedance of an amplifier is explained below
...
Z out − A
...
Z out − A( β Vout )
Or Vout (1 + β A) = I out Z out
V
Z
Or out = out
I out 1 + β A
Z
Z outf = out
1 + βA
Thus, series voltage negative feedback reduces the output impedance of an amplifier by a
factor (1 + βA)
...
8
`
Q
...
Ans:
Advantages:
1
...
2
...
3
...
4
...
Explain how the timer IC 555 can be operated as an astable multivibrator, using timing
diagrams
...
01µF
The Timer -555 As An Astable Multivibrator
An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave
generating circuit
...
Internal Circuitary With External Connections
54
AE05
BASIC ELECTRONICS
When Q is low, or output Vout is high, the discharging transistor is cut-off and capacitor C
begins charging towards Vcc through resistances RA and RB
...
Eventually, the threshold voltage exceeds + 2 Vcc ,
3
comparator 1 has a high output and triggers the flip-flop so that its Q is high and the timer
output is low
...
When it drops below Vcc
...
Q
...
(10)
Ans:
The continuity equation states a condition of a dynamic equilibrium for the concentration of
mobile carriers in any elementary volume of the semiconductor
...
The differential equation governing this functional relationship, called the
continuity equation, is based upon the fact that charge can be neither created nor destroyed
...
If τn is the mean lifetime of holes then P/τn equals the
holes per second lost by recombination per unit volume
...
adx
------(1)
τn
If ‘g’ is the thermal rate of generation of electron-hole pairs per unit volume, the number of
coulombs per second increases within the volume and increase within the
volume = e
...
dx
...
If the current entering
the volume at x is In and leaving at x + dx is I n + dI n
Decrease within the volume = dIn
...
dp
Increase within the volume = e
...
dx
...
dp
Under these conditions I n = 0 and
=0
...
τn
Combining equations (5), (6) and (7) we have the equation of conservation of charge, called
the continuity equation,
dp
p − po
d2p
d (PE )
=−
+ Dn 2 − µ n
dt
dx
τn
dx
Q
...
(8)
Ans:
Important characteristics:
1
...
Low voltage gain
3
...
56
AE05
BASIC ELECTRONICS
− h fe
× (Z in to Q2 )
hie
− h fe hie
=
≈ −1
...
Voltage gain of
stage-2,
h fb × (R3 || Rh )
Av 2 =
hib
− h fe × (R3 || Rh )
∴ Over-all voltage gain, Av =
...
12
Write a neat sketch to shown the construction of a depletion-enhancement MOSFET and
explain its operation in both the modes
...
When gate is
positive with respect to the source it operates in the enhancement
...
When the gate is made negative w
...
t the substrate, the gate repels some of the negative
charge carriers out-of the N-channel
...
The more negative
the gate, the less the drain current
...
13
Draw the circuit of Hartley oscillator and derive an expression for its frequency of
oscillation
...
hie ( Z1 + Z 2 + Z 3 ) + Z1 Z 2 (1 + h fe ) + Z 2 Z 3 = 0
--------(1)
Here Z1 = jwL1 + jwM , Z2 = jwL2 + jwM
and
Z3 =
1
=− j
wc
jwc
Substituting these values in equation (1), we get
=0
j ( jwL + jwM )( jwL + jwM )(1 + h ) + ( jwL + jwM ) − j
hie ( jwL1 + jwM ) + ( jwL2 + jwM ) −
1
2
fe
2
+
wc
wc
1
1
jwhie L1 + L2 + 2 M − 2 − w 2 (L2 + M )(L1 + M )(1 + h fe ) − 2 = 0
w c
w c
Equating imaginary parts of above equation to zero we get,
1
While L1 + L2 + 2M − 2 = 0
w c
Or L1 + L2 + 2 M −
w 2c =
1
L1 + L2 + 2M
Or f =
Q
...
(8)
58
AE05
BASIC ELECTRONICS
Ans:
Current Mirror Circuit
In the design of op-amps, current strategies are used that are not practical in discrete
amplifiers
...
One such approach is the use of the current mirrors to bias differential
pairs
...
I
I
I B = E ≈ E and I C ≈ I E
...
15
β
β
Vcc − VBE
RX
Explain, using neat circuit diagram and waveforms, the application of timer IC555 as
(9)
monostable multivibrator
...
e
...
As the
discharge transistor is cut-off, the capacitor C begins charging towards + Vcc through
resistance RA with a time constant equal to RAC
...
The transistor goes to saturation, thereby discharging the capacitor C and output of
the timer goes low
...
16
Write the circuit diagram of a square wave generator using an opamp and explain its
operation
...
The heart of the oscillator is an inverting op-amp
comparator
...
A fraction of
the output is feedback to the non-inverting input terminal
...
R3
Vin = Vc − β Vout
where β =
R2 + R3
When Vin is positive, Vout = −Vz1 and
When Vin is negative, Vout = V z2
...
17
Distinguish between synchronous and asynchronous counters
...
(12)
Ans:
Difference between synchronous and asynchronous counter :
1
...
But in the case of
asynchronous counter the output of first flip-flop is given as the clock input of the
next flip-flop
...
In synchronous counter the output occurs after nth clock pulse if number of bits are
N
...
Design of 3 bit UP DOWN counter:For M = 0, it acts as an UP counter and for M = 1 as a DOWN counter
...
The input of the flip-flops are determined in a manner similar to the
following table
...
Q0 M
J 2 = K 2 = M Q1Q0 + M Q1 Q0
= M Q1Q0 + M Q1 Q0
= M Q1Q0
...
18
Describe how conductivity and carrier mobility of a sample of semiconductor can be
determined by subjecting it to Hall-effect
...
Thus phenomenon is called the
Hall-Effect
...
In the equilibrium state the electric field intensity E due to Hall-effect must exert a force on
the charge carriers which just balances the magnetic force
...
e
...
V
Now electric field, E = H or
d
VH = E
...
v
...
The current density is given as
I
I
J= =
= ρ
...
d
I
∴ v=
ρw
...
I
Now, VH = B
...
ρwd
BI
VH =
ρw
Hall-coefficient RH is defined by,
1 V
...
I
and conductivity, σ = ρµ
and mobility, µ = σ
...
19
Draw the symbol and characteristics of an N-channel JFET and mark linear region,
saturation region and breakdown region
...
20
Using necessary circuits and waveforms illustrate and explain positive and negative
(12)
clamping of voltages
...
A
positive clamping circuit is shown in above figure
...
Input waveform
Negative Clamper
Output waveform
In negative clamping circuit, with the positive input, the diode D is forward biased and
capacitor C charged with the polarity shown
...
When the input goes negative, the diode is reverse biased and acts as an opencircuit and thus has no effect on the capacitor voltage
...
Thus during negative
input, the output voltage being the sum of the input voltage and the capacitor voltage is
65
AE05
BASIC ELECTRONICS
equal to –V – (V – Vo) or – (2V – Vo)
...
Q
...
Explain its behaviour at low, mid and high
frequencies by drawing separate equivalent circuit for each frequency region
...
Mid Frequency Range
Current, I =
h fe I b Rc
Rc + hie
So current gain, Ain =
Vout = hie I =
2
...
Rc
hie Rc jwc d + hie + Rc
Vin = hie I b
h fe Rc
V
Ain = out =
Vin hie Rc jwcd + hie + Rc
Vin = hie I b
hie h fe I b Rc /( Rc + hie )
V
Avin = out =
Vin
hie I b
h fe Rc
Avin =
Rc + hie
Low frequency range:
Thevenin’s Equivalent circuit for low frequency range
I=
h fe I b Rc
hie + Rc + j / wC c
So current gain, Ail =
h fe Rc
I
=
I b hie + Rc − j / wC c
67
AE05
BASIC ELECTRONICS
Output-voltage, Vout = hie I =
h fe hie I b Rc
hie + Rc − j / wC c
Input-voltage, Vin = hie I b
V
So voltage gain Avl = out
Vin
hie h fe I b Rc
hie + Rc − j / wC c
hie I b
h fe Rc
Avl =
hie + Rc − j / wC c
=
Q
...
(8)
Ans:
Stability:- The variations in temperature, supply voltages, ageing of components or
variations in transistor parameters with replacement are some factors that affect the gain of
an amplifier and cause it to change
A
A 1
Af =
=
≈
1 + βA βA β
The gain is thus independent of internal gain of the amplifier and depends on the passive
elements such as resistors
...
equation w
...
t
...
β
=
We have
dA
(1 + β A) 2
1
=
or
(1 + βA) 2
dA
dA f =
(1 + β A) 2
dA f dA (1 + β A)
=
×
Or
Af
A (1 + β A) 2
1
=
...
Thus negative feedback improves
the gain stability of the amplifier
...
Now when feedback is applied, output as well distortion is feedback to the input
...
A part βDf of this distortion
is feedback to the input
...
Net distortion, D f = D − βAD f
D
1 + βA
Thus the distortion is reduced by a factor (1 + βA)
...
Z out + A Vin
Df =
= I out Z out − A
...
= I out Z out − A
...
Vout
...
Q
...
What is its distinct
advantage over other tuned oscillators?
(7)
Ans:
69
AE05
BASIC ELECTRONICS
As the circulating tank current flows through C1, C2, C3 in series, the equivalent
capacitance is
1
C1C2C3
C=
=
1 + 1 + 1
C1C2 + C2C3 + C3C1
C
C
C
1
2
3
1 1
1
1
f =
LC1 + LC 2 + LC3
2π
In a clapp oscillator C3 is much smaller than C1 and C2
...
Q
...
e
...
c R
dt
dV
Vout = −CR c
dt
70
(9)
AE05
BASIC ELECTRONICS
(ii)
i (t ) =
Integrator:
V (t )
R
1
i (t )
...
dt
c R
1
Vout (t ) = −
V (t )
...
Therefore, Va/Ra + Vb/Rb + Vc/Rc = - (Vo/RF)
Vo = - [(RF/Ra) Va + (RF/Rb)Vb + (RF/Rc)Vc]
If Ra = R b= Rc = R then Vo = (-RF/R) [Va+Vb+Vc]
(v)
i
...
, output voltage is equal to the negative sum of all the input times the gain of the circuit
RF/R
...
25
Explain the operation of a foldback current-limiting circuit connected to a series voltage
regulator, by drawing a neat circuit diagram
...
The fold-back current limiting
circuit is the solution to this problem
...
R7
VB3 =
(I L R5 + Vout ) = K (I L R5 + Vout )
--------(1)
R6 + R7
R7
Where K =
R6 + R7
Vout + VBE3 = VB3
VBE3 = VB3 − Vout = K (I L R5 + Vout ) − Vout
VBE3 = KI L R5 + ( K − 1)Vout
---------(2)
Now if load resistance decreases, may be due to any reason, load current IL will increase
causing voltage drop ILR5 to increase
...
This makes transistor Q3 – ON in a stronger way
...
This results in reduction of the conduction level of transistor Q1
...
72
AE05
Q
...
Draw the logic diagram using gates of your choice to
realize the minimized function
...
27
Define mobility in a semiconductor
...
Mobility is the ratio of drift velocity and
electric field
...
Yes, the mobility depends on the doping levels
...
28
What is the quantity of mobility for electrons and for holes in a silicon semiconductor?
(2)
Ans:
The typical value of mobility of electrons in a silicon semiconductor is 0
...
046m2/V-s
...
29
BASIC ELECTRONICS
A semiconductor has donor and acceptor concentrations of ND and NA, respectively
...
30
We know that np = ni 2
For n type semiconductors: n ≈ ND
p = (ni) 2 / ND
For p type semiconductors: p ≈ NA
∴ n = (ni) 2 / NA
What do you understand by ‘cut-in’ voltage of a diode?
(4)
Ans:
The cut in voltage is the voltage across the diode below which current is very small(less than
1% of rated current) in the forward biased condition only
...
3(i)
The above figure shows the V-I characteristics of diode in the forward biased region
...
5V
...
Q
...
Indicate the knee on the curve and
explain its significance
...
From the characteristics shown in fig 3 (ii), we see that for currents greater than the
knee current ( Izk ), the V-I characteristic is almost a straight line
...
As the current through the zener deviates from Izt, voltage
across changes only slightly
...
74
AE05
BASIC ELECTRONICS
Fig
...
Lower the value of rz, more constant is the zener voltage as the current
varies
...
When the magnitude of ‘I’ decreases below Izk, the zener ceases
to operate as a voltage regulator
...
Q
...
Ans:
(i) Wide band
(ii) Direct coupled
(iii) Tuned amplifier
(i) Wide band amplifier: The gain remains constant over wide frequency range, but falls off
at low and high frequencies as shown in the above Fig (i)
...
(ii) Direct coupled amplifier: It is also called as dc amplifier
...
(iii)Tuned amplifier: The gain peaks around certain frequency say ω0 and falls off drastically
on both sides of this frequency
...
Q
...
Represent its 3dB frequency
graphically
...
) / ((s+ωp1) (s+ωp2)……
...
represent poles
...
represent zeros
...
Also one of the poles will
have much higher frequency than all the other poles
...
In this case, low frequency response of amplifier is dominated by the pole at
s = -ωp1 and lower 3dB frequency is approximately = ωp1
i
...
,ωL ≈ ωp1
This is called as dominant pole approximation
...
e
...
If dominant low frequency pole does not exist, then
ωL = √ ( ωp1²+ωp2²-2ωz1²-ωz2²)
If FL(s) = (s (s+10)) / ((s+100) (s+25))
ωp1=100rad/sec is 2 octaves higher than 2nd pole and a decade higher than 0
...
34
(100 2 + 25 2 − 2 × 10 2 = 102 rad/sec
Draw the characteristics of an n channel JFET
...
(8)
Ans:
The figure below shows a family of ID v/s VDS characteristics of an n channel JFET for various
values of VGS
...
This is true for a given value of VGS
...
76
AE05
Q
...
Hence
they are called static characteristics
...
36
Write the equation, which represents the boundary between the triode region
region?
and pinch off
(4)
Ans:
The JFET operates in the triode region for
Vds > Vgs - Vp
Where Vds = drain to source voltage
Vgs = gate to source voltage
Vp = pinch off voltage
Q
...
(2)
Ans:
Q
...
If a voltage VDS
is applied between drain and source, a current iD flows even for VGS=0
...
Applying negative VGS causes electrons to be repelled from the channel
resulting in lower conductivity and therefore is called depletion mode operation
...
FET used as an amplifier should be operated in saturation region
...
For a depletion type n channel MOSFET, threshold voltage Vt is negative
...
For it to operate in saturation, the drain voltage must be greater than the gate voltage by
at least | Vt | volts
...
In saturation region the MOSFET
provides a drain current whose value is independent of drain voltage VDS and is determined by
gate voltage only
...
As VGS decreases towards threshold, the drain current decreases
...
Q
...
This
phenomenon is known as Hall Effect
...
Consider an N type
semiconductor carrying current (I) placed in a transverse magnetic field (B) in the direction as
shown in the Fig
...
In order to obtain equilibrium state,
F (electric) + F (magnetic) =0
n
...
E + B
...
e E = - BJ/n
...
The Hall co-efficient RH is given by RH = 1/n
...
J
...
t
where t = thickness of the semiconductor
...
q
...
Conductivity of an extrinsic semiconductor is given by
σ = n
...
µn
Where µn = electron mobility &
Or σ = p
...
µp
µp = Hole mobility
Therefore µn = σ/nq =σRH
Q
...
Why common emitter
configuration is mostly used? Give its typical uses
...
1
...
Common emitter configuration
3
...
Collector current is given by IC = ß IB
...
The value of ß is ordinarily high and ranges from 10 to
500
...
(iii) Moderate output to input impedance ratio: In the CE configuration the ratio of output
impedance to input impedance is small
...
CE configuration is used for small signal and power
amplifier applications
...
41
What is transistor biasing? What are the basic conditions which are to be necessarily
fulfilled for achieving faithful amplification of input signal in transistor amplifiers? (7)
Ans:
Fixing the d
...
The quiescent point should lie in the central area of an active, linear
region of the transistor
...
The basic conditions required for achieving faithful amplification of input signal in transistor
amplifiers are:
1) Proper zero signal collector current: The value of zero signal current should be at least
equal to the maximum collector current when the signal is present
...
5V for germanium and 0
...
Q
...
Explain with the help of circuit diagram how an FET is used as a voltage amplifier and as
voltage dependent resistor (VDR)
...
FET is a voltage controlled current source
...
FET has a negative temperature co-efficient at high current levels, which
prevents FET from thermal break down
...
Pinch off Voltage:
It is the voltage at which the drain current reaches the maximum value and beyond which
drain current becomes constant
...
i
...
,
gm = ∆ID / ∆VGS VDS constant
...
i
...
,
µ = ∆VDS / ∆ VGS at constant ID
...
DC or static drain resistance is the ratio of VDS to ID
...
e RDS = VDS / ID
A
...
rd = ∆VDS /∆ID
FET as an amplifier is shown in Fig
...
Fig:9 (i)
81
AE05
BASIC ELECTRONICS
An enhancement n-channel MOSFET is biased with a battery VGS
...
Thus the total
instantaneous gate voltage is
vGS = VGS + vgs
The operating point can be got by intersection of load line and ID versus VDS curve
corresponding to instantaneous values of vGS
...
The output signal is an
amplified replica of the input signal
...
FET as voltage dependent resistor:
FIG: 9 (ii)
Figure 9 (ii) shows the output characteristics of an FET
...
If we consider the slope of the curve for low values of VDS, we see that the slope varies with
variations in VGS
...
Hence for a given VDS = V1, the resistance depends on gate voltage and thus it is seen that FET
acts as voltage dependent resistor
...
43
What is a tuned amplifier? What is the fundamental difference between audio
amplifiers and tuned amplifiers? How is bandwidth related to resonant frequency (fr)
and the quality factor (Q)
...
Audio amplifiers provide the constant gain over a wide band of frequencies
...
This is shown in
Fig
...
BWA is the bandwidth of response of a typical audio amplifier, while BWT is the
bandwidth of tuned amplifier and fr is called the center frequency of tuned amplifier
...
10(a)
The quality factor Q of a tuned amplifier is equal to the ratio of center frequency (fr) to
bandwidth (BWT) i
...
For a parallel resonance circuit is given by
fr = 1/ (2π√LC) and Q = X L / R where XL is the reactance of the inductor having resistance R
...
44
Discuss the terminal properties of an ideal operational amplifier
...
11(a) shows the schematic of an ideal op-amp
...
i) The input impedance of an ideal op-amp is infinite
...
ii)The gain of an ideal op-amp is infinite ( ∞ ), hence the differential input Vd =V1-V2 is zero
for the finite output voltage V0
...
11(a)
iii) The output voltage V0 is independent of the current drawn from the output terminal
...
This results in the following Characteristic of an ideal op-amp
...
It is the differential open loop gain
...
c) Zero output impedance: It is denoted as Ro and ensures that the output voltage of the opamp remains the same, irrespective of the load
...
e) Infinite bandwidth: This ensures that the gain of the op-amp will be constant over the
frequency range from d
...
83
AE05
BASIC ELECTRONICS
f)
Infinite CMRR: This ensures zero common mode gain for an ideal op-amp
...
g) Infinite slew rate: This ensures that the changes in the o/p voltage occur simultaneously
with the changes in the input voltage
...
45
What is an ideal diode? Sketch the characteristics of an ideal diode
...
Conducts with Rf = 0, when forward biased
b
...
An ideal diode behaves like a switch which is closed in the
forward direction and open in the reverse direction
...
12a
...
Fig
...
46
Describe the construction and operation of JFET
...
(7)
Ans:
The basic structure of an n-channel JFET is as shown in Fig
...
The drain and source
terminals are made by ohmic contacts at the ends of n-type semiconductor bar
...
The n-type region between two p+ gates is
called the channel through which majority carriers flow between the source and the drain
...
In normal operating mode, this pn junction is
maintained in reverse biased state
...
This reverse biases the junction, and hence the depletion region exists
...
84
AE05
BASIC ELECTRONICS
Fig
...
Since gate region is heavily
doped than the channel region, depletion region penetrates more deeply into the channel
...
Therefore, as reverse bias increases, the effective width of the channel decreases
...
This voltage is called pinch off voltage (Vp)
...
In a MOSFET metal gate electrode is separated by an oxide layer from the semiconductor
channel
...
14a(ii) shows a Common Source (CS) configuration
...
VGG provides the necessary reverse bias between gate and source of JFET
...
Fig
...
14a(iii)
Q
...
Ans:
The collector tuned circuit is shown in Fig
...
16a(i)
Fig
...
16a(iii)
86
(7)
AE05
BASIC ELECTRONICS
The equivalent circuit of the amplifier is shown in Fig
...
Voltage Gain AV= Vo/Vi
From Fig
...
Z (at resonance) = Rt
Fig
...
16a(ii)
...
16a(ii) neglecting Cs)
Vo = -gmVi( rbeZ / (rbb+rbe))
AV = Vo/Vi = -gmVi(rbeZ/(rbb+rbe))
= -gm(rbe/(rbb+rbe)) x (Rt/(1+2jQeffδ))
At resonance, voltage gain is
AV = -gm(rbe/(rbb+rbe)) x Rt
Q
...
(7)
Ans:
A tuned amplifier is required to be highly selective
...
Q
...
(4)
Ans:
A pure semiconductor which is not doped is said to be intrinsic semiconductor
...
When pure semiconductors are mixed (doped) using trivalent or
pentavalent elements, we get extrinsic ones, which are p type in the former case and n type in
the latter
...
This happens by participation of electrons of doping element with those of
semiconductor in forming bonds
...
Q
...
87
(6)
AE05
BASIC ELECTRONICS
Ans:
Classification according to operation mode:
The duration of device conduction with respect to input signal cycle period determines the
class of operation
...
Class B: Device conducts only during one half cycle of input
...
Class C: Device conducts for less than half cycle of input
...
These different operations are achieved by appropriate biasing of the device by setting up the
desired quiescent current and voltage (or Q-point)
...
20 b
...
Fig
...
51 Draw a block diagram of a single loop feedback amplifier, and explain the function of each
block
...
(9)
88
AE05
BASIC ELECTRONICS
Ans:
The block diagram of a single loop feedback amplifier is as shown in Fig
...
Comparator or mixer: This block combines the source signal with the feedback signal
...
Basic amplifier: The ratio of output signal to the input signal of a basic amplifier is
represented by ‘A’ and depends on the type of amplifier
...
When voltage
has to be sampled, feedback network is connected in parallel to the output terminals and in
series when current is to be sampled
...
21a
Feedback network: This is a passive two port network providing a known fraction of the
input to the mixer at input
...
Sensitivity of transfer characteristics
...
Non linear distortion
...
Noise
...
Frequency distortion
...
Bandwidth
...
Input and output impedances of the amplifier
...
I/P impedance
O/P impedance
Voltage
Series
Increases
Decreases
Current
Series
Increases
Increases
Q
...
i) Nyquist criterion
...
iii) Schmitt trigger
...
Current
Shunt
Decreases
Increases
Voltage
Shunt
Decreases
Decreases
(2x7)
Ans:
i) Nyquist criterion:
89
AE05
BASIC ELECTRONICS
Fig
...
22(ii) unstable system
The diagrams above shows Nyquist plot for 2 types of systems (stable and unstable)
...
The Nyquist plot intersects the negative real axis at a
frequency ω180
...
If intersection occurs
to the right of point (-1, 0) the amplifier will be stable
...
Nyquist plot is used to determine whether there are any poles on the right half of s-plane for a
feedback amplifier
...
(T(s) is the return ratio)
...
Therefore for a stable feedback amplifier, the Nyquist plot of function AF(s) should not
encircle the point –1+j0
...
In Fig
...
In Fig
...
ii) BIFET and BIMOS circuits:
Ion implantation permits the fabrication of JFETs / MOSFETs and BJTs on the same chip
...
(BIFET=BJT+FET,
BIMOS=BJT+MOSFET)
...
The remaining
stages use BJTs
...
2) Lower input current and hence decreased input offset currents and higher slew rates
...
Input bias current of JFET is the reverse saturation current IGSS of reverse biased gate to
channel junction
...
Since the input current IG is very small, the
offset current due to device mismatch is also much smaller than that with BJT circuits
...
Therefore, the reduction of gm results in increased slew rate
...
To overcome
this limitation, BIFET and BIMOS Op-amps employ three-stage architecture
...
It converts any given waveform into a rectangular
output
...
Input is applied to inverting
terminal (2) and feedback voltage to non-inverting terminal (1)
...
Let vo = Vz+VD
Vz = drop across reverse biased zener
...
And if v2
Fig 22 (iiia) Schmitt Trigger
The voltage at non-inverting terminal is given by
VA+ R2 (V0-VA) = V1 (v2
If v2 is now increased, then vo remains constant and vo = + V0 constant until v2=V1, when v2
exceeds V1, v0 changes
...
This is shown in Fig 22 (iiib)
...
VH=V1-V2
If we now decrease V2, output remains at –Vo until V2 = V2
...
This circuit can be used as a squaring circuit
...
The input and
output waveforms are as shown in the following figure below
...
This circuit converts an irregular shaped
waveform to a square wave or pulse
...
The input voltage Vin triggers the output Vo every time it exceeds certain voltage level
called the upper threshold voltage Vut or becomes smaller than the lower threshold voltage Vlt
as in Fig below
...
The voltage across R1 is
dependent upon the value and polarity of Vo
...
When V0 = -Vsat voltage across
R1 is referred to as the lower threshold voltage Vlt and is given by
Vlt = (R1/ (R1 + R2))* (-Vsat)
...
ROM ≈R1║ R2 is used to minimize the offset problems
...
When input of the
comparator exceeds Vut, its output switches from +Vsat to –Vsat & reverts to its original state
...
(b) Alternative Solution II
Schmitt trigger is used to change a slowly varying input voltage into an output waveform of an
abrupt discontinuous change that occurs at a precise value of the input voltage
...
Schmitt trigger is also called as regenerative comparator
...
The Schmitt trigger circuit is as shown in the
Fig
...
It consists of two similar transistors Q1 and Q2 coupled through RE and resistors R1, R3,
R4 from a voltage divider across VCC to –VBB which places a small positive voltage on the
base of Q2
...
C voltage is applied to the input and suppose this
positive voltage is sufficient to overcome the reverse bias on the base of Q1, The sequence of
events that follows is as follows
...
Q1 comes out of cut off and starts to conduct
...
Its collector voltage drops
...
3
...
4 With reduced IE voltage drop across RE is reduced
...
Consequently, the reverse bias of Q1 is further lowered and it conducts more
heavily
...
As a result, collector voltage of Q1 falls further there by driving Q2 still closer to cut off
...
Q1 conducting at saturation with its collector voltage almost zero
...
Q2 becoming cut off with its collector voltage nearly VCC
...
(i)-Schmitt Trigger
This circuit can be used as a squaring circuit
...
The input and output
waveforms are as shown in the Fig
...
Fig
...
(iii)
94
AE05
BASIC ELECTRONICS
The transfer characteristics i
...
, Vin v/s Vo is shown in Fig
...
Due to the positive feedback the comparator is said to exhibit hysteresis
...
Because of hysteresis, circuit triggers at a higher voltage for increasing than for decreasing
signals
...
Consider two single bit numbers A and B,
One bit comparator
Where C=1 for A>B
E=1 for A=B
D=1 for A
EX - NOR gate is an equality detector
...
c) Condition AConsider a 4-bit comparator
...
a) For A = B, A3 = B3, A2 = B2, A1 = B1, A0 = B0
Therefore E=E3E2E1E0
If A = B then E = 1
If A ≠ B then E = 0
b) For A>B: A3 >B3 (MSB)
Or A3=B3 and A2>B2
Or A3=B3 and A2=B2 and A1>B1
Or A3=B3 and A2=B2 and A1=B1 and A0>B0
This is given by
C = B3A3 +B2E3A2 +B1 E3E2A1 +B0 E3E2E1A0
If A>B then C = 1
d) For A
95
AE05
Q
...
Ans:
(8)
Fig 23 (i)
The circuit of a half wave rectifier is shown in the Fig 23 (i)
...
Then the diode cuts off and the capacitor
discharges through the load resistor R
...
At some instant of time input voltage exceeds the capacitor
voltage and the diode turns on
...
To keep the output voltage from decreasing too much, during
capacitor discharge, value of C is selected so that the time constant RC is much greater than
the discharge interval
...
54 Draw the load voltage waveform for a half wave and full wave rectifier with a
capacitor filter (no explanation required)
...
55
Explain the terms fan in and fan out in logic gates
...
If fan in is exceeded, a logic gate will produce either an undefined
or incorrect output state
...
Fan out: A logic gate may be capable of providing input to several similar gates
...
Q
...
f(w,x,y,z)=Σ(0,1,2,5,7,8,9,10,13,15)
And from the set of prime implicants thus obtained, find out minimal sum of
product expression of the function
...
The prime implicants are
(i) xz
(ii)xy
(iii)xz
The minimum SOP representation is:
f (w,x,y,z) = xz +xy+xz
Q
...
For processing
these signals several methods are employed and all these systems require the inputs in the
digital form
...
Therefore A/D converters are used to convert the signals in analog
form into digital form
...
58
Explain 3 bit parallel comparator ADC with the help of a diagram and give its truth
table
...
In this method, analog voltage Va is
applied to all the comparators
...
The reference voltage to last comparator is V/8
...
It requires 7 comparators
...
When input voltage is above the reference voltage, the output
of that comparator is high (logic 1)
...
For this, the digital output of the encoder should be 2 (Y2=0, Y1=1,
Y0=0) which is interpreted as an analog voltage between (2/8) V and (3/8) V
...
(Y2=Y1=Y0=0)
...
59
W2
0
0
1
1
1
1
1
1
W1
0
1
1
1
1
1
1
1
Y2
0
0
0
0
1
1
1
1
OUTPUTS
Y1
Y0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
What is an oscillator? How does it differ from an amplifier? What are the essential parts of an
oscillator circuit?
(7)
98
AE05
BASIC ELECTRONICS
Ans:
The oscillator is a circuit which generates signals of constant amplitude and frequency
...
The circuits which generate square, pulse or rectangular waveforms are called as
nonlinear oscillators
...
Amplifier is an energy conversion device, which gets energy from the dc source and
converts into an a
...
Conversion is controlled by the input signal
...
It produces output signal, as long
as the dc power is supplied
...
The essential parts of an oscillator circuit are
i) Transistor amplifier
ii) Frequency selective network: The Frequency selective network is connected in positive
feedback loop
...
Q 60
Draw the circuit diagram of Colpitts oscillator and explain its working
...
It uses two capacitors C1 and
C2 placed across a common inductor L and the center of the two capacitors is tapped
...
The transistor circuit is the amplifier
...
The capacitors discharge
through L, which sets up oscillations of frequency
fo = 1 / 2π√LC
Where C = C1 C2 / (C1 + C2)
...
The voltage across C2 is 180o out of phase with the voltage
across C1
...
99
AE05
BASIC ELECTRONICS
Fig 27b
A phase shift of 180o is produced by the transistor and a further phase shift of 1800 is
produced by C1-C2 voltage divider
...
Q
...
Explain its working with neat
and clean waveform i) In case of square wave input ii) In case of sine wave input
...
Integrators can be passive integrator or active integrator
...
Fig 28a(i)
Expression for output voltage:
Since node B is grounded, node A is also at ground potential
...
As the input
current of op- amp is zero, the current through CF is the current through R1
...
It can be observed that the
square wave is made up of steps i
...
, step of ‘A’ between time period of ‘0’ to T/2 while a step
of ‘-A’ between T/2 and T
...
So in the period ‘0’ to ‘T/2’,
the slope is ‘–A’
...
e
...
Therefore output VO (t) = -At 0
i
...
, Vin (t) = Vm Sin ωt, where Vm is the amplitude of sine wave and T is the period of the
waveform
...
VO (t) = - ∫ Vin dt = - ∫Vm sin ωt dt
= - Vm [1/ω (-cos ωt)] = -Vm /ω (-cos ωt)
Thus the output of an integrator is a cosine waveform for a sine wave input
...
Q
...
(6)
Ans:
A summer that gives non inverted sum of the input signals is called as non- inverting summing
amplifier
...
Fig 28b(i)
Q
...
Node ‘A’ is at the same potential
...
e
...
e
...
Then
VO = [(R/2) V1/R + (R/2) V2/R]
= [(V1 + V2)/2]
Thus the magnitude of the output voltage is the average of the input voltages
...
_
_
For the logic expression Z = AB + AB
102
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BASIC ELECTRONICS
(2)
(1)
(4)
i) Obtain the truth table
...
(iii)Circuit realization using AND, OR, NOT gates
...
Q
...
(7)
Ans:
The De Morgan’s theorem can be stated as follows
Theorem 1: The complement of a product of variables is equal to the sum of the complements
of the individual variables
...
B
...
D……
...
Symbolically,
___________
_ _ _
(A + B + C +…
...
B
...
The theorems can be verified by using truth table
...
103
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BASIC ELECTRONICS
____ _ _ _ _
B A+B A+B A B A
...
65
What is a JK flip flop? How does it differ from the SR flip flop in construction and operation?
(7)
Ans:
A JK flip flop is a refinement of the RS flips flop, in that the indeterminate state of the RS
type is well defined in the JK type
...
When J = K =1 JK is flip flop, it complements the outputs
...
Fig 30 (a) shows the logic diagrams of SR flip flop
and JK flip flop
...
Q’ is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q’ was previously 1
...
When
both J & K are 1, the clock pulse is transmitted through one AND gate only, the one whose
input is connected to the output which is presently equal to 1
...
If
Q’ = 1, the output of the lower AND gate becomes a 1 d the flip flop is set
...
Q
...
Such systems are called memory less systems
...
A combinational circuit and
storage elements are interconnected to form the sequential circuit
...
Fig 30 (B)
The sequential circuits receive binary information from its environment via inputs
...
They also
determine the values used to specify the next state of the storage elements
...
67
Show how a full adder may be implemented by using two half adders
...
68
Write short notes on
(i) Voltage Regulator
(ii) Multivibrator
(iii) Shift Register
(2x7)
Ans:
(i) Voltage Regulator:
Voltage regulation may be defined as the ability of the power supply or source to maintain a
constant output voltage in spite of a
...
Mathematically, it is given by the relation,
( (Vmax –Vmin) /Vmax )x 100
Vmax = maximum d
...
output voltage
...
c
...
In general, the voltage regulation may also be expressed as
((VNL –VFL) /VFL) x 100
VFL = full load voltage of the supply
...
It is a known fact, that all the electronic devices and circuits require a constant d
...
c voltage result in erratic operation of the electronic
devices
...
c voltage can be supplied from dry cells or batteries
...
c power supplies
...
c power supply is
made by converting the domestic a
...
c supply
...
c power supply, are given below:
1)Rectifier ,
2)Filter, and
3)Voltage regulator
...
c power supply, the filter is the
second or the intermediate element and the voltage regulator is the last element
...
c
...
When the a
...
c voltage produced
at the filter output
...
c voltage may also occur, when the load resistance
connected at the filter output changes above or below its normal value
...
c
...
c input voltage or the load resistance varies above or
below the normal values
...
zener diode shunt regulator
...
Transistor shunt regulator
...
Transistor series regulator
...
Controlled transistor series regulator
...
Monolithic regulator
...
A multivibrator is a switching circuit which depends, for operation, on
positive feedback
...
...
Each amplifier stage
supplies feedback to the other in such a manner that will drive the transistor of one stage to
saturation and the other to cut off
...
e
...
The output may be taken across any of the stages and may be rectangular or square
wave depending upon the circuit conditions
...
a) Astable multivibrator or free running multivibrator
b) Monostable multivibrator or one-shot multivibrator
c) Bi-stable multivibrator or flip-flop multivibrator
a) Astable multivibrator or free running multivibrator alternates automatically between the
two states and remains in each state for a time dependent upon the circuit constants
...
Because it continuously
produces the square-wave output, it is often referred to as a free running multivibrator
...
The application of input pulse triggers the circuit into its quasi-stable state, in
which it remains for a period determined by circuit constants
...
c) Bi-stable multivibrator or flip-flop multivibrator has two stable states
...
Thus one pulse is used to generate half-cycle of square wave and another pulse is to generate
the next half-cycle of square wave
...
d) Shift registers: A register capable of shifting its stored bits laterally in one or both
directions is called a shift register
...
All the flip flops receive a common clock pulse, which activates the shift from each
stage to the next
...
The output of a given flip flop is connected to the D input of the flip flop at its right
...
Serial input SI is the input to the leftmost flip flop during the shift
...
Fig 18 A 4 bit shift register
Shift registers can be used for converting serial data to parallel data and vice versa
...
Q
...
(7)
Ans:
Wein-bridege oscillator is used in audio frequency range
...
The Fig
...
shows the circuit diagram of an Wien-bridge oscillator
...
RC bridge circuit is a lead lag network
...
By
adding a feedback network, the oscillator becomes sensitive to a signal of only one particular
frequency
...
Fig
...
The bridge is balanced only when
R4 (R2 / (1+jωC2R2)) = R3 (R1 – j / ωC1)
R2 R4 = R3 (1 + jωC2R2) (R1 – j / ωC1)
or
R2R4 – R3R1 – (C2 / C1) R2R3 + (jR3 / ωC1) – j ωC2R2R1R3=0
Separating real and imaginary parts, we have
R2R4 – R3R1 – (C2 / C1) R2R3=0
or
(C2 / C1) = (R4/ R3) – (R1 / R2)
and (R3 / ωC1) – ωC2R2R1R3=0
ω2= (1 / C2C1R2R1) or ω=√(1 / C2C1R2R1)
fo= 1/ (2 π √(R1R2C1C2))
If R1 = R2 = R and C1 = C2 = C then
fo = 1/(2 π x R x C)
and
R4=2R3
Q
...
Frequency range:
The oscillator selected for a particular application should be capable of supplying an output
signal whose upper and lower frequency limits exceeds those required by the application
...
2
...
108
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BASIC ELECTRONICS
3
...
Frequency stability determines how
closely the oscillator maintains a constant frequency over a given time period
...
Waveform distortion:
This quantity is the measure of how closely the output waveform of the oscillator resembles a
pure sinusoidal signal
...
5
...
The output impedance of the oscillator be equal to the characteristic impedance of the
system to which it is to be connected
...
71
In a circuit shown in figure below, calculate and sketch the waveforms of current i over one
period of input voltage
...
(14)
Ans:
Between the duration 0 and π /2 both diodes are ON
...
Between the duration π and 3 π /2 both diodes are OFF
...
i = 1/2 (sin t + cos t)
for 0 ≤ t ≤ π /2
i = 1/2 (sin t)
for π /2 ≤ t ≤ π
i=0
for π ≤ t ≤ 3 π /2
i = 1/2 (cos t)
for 3 π /2 ≤ t ≤ 2 π
109
AE05
Q
...
(7)
Ans:
Bistable multivibrator (BVM)
It has two absolutely stable states
...
Since one trigger pulse causes the multivibrator to flip from one state to another and the next
pulse causes it to flip back to its original state, the multivibrator is also known as “flip-flop”
circuit
...
34a
Circuit operation:
In the circuit shown in Fig
...
Similarly, when Q2 is OFF, the potential divider from VCC to –VBB (RL2, R1, and R3) is
designed to keep the base of Q1, at about 0
...
Now suppose a
positive pulse is applied to R, it will cause Q2 to conduct
...
Q
...
(7)
Ans:
For a sequential system, we must know what has happened in the past
...
The basic unit of this
storage is flip-flop
...
e
...
A flip-flop maintains its output state until directed by an input signal to change its state
...
S-R flip-flop:
It uses a pair of cross coupled transistors as shown in Fig
...
When, transistor T1 is in
saturation then its collector voltage is the base drive for transistor T2, i
...
, no base drive for
T2
...
This drives
the base of T1 and thus T1 operates in saturation region
...
36a
In effect T2 is OFF and T1 is ON making Q=1(+VCC)
...
By introducing one input at the base of each transistor we can control the
state of operation of the transistor
...
74
Explain with a neat diagram the working of a BCD counter
(7)
Ans:
BCD decade counter goes through a straight binary sequence from 0000 to 1001 state
...
The circuit of a BCD counter is given in fig
...
– A BCD counter
This is implemented by connecting these inputs to a constant high level
...
__
This is implemented by ANDing QA and QD and connecting the gate output to JK inputs of
FlipFlop -B
...
FlipFlop -D changes on next clock pulse each time QA = 1 and QB = 1, QC = 1 or when
QA = 1 and QD =1
JD = KD =QAQBQC+QAQD
Q
...
Also give the equivalent circuit of the opamp
...
In this stage high-gain is
desirable so that there would be a negligible effect on the output of any shortcoming in the
following stages
...
The second stage is usually another differential amplifier, which is driven by the output of
first stage
...
In this amplifier output is measured at the
collector of only one of the two transistors with respect to ground
...
The third stage, known as level shifting stage, is usually an Emitter-follower circuit in order
to shift dc-level at the output of the intermediate stage downward to zero volts with respect
to ground
...
This increase in dc-level tends to shift the
operating point of the succeeding stages which also limits the output voltage swing or may
distort the output signal
...
This stage increases the
output voltage swing and current supplying capability of the amplifier
...
Q
...
Describe its operation and
derive an expression for its pulse period
...
38a(i)
...
Fig
...
7V
...
The capacitor
will charge through Rf towards +Vz as D1 becomes reverse biased
...
38a(ii)
When Vc < - βVz, the comparator again swings back to +Vz and capacitor C will charge
towards +Vz until Vo = VD where ‘C’ will be clamped again at VD
Derivation:
Charging from VD to –Vz: Vc = -Vz + (VD + Vz) e-t/ τ
Where τ = Rf C
...
Hence – βVz = -Vz + (VD + Vz) e-T/ τ
Solving for T, we get T = RfC ln [(VD+Vz)/ (Vz- βVz)] = RfC ln [(1 + VD/ Vz)/ 1-β]
Q
...
(4)
Ans:
Removing triggering circuit, D2 and D1 from the circuit shown in Q
...
38b
...
38b
...
78 Sketch the circuit of a bridge rectifier and describe its operation
...
If a capacitor is added to the circuit,
show the output voltage waveform of the rectifier
...
39a(i)
...
39a(i)
Operation: During positive half cycle of the input voltage point A becomes positive
...
D1 and D2 conduct in series
with the load and the current flows in the direction as shown in figure1 by solid arrows
...
D3 and D4 conduct in series
with the load and the current flows as shown by dotted arrows
...
39a(ii)
...
39a(ii)
Expression for efficiency and ripple factor:
iL = Im sin ωt 0 ≤ ωt ≤ π
iL = -Im sin ωt π ≤ ωt ≤ 2π
π
Idc = (1/π) ∫ Im sin ωt d(ωt)
0
Idc = 2Im / π and Edc = 2Em / π
115
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BASIC ELECTRONICS
In bridge rectifier, in each half cycle two diodes conduct simultaneously
...
PDC = IDC2RL = (2Im/π) 2 RL
PAC = Irms2 (2Rf+Rs+RL) = (Im/√2)2 (2Rf+Rs+RL)
[(4Im2/π2) RL]
Therefore, rectification = PDC/PAC =
efficiency
Im2/2 (2Rf+Rs+RL)
≈
8RL
(since 2Rf+Rs<< RL)
2
π RL
= 8/π2 = 81
...
48
...
39a(iii) shows how a capacitor filter is connected to the rectifier output and the
output voltage waveform of the rectifier across the load, with capacitor filter
...
39a(iii)
Fig
...
39a(iv) shows the rectifier output without filter and solid line
shows the output across the capacitor filter
...
79 Describe using a neat circuit diagram, the operation of a transistor series voltage regulator
...
39b shows the circuit of a transistor series voltage regulator
...
39b
In the above circuit, transistor behaves as an emitter follower
...
e it behaves as a variable
resistor whose value is determined by the base current
...
i
...
Therefore the forward bias of the transistor is
reduced, which reduces the level of conductance
...
Q
...
Write also the canonical SOP expression for F
...
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
AB
0
0
0
0
0
0
1
1
_
AC
0
1
0
1
0
0
0
0
_
AB+AC
0
1
0
1
0
0
1
1
117
BC
0
0
0
1
0
0
0
1
_
(AB+AC)BC
0
0
0
1
0
0
0
1
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BASIC ELECTRONICS
The canonical SOP expression for F is found from 1’s in the 4th and 8th rows
...
e
...
81 Write the logic diagram and truth table of clocked S-R flip flop and explain its operation
...
41a(i) shows clocked RS flip flop
...
The outputs of the two AND gates remain at ‘0’, regardless of the R and S inputs as long as
Cp=0
...
Fig
...
41a(ii) shows truth table for clocked RS flip flop
...
41a(iii) illustrate
the operation of clocked RS flip flop
...
41a(ii)
Drawbacks of SR flip-flop:
i) A 11 input (R =S =1) is not allowed as it will make both Q and Q = 1 while the clock
pulse is 1
...
ii) While clock pulse is 1, change in inputs changes the output
...
41a(iii)
Q
...
41b shows the circuits of a 4-bit ripple counter consisting of edge-triggered flip-flop (JK)
...
41b
In this ripple or asynchronous counter, the clocking for all flip-flops except the one at the LSB
is obtained by the transition of the flip-flop at the previous stage
...
Flip-flops as shown are sensitive to negative edge of clock
signal
...
For each negative transition of
a clock, Q0 changes its state
...
Q2 changes
its state for every 1 to 0 transition of Q1
...
The truth table is as follows:
Clk
Q3
Q2
Q1
Q0
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
119
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BASIC ELECTRONICS
Clk
Q3
Q2
Q1
Q0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
Q
...
Also write their energy band diagrams, clearly showing the different energy levels
...
84 What is Early effect? Explain how it affects the characteristics of BJT in CB configuration
...
238 - 39
Q
...
(8)
Ans: p
...
86
Explain the effect of temperature on a JFET
...
276
...
87
Describe how oscillations are developed in a tank circuit
...
655
Q
...
(i) CMRR
(ii) slew rate
Ans: p
...
826
Q
...
Explain the role of each block
...
908 – 09
...
90
BASIC ELECTRONICS
Draw the circuit of 4-bit ring counter using suitable flip-flop
...
(8)
Ans: p
...
91
Show how a T-flop-flop can be constructed using J-K flip-flop
...
(2)
Ans: p
...
92
Distinguish between avalanche and zener breakdown in p-n junction diode
...
In the case of
avalanche breakdown, the carriers are thermally generated ones accelerating under
externally applied large electric field in reverse bias and the process is cumulative giving
rise to more and more pairs of carriers by multiple collision of ions
...
On the other hand, in a zener diode, the breaking of ionic bond and generation of extra
carriers is by the intense electric field across a very narrow depletion region at the junction,
due mainly to rather heavy doping of both p and n regions of the diode
...
This phenomenon is called
‘Zener breakdown’
...
93 Draw the circuit of Darlington amplifier and analyse it to obtain expressions for its current
(10)
gain and input impedance
...
Ans: The circuit for Darlington amplifier is shown below
The equivalent circuit for small signal is as shown below
121
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BASIC ELECTRONICS
Considering Q 2 , Zin 2 = hfe 2 R E
……(1)
Current Gain: A i 2 = I0e2 / I 2 = I e 2 / I b 2 ~ hfe 2 …
...
Hence without neglecting 1/hoel,
the current gain for Q1 is
h fe1
h fe1
I
A i1 = 2 =
=
……(3)
I1 1 + h Oe1Zin 2 1 + h Oe1 (h fe 2 R E )
If h fe1 = h fe 2 and h oe1 = h oe 2 = h oe , equation (3) can be written as
h fe
Ai1 =
and Ai2 = h fe
1 + hoe (h fe RE )
The overall gain of the amplifier is A i = A i1Ai 2
h fe 2
i
...
, A i =
1 + h oe h fe R E
For h oe h fe R E ≤ 0
...
r
...
(4)
…
...
1 , then Zin1 ≅ h fe 2 R E = β 2 R E
The advantage of darlington amplifier is its very high current gain and very high Zin
...
Q
...
Analyse the equivalent circuit to find an expression for voltage gain and output resistance
...
122
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BASIC ELECTRONICS
Fig(2) shows current source equivalent circuit where gm Vi represents controlled source
and rd represents the incremental drain resistance
...
e
...
Zo + R L
Q
...
Show how stabilization of gain of an amplifier is achieved with negative
feedback
...
If to this amplifier
negative(voltage) feedback is provided, the situation is shown in fig(2)
...
e
...
In fig(2), it is shown that a fraction of the output voltage (i
...
β Vo ) is added negatively (i
...
123
AE05
BASIC ELECTRONICS
negative feedback) to the signal input Vi so that the actual input to the basic amplifier is
Vi − Vf = Vi − β Vo
...
e
...
e
...
e
...
e
...
r
...
A
dA f (1 + Aβ) − Aβ
1
=
=
dA
(1 + Aβ) 2
(1 + Aβ) 2
dA
dA f =
Now divide this expression by (1)
(1 + Aβ) 2
A
Then A f =
1 + Aβ
This shows that though the per unit change in the gain of the basic amplifier is
dA
, the
A
1
times the same
...
change in the gain of the overall amplifier with negative feedback is
Q
...
What type of negative feedback takes place in the
circuit? Analyse the circuit to derive an expression for voltage gain with feedback
...
Its equivalent circuit for analysis is also
shown
...
Hence this is a case of
voltage series feedback
...
Then Vi appears across G and
S
...
Then R is present only in the output circuit
...
The equivalent circuit, by replacing the FET by its low frequency model, is shown in fig(3)
...
Hence β = f = 1
Vo
The gain of the basic amplifier is (as Vi = VGS )
Vo
g m rd Vi
µR
=
=
…………
...
b
...
e
...
b
...
e
...
(2) the expression for gain of the source follower
...
97 Explain the principle underlying the working of R-C oscillators
...
(7)
Ans:
The general requirement for producing oscillations in an amplifier is to provide positive
feedback so that feedback voltage is in phase with the input to the amplifier
...
As an
inverting amplifier provides π (1800) phase shift, it can be used along with a phase shifting
network that provides further π (1800) shift at the desired frequencies as shown in the block
schematic below
...
The R’s and C’s
must be so chosen as to produce 1800 shift at the frequency of oscillation required
...
All these, essentially mean that
Barkhausen criterion of unity loop gain i
...
–Aβ = 1, is network, which also means that
there should be positive feedback to the basic amplifier
...
Q
...
(9)
Ans:
A sample – and – hold circuit is essentially a switch in series with a capacitor, as in fig(1)
fig(1)
S/H Control voltage
Fig(2)
The voltage across the capacitor C tracks the input signal Vi during the time TON, when a
logic control closes the switch S
...
The switch may be a relay, a diode bridge
gate, a BJT or a MOSFET controlled by a gating signal
...
The analog signal Vi to be sampled is to be applied at the drain terminal of the E-MOSFET
and a pulse train is applied at the gate, the MOSFET connects the drain to the source so that
Vin is applied across the capacitor during the time the pulse is present
...
126
AE05
BASIC ELECTRONICS
fig(3)
During the time the MOSFET is ON, the Vi appears across the capacitor and so at the
output of the non-inverting amplifier as Vo
...
During this time, the voltage on C will be held
constant at a value of Vi, which prevailed at the end of TON
...
To obtain an output that closely
approximates the input, the frequency of the control voltage at the gate should be as large as
possible
...
Q
...
Derive an expression for the frequency of the wave
...
127
AE05
BASIC ELECTRONICS
The Zener diodes will clamp the voltage Vi at either + Vz or – Vz depending on the polarity
of the saturation voltage at the output of the comparator
...
V
The current into C is I = z and Vo(t) is given by
R3
1 t
1
V (t ) = V (t ) − ∫ I dt = V (t ) − (t − t )
……………(1)
o
o o C
o o C
o
t
o
Now the voltage Vz(t) is found by using superposition
R V (t )
R 4 Vz
Vz ( t ) =
+ 1 o
R1 + R 4 R1 + R 4
When Vz(t) reaches zero at t = t1, the comparator output changes to V1 = -Vz
...
(3)
i
...
Vz (t1 ) = - 4 Vz
R1
The direction of current into the integrator will reverse from t1 until t2 and is given by
− Vz
I=
= −I
R3
During t2 > t > t1 the Vo(t) will be a positive going ramp
...
(4)
R1
as this value is limited by +Vz
At t2, the comparator switches its output again and the cycle repeats
...
e
...
100 Explain how an astable multivibrator can be implemented using 555 timer IC
...
fig(1)
fig(2)
129
AE05
BASIC ELECTRONICS
At the non-inverting inputs of comparators, the potential division of Vcc across the R’s
causes V1 = 2 3 Vcc and V2 = 13 Vcc
...
Assume that at t = 0, Vc = V2, which causes comp 1 output to be high and Q output of the
latch is in reset condition, which in turn makes V0 ~ 0 volts, as shown in fig 2
...
At t =
T1, let the value of Vc which is also ‘threshold voltage’ of the timer, be V1
...
The transistor Q1 is now cut
off Q = 0
...
At
t = T2 , Vc = V2 again which causes repetition of cycle of events described above
...
1
...
101 Why filters are used along with rectifiers in the construction of a power supply? List the filter
(10)
types used in power supplies
...
Ans:
Necessity of filters for rectifiers:
The output from any basic rectifiers is not a pure d
...
There would be considerable a
...
component in their output, called ‘ripple’, in addition to the desired d
...
component
...
c
...
To construct
a good power supply which gives pure d
...
output, we need to remove or filter out the a
...
component from the output of rectifiers
...
c
...
c
...
fig(1)
Following are the commonly used filter types are:
(i) Capacitor filter (ii) Series inductor filter (iii) Choke input filter (iv) π-filter (v) RC filter
...
(i) Capacitor filter:
It is connected in shunt or parallel with the load as shown in the fig (1)
fig(2)
fig(3)
130
AE05
BASIC ELECTRONICS
This is the simplest and the least expensive filter
...
c
...
In the case of a full-wave rectifier without filter, the load voltage
would also be the rectified waveform shown by the dotted line
...
(ii) Series Inductor filter:
Property of an inductor is to oppose any change in the current through it
...
fig(4)
fig(5)
The inductor or choke stores energy in its magnetic field when the current is above an
average value
...
The effect of the inductor filter is illustrated in fig 5 above
...
C
fig(6)
fig(7)
The effect of the L-Section filter is illustrated in fig 7
...
c
...
(iv) π-filter: The circuit of π-filter is shown in fig 8
...
c
...
The effect
of the filter on a full-wave rectifier output is illustrated in fig 9
...
fig(10)
fig(11)
The disadvantages of the π-filter are its bulk, weight and higher cost
...
However, the R
being dissipative of energy, the overall efficiency of the power supply will be less than
possible with π-section filter
...
Q
...
(3)
Ans:
It is the property of Boolean algebra that for a given Boolean expression there always exists
a dual
...
e
...
: The expression x + xy = x which is law of absorption has a dual x(x + y) = x
...
The K-map for this function is
fig (1)
fig (2)
If a dual map is drawn by replacing ‘1’ by ‘0’ and ‘0’ by ‘1’ as shown in, and if we simplify
the function represented by the map, we get the expression
f d = (A + C)( B + C)(B + D)
= CD + CB + ABD
which is the dual function f = AC + BC + BD
Q
...
(2)
Ans:
Canonical SOP form is directly obtained for
F ( A, B, C ) = ∑ (1,5,7) as ∑ ( M 1 + M 5 + M 7 )
i
...
F(A, B, C) = A BC + ABC + ABC --------- canonical SOP expression
...
e
...
e
...
Q
...
Explain its
operation with reference to truth table
...
When
the clock is low of CK = 0, the outputs of both the gates are ‘1’ irrespective of the values of
S and R
...
e
...
Now let the CK = 1
...
For S = 0, R = 0, the outputs of 3 and 4 are 1
...
This is
indicated in the truth-table, at the first row
...
For these inputs
the Q is 1
...
This action is called ‘setting’ the flip-flop and is indicated at the second row of the truthtable
...
Thus Q will be forced to be at logical zero and Q = 1
...
For S = 1, R = 1, the outputs from both 3 and 4 are zero and therefore the outputs of the
both the gates 1 and 2 are ‘1’
...
Hence the state of the
flip-flop is unidentified or indeterminate
...
Q
...
(5)
Ans:
The requirement of a full adder is indicated in the block shown below
...
Thus considering all the possible combinations for the augend( A n ), addend ( Bn )
and carry( C n −1 ) inputs, the truth-table is drawn to obtain the required ‘sum’ and ‘carry’
outputs, as shown above
...
134
AE05
BASIC ELECTRONICS
For finding simplified expression for Cn, a k-map is drawn as below
k-map for Cn
from the map
Cn = AnBn + AnCn-1 + BnCn-1
The implementations of Sn and Cn are shown by the AND – OR logic below
Q
...
5 K ohm and the capacitors are of
0
...
Determine the PRR (pulse repetition rate)
...
Q
...
The transformer rms secondary voltage from centre tap to each end of secondary is
50V and load resistance is 980
...
(ii) rms load current and output efficiency
...
108
(ii) 50 mA
(iii) 79
Title: electronics questions
Description: test your electronics skill if you think you are smart in electronics ....
Description: test your electronics skill if you think you are smart in electronics ....