Notesale: Turn your study into money

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Copyright © 2008 by Dr
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K
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I n t e r f a c i ng M e mo r y w i t h 8 0 8 5
A microprocessor will have its own address space for accessing physical memory
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For example a microprocessor like 8085 has 16 address lines, and it can
access a physical memory space of 64K starting from 0000H to FFFFH as shown in
Table 3
...
The process of interfacing memories to microprocessor and allocating address
to each memory location is called memory mapping
...
But practically, when ICs are used as memory
devices, instead of a single IC (Integrated Chip), few devices that fit into the address
space will be used
...
For example instead of using a memory device of size
64KB (Kilo Bytes), we can use 8 memory devices with a capacity of 8KB each
...
When
memory blocks are used, to access all the locations in a block n address lines are needed
so that
2n = 8 K
= 23 K
= 23 x 210
= 213
Therefore n = 13
3
...
The data stored in the memory is accessed by specifying its address
...
They are
i)
Each memory location has only one address, there is no duplication in the
address
ii)
Memory can be placed contiguously in the address space of the
microprocessor
iii)
Future expansion can be made easily without disturbing the existing
circuitry
There are few disadvantages in this method
i)
Extra decoders are necessary
ii)
Some delay will be produced by these extra decoders
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K
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Thyagharajan

2

The main advantage of linear select decoding is its simplified decoding circuit
...
But there are many disadvantages in this
decoding
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3
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1

Absolute Address Decoding

The 8085 microprocessor has 16 address lines
...
If all these lines are connected to a single memory
device, it will decode these 16 address lines internally and produces 216 different
addresses from 0000H to FFFFH so that each location in the memory will have a unique
address as shown in table 3
...
1
...

Figure 3
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A15 A14 A13 A12
0 0 0
0

A11 A10 A9 A8
0 0 0 0

A7 A6 A5 A4
0 0 0 0

A3 A2 A1 A0
0 0 0 0

Hex Address
0000H

0

0

0

0

0

0

0

0

0 0

0

0

0

0

0

1

0001H

0

0

0

0

0

0

0

0

0 0

0

0

0

0

1

0

0002H

-

-

-

-

-

-

-

-

-

-

-

-

- - - - -

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

FFFEH

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

FFFFH

Table 3
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K
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Thyagharajan

3

FFFF H
FFFE H
FFFD H

8001 H
8000 H
7FFF H

0002 H
0001 H
0000 H

Figure 3
...
In such cases the physical memory
space of the microprocessor is divided into smaller memory spaces or memory blocks
...
This is called address portioning
...
These three lines are
called the block select address signals and this is called address partitioning
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The starting address and ending address of each block can be found as
shown in Table 3
...
Since each block is an Integrated Chip (IC), and each chip has a
Chip Select signal, the block select address lines must be used to select the ICs
...
Therefore we have to
decode these lines using a 3 to 8 decoder or 1 of 8 decoder
...
The higher 3 address lines (A13,
A14 and A15) are externally decoded by a 3 to 8 decoder
...
2
...
The diagrammatic representation of each block with its
address range shown in figure 3
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Copyright © 2008 by Dr
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K
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2: Address Space for Memory Blocks

0 0

Copyright © 2008 by Dr
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K
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2: 64KB Memory Map
(Eight Blocks)

We use 74LS138 address decoder to generate the chip select signals for each
memory block
...
3
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Similarly when these lines are 001 (C=0, B=0 and A=1) Y1 will be
activated and the second memory block will be selected
...
Since this content is placed on
the address bus while accessing the memory, the microprocessor will start executing the
program from the address 0000H
...
The input may
even be a function key that requires a specific action to be carried over
...
Therefore, in any microprocessor
based system an EPROM should be placed at the reset address (0000H)
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Specifically there should be a RAM for stack operations
...
The
memory map for this case can be given as shown in figure 3
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The EPROM chip must be
selected using the chip select signal CS1 and the RAM1 chip must be selected using CS2
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4
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K
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Thyagharajan

6

A13

A

Y0

CS1

A14

B

Y1

CS2

A15

Block
Select
Address
Signals

C

Y2

CS3

74LS138 Y3

CS4

Y4

CS5

G1

Y5

CS6

G2

Y6

CS7

G3

Y7

CS8

+5V

IO/M

}

Block
Select
Signals

Figure 3
...
Each location in the memory will have a single address
...

Most of the microprocessor based systems do not use the complete 64 KB
memory space
...
For example in the
memory map shown in figure 3
...
5
...
Therefore it is also called absolute address
decoding
...
The memory interface
diagram for this case is given in figure 3
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Copyright © 2008 by Dr
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K
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K
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Thyagharajan

8

FFFF
E000
DFFF

Unused memory space

C000
BFFF
A000
9FFF
8000
7FFF
6000
5FFF Memory
RAM 2
4000 Block3(8KB)
3FFF
2000
1FFF Memory
EPROM
Block1(8KB)
0000

Figure 3
...
6: Interfacing EPROM and RAM

Instead of using 3 to 8 decoder, NAND/AND/OR gates can also be used to
generate chip select signals as shown in figure 3
...
In this case, CS1 will be activated to
select the EPROM, when all the three inputs to the OR gate (OR1) are zero
...
This is also an absolute address decoding method
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K
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Thyagharajan

9

decoders (gates) when we want to add more memory chips
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So no
memory space of the microprocessor is wasted without being used
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7: Address Decoding using OR Gates

3
...
2

Linear Select Address Decoding

In the circuit given in figure 3
...
The outputs Y0 and Y2 of the 74LS138
decoder will be activated as given in table 3
...
Since the address line A15 is not connected
to the decoder and the pin C of the decoder has been grounded, irrespective of the signal
A15 (i
...
A15 is 0 or 1), the pin C is 0
...
e
...
Similarly Y2 will also be selected twice
...
4
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3: Linear Select Address Decoding – Chip Select Signals

Copyright © 2008 by Dr
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K
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8: Linear Select Address Decoding - Circuit Diagram

Block
No

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0

0

0

0

0

0

0

0

0

0

0

0

0 0

0 0

0
0

0
1

0
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

0
1

1
0

0
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

1
1

0
1

0
0

1
0

1
0

1
0

1
0

1
0

1
0

1
0

1 1
0 0

1 1
0 0

1 1
0 0

1

1

0

1

1

1

1

1

1

1

1 1

1 1

1 1

1

3

5

7

Hex
Address
range
0000H
to
1FFFH
4000H
to
5FFFH
8000H
to
9FFFH
C000H
to
DFFFH

Table 3
...
This is due to the signals A13 and A14 which have same values in both
the cases and hence activates the same chip select signal CS1
...
The memory
map for this case is as shown in figure 3
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Copyright © 2008 by Dr
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K
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9: Linear Select Address Decoding – Memory Map
A13

OR 2

OR 1

A13
CS1

CS3

A14

A14

CS
EPROM
8K

CS
RAM 2
8K

A0 - A12 Address Bus

Figure 3
...
We may not simply add additional circuitry without
disturbing the already existing circuit
...
e
...
This type of address decoding is called as Linear Select or partially decoded
addressing
...
The same circuit can also be implemented using OR gates as shown in figure
3
...
In this circuit the OR gates require only two inputs
...
Therefore, linear select addressing reduces the
hardware requirements
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K
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Thyagharajan
3
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11 that reads a byte (opcode) from
the memory
...
The decoder (74LS138) produces the chip select signals from these address
lines after a small decoding delay
...
When the chip select signal enables the memory
chip, since the address has been already placed on the address pins of the memory, the
memory will place the data on the data lines after a small access delay called the memory
access time
...
The memory access time is the time delay between the address placed on the
address bus by the address decoder and the data placed by the memory on the data bus
...
e
...
11 by hashed lines
...
This may
even damage the processor
...
So, the bus contention will
occur when two ICs try to place data on the same bus at the same instant of time
...
Since the RD or WR signal is issued by the processor only after the first Tstate, if these signals are used along with the output of the address decoders to select the
chip, the content of the memory will not be placed before the start of the T2 state
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K
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Thyagharajan

T2

T1

13

T3

T4

CLK

A15
A8
AD7

41H

Unspecified

High-Order Memorry Address

Low-Order address

Data from memory

00H

F

4FH Opcode

AD0

C
Delay in the decoder

ALE
CS

Access Time

Bus Contention

G
Data from
the Memory

4FH Opcode

H
Bus Contention

CS

E

B

RD

D
A

Avoiding Bus
Contention

Figure 3
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K
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Thyagharajan

A13

A
B

Y1

A15

C

CS1

Y0

A14

Y2

+5V

CS2
CS3
CS4
CS5

G1

RD

Y3
Y4

IO/M

14

Y5

CS6

G2

Y6

CS7

Y7

CS8

74LS138

G3

WR

CS
RAM 2

CS
EPROM

A0 - A12 Address Bus

Figure 3
...
12, the CS signal can be
delayed until the end of T1 state
...
In figure 3
...

If you are using logic gates to decode the addresses, bus contention may be
avoided by combining the output of the final stage of the decoder with RD or WR signal
to produce an active low chip select signal
...

Example 3
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Copyright © 2008 by Dr
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K
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13: Memory Map

A memory chip select decoder is used to provide chip select signal for each
memory device (IC)
...
74LS138 is a 3 to 8 decoder and it can be used for this purpose
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To access 1K locations 10 address lines must be used
(210 =1K = 1024 locations)
...
Since 8085 has 16 address lines the decoding can
be indicated as shown below
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14: Variable Address Lines

While accessing 4 K locations the lower 12 bits (A0 – A11) can have either 0 or 1
...
The remaining 4 address lines (A12 A15) are the block select address signals, which decide the memory block number
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If it is 0001 the memory block that can be accessed is 1
...

The following table shows the starting and ending address of each memory block
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K
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Thyagharajan

Block
No

A15 A14 A13 A12 A11 A10 A9 A8

16

A7 A6 A5 A4

0

0

0

0 0

0

0 0 0

0 0

1

0
0

0
0

0 0
0 1

1
0

1 1 1
0 0 0

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

2

0
0

0
0

0
1

1
0

1
0

1 1 1
0 0 0

1 1 1 1
0 0 0 0

1 1 1 1
0 0 0 0

3

0
0

0
0

1
1

0
1

1
0

1 1 1
0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

1
0

1
0

4

0
0

0
1

1
0

1
0

1
0

1 1 1
0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

1
0

1
0

5

0
0

1
1

0
0

0
1

1
0

1 1 1
0 0 0

1 1 1 1
0 0 0 0

1 1
0 0

1
0

1
0

0

1

0

1

1

1

1 1

1

1

1

1

1

1

0

0 0 0

1 1 1 1
:
:
:
0 0 0 0

0 0 0

0

1

1

1

1

1

1

1 1 1

1

15

1 1

1 1

0 0

A3 A2 A1 A0

1 1 1 1

0

0 0

0

Hex
Address
Range
0000H
to
0FFFH
1000H
to
1FFFH
2000H
to
2FFFH
3000H
to
3FFFH
4000H
to
4FFFH
5000H
to
5FFFH

F000H
to
FFFFH

Table 3
...
e
...
When CBA is
001 the O1 will be activated and all other output pins will be at high state
...
e
...
Table 3
...
So this can be
connected to G3 pin of the 74LS138
...
During memory operations IO/M = 0
...
The pin G1 is connected to +5V through a resistor to
enable 74LS138
...
This allows selecting this EPROM chip when the microprocessor sends
address in the range 0000H to 0FFFH
...
Since no memory chip is connected in the address range 2000H to
3FFFH, the output pin Q2 is left free
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K
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Thyagharajan

17

5FFFH and these addresses are covered by Q4 and Q5 pins
...
The output of the AND gate is connected to the chip
select pin of the RAM and this CS will be activated (active low) if either Q4 or Q5 is low
...
e
...

C B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

A
0
1
0
1
0
1
0
1

Output pin Activated
O0
O1
O2
O3
O4
O5
O6
O7

Table 3
...
Since 8K RAM has 13 address
lines in addition to the twelve address lines (A0 to A11) A12 of MPU must also be
connected to the A12 pin of the 8K RAM
...

Y0

A

A12

0000 - 0FFF

A13

B

Y1

1000 - 1FFF

A14

C

Y2

2000 -2FFF

Y3

3000 - 3FFF

+5V

74LS138

Y4
G1

A15

5000 - 5FFF

G2

IO/M

4000 - 4FFF

Y5
Y6

6000 - 6FFF

Y7

7000 - 7FFF

G3

From MPU

Address Bus A11
...
D0

Figure3
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Thyagharajan

3
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The RD or
WR signal starts approximately in the middle of the T2 state and available up to the end
T3 state
...
5 T state or 500 ns (1
...
5 micro seconds) and hence the
memory access time should be less than 500 ns
...
If a low speed memory has access time greater than
this value, Wait cycles are introduced between T2 and T3
...
The
memory can decode the address as soon as it gets the address from the microprocessor
...
For
example 2716 EPROM has access time of 450 ns and therefore it can be directly
interfaced with 3 MHz 8085, but one wait cycle is necessary if it is interfaced with a
microprocessor operating at 5 MHz
...

The READY pin of 8085 processor is used to introduce wait states
...
When this pin is
made low, the processor will enter into wait state until it is made high again
...
16 is required for this purpose
...
17
...

The Q0 output is connected to D1 input of the second flip-flop
...
The complement value of Q1 is available on Q1 pin of the second flip-flop
...
e
...
17
...
It will remain in that state until Q1 becomes high
...
17 and allows memory to take
one more clock period time to place the contents on the bus
...
This will make Q1 logic high and hence the READY signal becomes high and the
processor continues its work
...
The 8085 checks the READY signal at
the second T-state of every machine cycle
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Thyagharajan
D Flip-Flop

+5V
ALE

D Flip-Flop

Q0

D0

19

Q1

D1

CLK

CLK

Q0

Q1

R

R

To READY
Pin of 8085

CLKOUT from 8085

Figure 3
...
17: Timing Diagram with Wait State

T1

Copyright © 2008 by Dr
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K
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4

20

Interfacing More than 64K Memory

The 8085 microprocessor can address only 64K memory at a time, if you want to
interface more than 64K memory; you can use a jumper or an IO port bit as shown in
figure 3
...
the chip select signal CS3 will select RAM 2 if the jumper connects B and C
and it will select RAM 3 if the jumper connects A and B
...
The main difference between
jumper selection and port bit selection is the manual selection in the first case and
automatic or program activated selection in the second case
...
4: Memory Interface Diagram

Figure 3
...
Any memory chip that is being
interfaced with processor must fit into this memory space
...
There are two types of address
decoding viz absolute address decoding and linear select address decoding
...




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