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Title: VHDL NOTES
Description: In this note, we describe: 1. About VHDL 2. Fundamental VHDL Units 3. LIBRARY Declarations 4. ENTITY 5. ARCHITECTURE 6. VHDL reserved words
Description: In this note, we describe: 1. About VHDL 2. Fundamental VHDL Units 3. LIBRARY Declarations 4. ENTITY 5. ARCHITECTURE 6. VHDL reserved words
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VHDL Notes
1
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#1
About VHDL
VHDL is a hardware description language
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2
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3
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4
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5
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An
additional standard, the IEEE 1164, was later
added to introduce a multi-valued logic system
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Fundamental VHDL Units
As depicted in figure 1, a standalone piece of VHDL
code is composed of at least three fundamental sections:
LIBRARY declarations: Contains a list of all libraries to
be used in the design
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ENTITY Specifies the I/O pins of the circuit
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A LIBRARY is a collection of commonly used pieces of
code
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The typical
structure of a library is illustrated in figure 2
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VHDL Notes
3
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LIBRARY library_name;
type is employed in the design
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USE library_name
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package_parts;
The std is a resource library (data types, text i/o, etc
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vhd file, plus all files
sign:
1
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ieee
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work (work library)
Their declarations are as follows:
LIBRARY ieee;
USE ieee
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all;
LIBRARY std;
USE std
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all;
LIBRARY work;
USE work
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created by the compiler, simulator, etc
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(8
levels)
and
std_logic_arith: Specifies the SIGNED and UNSIGNED data types
and related arithmetic and comparison operations
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std_logic_signed: Contains functions that allow operations with
STD_LOGIC_VECTOR data to be performed as if the data were of type
SIGNED
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no need to declare them; only the ieee library must be explicitly written
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#1
INTRODUCTION and CODE STRUCTURE
ENTITY
An ENTITY is a list with specifications of all input and output pins (PORTS) of the
circuit
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ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
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IN and OUT are
truly unidirectional pins, while INOUT is bidirectional
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The type of the signal can be BIT, STD_LOGIC, INTEGER, etc
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Example: NAND Gate
ENTITY nand_gate IS
PORT (
A : IN Bit;
B : IN Bit;
C : OUT Bit);
END nand_gate;
3
5
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Its syntax is the following:
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END
architecture_name;
As shown above, an architecture has two parts: a declarative part (optional),
where signals and constants (among others) are declared, and the code part
(from BEGIN down)
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Example: NAND Gate
ARCHITECTURE nand_archi OF nand_gate IS
BEGIN
C <= A NAND B
END
nand_archi;
VHDL Notes
6
Title: VHDL NOTES
Description: In this note, we describe: 1. About VHDL 2. Fundamental VHDL Units 3. LIBRARY Declarations 4. ENTITY 5. ARCHITECTURE 6. VHDL reserved words
Description: In this note, we describe: 1. About VHDL 2. Fundamental VHDL Units 3. LIBRARY Declarations 4. ENTITY 5. ARCHITECTURE 6. VHDL reserved words