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HNC Electrical and Electronic Engineering
Year One - 2013/14
Module: Digital & Analogue Devices

Logic
Families

Keith A
...
Hudson

2

Digital & Analogue Devices
13 April, 2014

Contents
1

Logic Families (Task 1)
...
1
1
...
10

1
...
8

TTL vs CMOS
...
13
2
...
13

2
...
1

Voltage Comparison
...
1
...
14

2
...
3

Fan-Out
...
2

CMOS Driving TTL
...
2
...
15

2
...
2

Current Comparison
...
2
...
17

2
...
18

Combinational Logic (Task 2)
...
1

Mixed Logic
...
2

NAND Only Logic
...
3

Optimised NAND Only Logic
...
4

Why NAND Only Logic?
...
35

5

Combinational / Sequential Logic (Task 4)
...
49

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7
Figure 2: I/O voltage levels for standard 74XX TTL series
...
9
Figure 4: Use of a pull-up resistor
...
18
Figure 6: Low voltage output driving high voltage Loads
...
19
Figure 8: I/P '0000' O/P '0'
...
21
Figure 10: I/P '0010' O/P '0'
...
21
Figure 12: I/P '0100' O/P '0'
...
22
Figure 14: I/P '0110' O/P '0'
...
22
Figure 16: I/P '1000' O/P '1'
...
23
Figure 18: I/P '1010' O/P '1'
...
23
Figure 20: I/P '1100' O/P '0'
...
24
Figure 22: I/P '1110' O/P '0'
...
24
Figure 24: I/P '0000' O/P '0'
...
25
Figure 26: I/P '0010' O/P '0'
...
26
Figure 28: I/P '0100' O/P '0'
...
26
Figure 30: I/P '0110' O/P '0'
...
27
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Figure 33: I/P '1001' O/P '1'
...
27
Figure 35: I/P '1011' O/P '1'
...
28
Figure 37: I/P '1101' O/P '1'
...
28
Figure 39: I/P '1111' O/P '0'
...
30
Figure 41: I/P '0001' O/P '1'
...
30
Figure 43: I/P '0011' O/P '0'
...
31
Figure 45: I/P '0101' O/P '1'
...
31
Figure 47: I/P '0111' O/P '0'
...
32
Figure 49: I/P '1001' O/P '1'
...
32
Figure 51: I/P '1011' O/P '1'
...
33
Figure 53: I/P '1101' O/P '1'
...
33
Figure 55: I/P '1111' O/P '0'
...
35
Figure 57: LSB
...
36
Figure 58: LSB
...
36
Figure 59: LSB
...
36
Figure 60: LSB
...
37
Figure 61: LSB
...
37
Figure 62: LSB
...
37
Figure 63: LSB
...
37
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MSB '1110' ==> '7'
...
MSB '0001' ==> '8'
...
MSB '1001' ==> '9'
...
MSB '0101' ==> 'A' (10)
...
MSB '1101' ==> 'b' (11)
...
MSB '0011' ==> 'C' (12)
...
MSB '1011' ==> '0' (13)
...
MSB '0111' ==> 'E' (14)
...
MSB '1111' ==> '0' (F)
...
MSB '0000' ==> '0' back to the start
...
Adapted from (Tangient LLC, 2014)
...
MSB '0000' ==> '0'
...
MSB '1000' ==> '1'
...
MSB '0100' ==> '2'
...
MSB '1100' ==> '3'
...
MSB '0010' ==> '4'
...
MSB '1010' ==> '5'
...
MSB '0110' ==> '6'
...
MSB '1110' ==> '7'
...
MSB '0001' ==> '8'
...
MSB '1001' ==> '9'
...
MSB '0000' ==> '0' Back to the start
...
Adapted from (Tangient LLC, 2014)
...
3 Logic-1
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Tables
Table 1: TTL chip families
...
10
Table 3: Advantages and disadvantages of TTL and CMOS
...
11
Table 5: Electrical characteristics
...
13
Table 7: TTL o/p to CMOS i/p - current comparison
...
14
Table 9: CMOS o/p to TTL i/p - voltage comparison
...
16
Table 11: Fan-out CMOS driving TTL – High level “1”
...
17
Table 13: F = A
...
D
...
42
Table 15: Karnaugh Map
...
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Digital & Analogue Devices
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1 Logic Families

(Task 1)

Figure 1: Different Logic Families (Nailis, 2014)

Logic gates are built using transistors
...

The CMOS family of logic gates is created by connecting NMOS and PMOS transistors
...
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1
...
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Figure 2 shows how noise margin are calculated
...
e
...


Figure 3: Propagation Delays

HNC Electrical and Electronic Engineering

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2 Complementary Metal-Oxide-Semiconductor (CMOS)
Table 2: CMOS chip families

Chip family

Description

Acronym

4000

Original CMOS

40H00

High Speed CMOS
(Slower than LS TTL)

74C00

CMOS
...
Pin compatible
...

Greater noise immunity
...
3 TTL vs CMOS
Table 3: Advantages and disadvantages of TTL and CMOS

Family
TTL
CMOS

Advantages
More robust – less susceptible to static damage
Lowest power consumption
Most common logic family today
Used in all PC processor chips

HNC Electrical and Electronic Engineering

Disadvantages
Uses more power than CMOS
Susceptible to damage by static and voltage
spikes

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supply voltage

𝑉 𝐶𝐶(𝑚𝑎𝑥)

5
...
25V

5
...
0V

5
...
supply voltage

𝑉 𝐶𝐶(𝑚𝑖𝑛)

4
...
75V

4
...
0V

4
...
logic-1 output voltage

𝑉 𝑂𝐻(𝑚𝑖𝑛)

2
...
7V

2
...
95V

4
...
9V

Min
...
0V

2
...
0V

3
...
5V

2
...
4V

0
...
5V

1
...
4V

2
...
logic-0 output voltage

𝑉 𝑂𝐿(𝑚𝑎𝑥)

0
...
5V

0
...
05V

0
...
1V

Max
...
8V

0
...
8V

1
...
0V

0
...
4V

0
...
3V

1
...
9V

0
...
output current (logic-1)

𝐼 𝑂𝐻(𝑚𝑎𝑥)

-0
...
4mA

-0
...
4mA

4mA

4mA

Max
...
04mA

0
...
02mA

1μA

1μA

1μA

10

20

20

400

4000

4000

Fan-out (logic-1)

𝑁=

𝐼 𝑂𝐻(𝑚𝑎𝑥)
𝐼 𝐼𝐻(𝑚𝑎𝑥)

Max
...
4mA

4mA

4mA

Max
...
6mA

-0
...
1mA

1μA

1μA

1μA

10

11

40

400

4000

4000

Fan-out (logic-0)

𝑁=

𝐼 𝑂𝐿(𝑚𝑎𝑥)
𝐼 𝐼𝐿(𝑚𝑎𝑥)

(Note: based on a 5V supply, where not stated)

HNC Electrical and Electronic Engineering

Year One: 2013/14

Keith A
...
Hudson

Digital & Analogue Devices
13 April, 2014

13

2 TTL and CMOS Interoperability
2
...
e
...
)
2
...
1 Voltage Comparison
Table 6: TTL o/p to CMOS i/p - voltage comparison

TTL Output

CMOS Input

𝑽 𝑶𝑯(𝑴𝑰𝑵)

Series

𝑽 𝑰𝑯(𝑴𝑰𝑵)

Comments
Series

5
...
0V
3
...
5V

74AHC Pull-up resistor required to use these
4000/74HC/74AC CMOS devices
...
0V
74ALS
74LS/74AS
74

2
...
5V
2
...
0V

2
...
65V
1
...
0V

74AHC
4000B/74AC

𝑉 𝑂𝐿(𝑀𝐴𝑋) ≤ 𝑉𝐼𝐿(𝑀𝐴𝑋) so the “0” voltage
1
...
8V 74HCT/74ACT/74AHCT

74LS/74AS/74ALS 0
...
4V
0
...
In order to use
4000, 74HC, 74AC and 74AHC CMOS chips we must use a pull-up resistor (see Figure 4)
...
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Digital & Analogue Devices
13 April, 2014

14

Figure 4: Use of a pull-up resistor

2
...
2 Current Comparison
Table 7: TTL o/p to CMOS i/p - current comparison

TTL Output
Series
74ALS
74AS
74F
74/74LS

𝑰 𝑶𝑯(𝑴𝑨𝑿)
400mA
2
...
0mA
0
...

2
...
3 Fan-Out
Table 8: Fan-out TTL driving CMOS

“1” 𝑁 =

𝑇𝑇𝐿 𝐼 𝑂𝐻(𝑚𝑎𝑥)
𝐶𝑀𝑂𝑆 𝐼 𝐼𝐻(𝑚𝑎𝑥)

=

0
...
I
...
one TTL device could drive up to 400
CMOS devices
...


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Year One: 2013/14

Keith A
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2 CMOS Driving TTL
(I
...
CMOS output to TTL input
...
2
...
95V
4
...
4V

Series

5
...
0V
𝑉 𝑂𝐻(𝑀𝐼𝑁) ≥ 𝑉𝐼𝐻(𝑀𝐼𝑁) so the “1”
voltage is compatible
74AHCT

3
...
0V

2
...
0V 74/74LS/74AS/74ALS

1
...
8V 74/74LS/74AS/74ALS
0
...
1V
4000B
0
...
0V

CMOS Output

𝑽 𝑰𝑳(𝑴𝑨𝑿)

Series

TTL Input

Comments

As Table 9 shows all the CMOS chips are voltage compatible with all of the TTL chips
...
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Digital & Analogue Devices
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2
...
2 Current Comparison
Table 10: CMOS o/p to TTL i/p - current comparison

CMOS Output
Series
74AC/74ACT
74AHC/74AHCT
74HC/74HCT
4000B

𝑰 𝑶𝑯(𝑴𝑨𝑿)
24
...
0mA
4
...
4mA

TTL Input
𝑰 𝑰𝑯(𝑴𝑨𝑿)

24
...
0mA
4
...
4mA

𝑰 𝑶𝑳(𝑴𝑨𝑿)

CMOS Output

74
74F
74AS
74LS

100μA

4000B

1
...
6mA
0
...
4mA

74ALS

𝑰 𝑰𝑳(𝑴𝑨𝑿)

Series

TTL Input

For 4000B CMOS chips
𝐼 𝑂𝐿(𝑀𝐴𝑋) ≥ 𝐼 𝐼𝐿(𝑀𝐴𝑋) so the “0”
current is compatible for these TTL chips

Comments

As Table 10 shows all (but the 4000B) CMOS chips are current compatible with all of the TTL chips
...


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Year One: 2013/14

Keith A
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2
...
04

0
...
02

0
...
02

74AC/74ACT

24

600

1200

1200

1200

1200

74AHC/74AHCT

8

200

400

400

400

400

74HC/74HCT

4

100

200

200

200

200

4000B

0
...
6

0
...
5

0
...
1

24

15

40

48

60

240

8

5

13

16

20

80

4

2

6

8

10

40

0
...

Note: 4000B CMOS chip cannot directly drive any of the following TTL chips: 74, 74F, 74AS
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2
...

The input to the buffer should match the output of the driver chip
...

A buffer can also be used to match voltage levels
...


Figure 6: Low voltage output driving high voltage Loads

Figure 6 shows the use of a voltage level translator buffer to drive a high voltage load from a low voltage
driver
...
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Figure 7: High-voltage o/p driving a low-voltage load

Figure 7 shows a low voltage buffer which can tolerant a 5V inputs as an interface to a low voltage load
from a high voltage driver
...
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20

3 Combinational Logic

(Task 2)

Table 13: 𝑭 = 𝑨
...
B

C

C
...
B + C
...
1 Mixed Logic
Error! Reference source not found
...
The
circuit is constructed using two NOT gates, two AND and one NOT gate
...
to Figure 23 shows the output value for all permutations of the input
conditions
...
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Figure 9: I/P '0001' O/P '1'

Figure 10: I/P '0010' O/P '0'

Figure 11: I/P '0011' O/P '0'

Figure 12: I/P '0100' O/P '0'

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13 April, 2014

Figure 17: I/P '1001' O/P '1'

Figure 18: I/P '1010' O/P '1'

Figure 19: I/P '1011' O/P '1'

Figure 20: I/P '1100' O/P '0'

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13 April, 2014

3
...
The circuit is constructed using
NAND gates only
...
)

Figure 24: I/P '0000' O/P '0'

Figure 25: I/P '0001' O/P '1'

Figure 26: I/P '0010' O/P '0'

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Digital & Analogue Devices
13 April, 2014

Figure 31: I/P '0111' O/P '0'

Figure 32: I/P '1000' O/P '1'

Figure 33: I/P '1001' O/P '1'

Figure 34: I/P '1010' O/P '1'

HNC Electrical and Electronic Engineering

Year One: 2013/14

Keith A
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Digital & Analogue Devices
13 April, 2014

Figure 39: I/P '1111' O/P '0'

HNC Electrical and Electronic Engineering

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Keith A
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3 Optimised NAND Only Logic
Figure 40 to Figure 55 show the circuit for the truth table (see Table 13)
...


Figure 40: I/P '0000' O/P '0'

Figure 41: I/P '0001' O/P '1'

Figure 42: I/P '0010' O/P '0'

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13 April, 2014

Figure 47: I/P '0111' O/P '0'

Figure 48: I/P '1000' O/P '1'

Figure 49: I/P '1001' O/P '1'

Figure 50: I/P '1010' O/P '1'

HNC Electrical and Electronic Engineering

Year One: 2013/14

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Hudson

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Digital & Analogue Devices
13 April, 2014

Figure 55: I/P '1111' O/P '0'

3
...
The change to NAND-only logic has not affected the output of the circuit
...

The originally circuit used 3 different types of logic
...

The final circuit has five Boolean operators, the same as the original circuit, but now they are all the same
type: NAND
...

The cost of a logic chip is fairly standard, regardless of the type of gates contained
...
(More if the additional wiring is taken into account
...

Placing three chips on a board takes three times as long as placing one chip (even if a robot is doing it)
...

NOR only circuits can also be used with similar results
...
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4 Sequential Logic

Digital & Analogue Devices
13 April, 2014

(Task 3)

Figure 56: 74LS73- Dual JK Flip-flop

A four stage ripple through counter can be constructed using four J-K flip-flops
...

In general, the number of discrete values that a multi-stage ripple through counter produces is given by the
equation:
[0
...

So a four stage counter will have values:
[0
...
(16 − 1)] = [0
...
e
...

This counter can count up to 15, but we wish to count from 0 to 9
...
e
...
This can be achieved
by connecting bits four (MSB) and two to a NAND gate
...
The counter will reach 1010 for a split-second before the output from all four flip-flops is reset to low
(0)
...

(Note: We are not interested in ̅ so it is not connected to anything
...
Together they form a binary-code decimal
counter
...

The J and K inputs of each flip-flop are joined together and connected to a high (1) signal
...

A signal generator is connected to the clock (CLK) input of U1:A
...
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Digital & Analogue Devices
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The output Q from U1:A is connected to the clock (CLK) input of U1:B
...

The output Q from U2:A is connected to the clock (CLK) input of U2:B
...
This toggles the
state of the next stage
...

Figure 57 to Figure 73 shows one complete cycle of the counter
...
MSB '0000' ==> '0'

Figure 58: LSB
...
MSB '0100' ==> '2'

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MSB '1100' ==> '3'

Figure 61: LSB
...
MSB '1010' ==> '5'

Figure 63: LSB
...
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Digital & Analogue Devices
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Figure 64: LSB
...
MSB '0001' ==> '8'

Figure 66: LSB
...
MSB '0101' ==> 'A' (10)

HNC Electrical and Electronic Engineering

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Keith A
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MSB '1101' ==> 'b' (11)

Figure 69: LSB
...
MSB '1011' ==> '0' (13)

Figure 71: LSB
...
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Digital & Analogue Devices
13 April, 2014

Figure 72: LSB
...
MSB '0000' ==> '0' back to the start
...
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Digital & Analogue Devices
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Figure 74 shows the timing of the circuit
...

Notice U1A goes high as clock pulse 1 goes from high to low
...

When U1:B goes from high to low (at the end of clock pulse 4), U2:A goes high
...

At the end of clock pulse 16 the count starts over
...
Adapted from (Tangient LLC, 2014)

HNC Electrical and Electronic Engineering

Year One: 2013/14

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When the counter reaches 1010 (10102 )
it is reset back to zero
...
Those circled in red are all “don’t care” states
so we can ignore that group
...
For all four terms “A” and “C” are constant
...
𝐷
The counter (in the previous circuit) can count up to 15, but we wish to count from 0 to 9
...
The counter will reach 1010
for a split-second before the output from all four flip-flops is reset to low (0)
...

Figure 75 to Figure 85 show the counter increment until 1010 is reached, at which point the reset occurs
and the counter starts again at zero
...
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Digital & Analogue Devices
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Figure 75: LSB
...
MSB '1000' ==> '1'

Figure 77: LSB
...
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Figure 78: LSB
...
MSB '0010' ==> '4'

Figure 80: LSB
...
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Digital & Analogue Devices
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Figure 81: LSB
...
MSB '1110' ==> '7'

Figure 83: LSB
...
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Digital & Analogue Devices
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Figure 84: LSB
...
MSB '0000' ==> '0' Back to the start

HNC Electrical and Electronic Engineering

Year One: 2013/14

Keith A
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Starting from the top:






A signal generator produces pulses that are connected to the clock (CLK) input of U1:A
...

When U1:A goes from high to low (at the end of clock pulse 2), U1:B goes high
...

When U2:A goes from high to low (at the end of clock pulse 8), U2:B goes high
...


Figure 86: Timing diagram for 0-9 Ripple Counter
...
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Figure 87 shows the above circuit wired up using a Digiac 3000-4
...


Figure 87: DIGIAC 3000-4
...
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6 Bibliography
Anon
...
d
...
[Online]
Available at: http://www
...
dk/electronics/toolbox/lookuptables/logic
...

Crompton, M
...
Mike C's Homepage
...
humber
...
Crompton/
[Accessed 17 05 2014]
...
EE201: Digital Circuits and Systems
...
eeng
...
ie/~ee201/indexold
...

Jain, R
...
, 2010
...
4th ed
...

Nailis, M
...
L4-HNC-CombinationalLogic-01, Middlesbrough: Middlesbrough College
...
ceng - Flip-Flops
...
wikispaces
...


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