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Title: computer architecture
Description: Most important questions with solution which generally asked in exams ...
Description: Most important questions with solution which generally asked in exams ...
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AC07/AT07
Computer Architecture
TYPICAL QUESTIONS & ANSWERS
PART - I
OBJECTIVE TYPE QUESTIONS
Each Question carries 2 marks
...
1
In a virtual memory system, the addresses used by the programmer belongs to
(A) memory space
...
(C) address space
...
Ans: C
An address used by programmers in a system supporting virtual memory concept is
called virtual address and the set of such addresses are called address space
...
2
The method for updating the main memory as soon as a word is removed from the
Cache is called
(A) Write-through
(B) write-back
(C) protected write
(D) cache-write
Ans: B
In this method only cache location is updated during write operation
...
3
A control character is sent at the beginning as well as at the end of each block in the
synchronous-transmission in order to
(A) Synchronize the clock of transmitter and receiver
...
(C) Detect the error in transmission and received system
...
Ans B
As the data are sent continuously as a block of data at the rate dictated by the clock
frequency, so the receiver should be supplied with the same function about the same
bit length in order to interrupt the information
...
4
In a non-vectored interrupt, the address of interrupt service routine is
(A) Obtained from interrupt address table
...
(C) Obtained through Vector address generator device
...
Ans: D
The source device that interrupted the processor supply the vector address which
helps processor to find out the actual memory location where ISR is stored for the
device
...
5
Computer Architecture
Divide overflow is generated when
(A) Sign of the dividend is different from that of divisor
...
(C) The first part of the dividend is smaller than the divisor
...
Ans: B
If the first part of the dividend is greater than the deviser, then the result should be
of greater length, then that can be hold in a register of the system
...
Q
...
(B) operand forwarding
...
(D) loop buffer
...
Q
...
(B) External interrupt
...
(D) Software interrupt
...
So it is a
program dependent, hence interrupt activated
...
8
Arithmetic shift left operation
(A) Produces the same result as obtained with logical shift left operation
...
(C) Needs additional hardware to preserve the sign bit
...
Ans: A
If the register hold minus five in two’s compliment form than in arithmetic shift left
the contents of the register shall be
It is found that the register contents multiplied by two after logical shift left
operation
...
2
AC07/AT07
Q
...
(B) CISC architecture
...
(D) Stack-organized architecture
...
Q
...
(B) assembler
...
(D) generated by operating system
Ans: B
During the first pass of assembler address symbol table is generated which contains
the label used by the programmer and its actual address with reference to the stored
program
...
11
The ASCII code for letter A is
(A) 1100011
(C) 1111111
(B) 1000001
(D) 0010011
Ans
...
12
The simplified expression of (A+B) + C is
(A) (A + B)C
(B)
(C) (C+A + B)
(D)
Ans
...
13
(C)
ABCD - seven segment decoder / driver in connected to an LED display
...
(A)b, c
(B)
c, b
(C)a, b, c
(D)
a, b, c, d
Ans
...
15
(A)
The negative numbers in the binary system can be represented by
(A) Sign magnitude
(B)
I's complement
(C) 2's complement
(D)
All of the above
Ans
...
14
A(B + C)
None of these
(A)
How many flip-flops are required to produce a divide-by-32 device?
(A)4
(B)
6
3
AC07/AT07
Computer Architecture
(C)5
Ans
...
16
(B)
(D)
(B)
Which of the following is a self complementing code?
(A) 8421 code
(B)
5211
(C) Gray code
(D)
Binary code
Ans
...
22
(C)
How many 128 x 8 RAM chips are needed to provide a memory capacity of
2048 bytes?
(A) 8
(B)
16
(C) 24
(D)
32
Ans
...
21
(A)
DMA interface unit eliminates the need to use CPU registers to transfer data
from
(A) MAR to MBR
(B)
MBR to MAR
(C) I/O units to memory
(D)
Memory to I/O units
Ans
...
20
to
What is the bit storage capacity of a ROM with a 512' 4-organization?
(A) 2049
(B)
2048
(C) 2047
(D)
2046
Ans
...
19
(C)
How many different addresses are required by the memory that contain 16K
words?
(A)16,380
(B)
16,382
(C)16,384
(D)
16,386
Ans
...
18
7
The content of a 4-bit register is initially 1101
...
What is the content of the register after each shift?
(A)1110, 0111
(B)
0001, 1000
(C)1101, 1011
(D)
1001, 1001
Ans
...
17
(D)
(A)
Which gate can be used as anti-coincidence detector?
(A) X-NOR
(B)
NAND
(C) X-OR
(D)
NOR
Ans
...
23
Which of the following technology can give high speed RAM?
(A)
TTL
(B)
CMOS
(C)
ECL
(D)
NMOS
Ans
...
24
(C)
Which is true for a typical RISC architecture?
(A)
Micro programmed control unit
...
(C)
Have few registers in CPU
...
Ans
...
27
(C)
After reset, CPU begins execution of instruction from memory address
(A)
0101H
(B)
8000H
(C)
0000H
(D)
FFFFH
Ans
...
26
(C)
In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped
I/O technique?
(A)
Either 256 input devices or 256 output devices
...
(C)
256 input devices & 256 output devices
...
Ans
...
25
Computer Architecture
(A)
When an instruction is read from the memory, it is called
(A)
Memory Read cycle
(B)
Fetch cycle
(C)
Instruction cycle
(D)
Memory write cycle
Ans
...
28
Which activity does not take place during execution cycle?
(A)
ALU performs the arithmetic & logical operation
...
(C)
Next instruction is fetched
...
Ans
...
29
A circuit in which connections to both AND and OR arrays can be
programmed is called
(A)
RAM
(B)
ROM
(C)
PAL
(D)
PLA
Ans
...
30
If a register containing data (11001100)2 is subjected to arithmetic shift left
operation, then the content of the register after 'ashl' shall be
(A)
(11001100)2
(B)
(1101100)2
(C)
(10011001)2
(D)
(10011000)2
Ans
...
31
Which logic is known as universal logic?
(A)
PAL logic
...
(D)
Ans
...
32
(A)
How many memory chips of (128 x 8) are needed to provide a memory
capacity of 4096 x 16?
(A)64
(B)
AB
(C)32
(D)
None
Ans
...
34
(B)
The time for which the D-input of a D-FF must not change after the clock is
applied is known as
(A)
Hold time
...
(C)
Transition time
...
Ans
...
33
NAND logic
...
(A)
In addition of two signed numbers, represented in 2' s complement form
generates an overflow if
(A)
A
...
(C)
Where A is the carry in to the sign bit position and B is the carry out of the
Sign bit position
...
35
Addition of (1111)2 to a 4 bit binary number 'a' results:(A)
Incrementing A
(B)
Addition of (F)H
(C)
No change
(D)
Decrementing A
Ans
...
36
(C)
In a microprocessor system, suppose
...
(D)
6
AC07/AT07
Q
...
Q
...
Q
...
43
(B)
(D)
(44)H
(55)H
(A)
Which flag of the 8085's flag register is not accessible to programmer
directly?
(A)Zero flag
(B)Carry flag
(C)Auxiliary carry flag
(D)Parity flag
Ans
...
42
Logical instructions
instructions to assembler
...
(A) more, faster
(B) more, slower
(C) less, slower
(D) less, faster
Ans
...
40
(B)
(D)
An attempt to access a location not owned by a Program is called
(A)
Bus conflict
(B)
Address fault
(C)
Page fault (D)
Operating system fault
Ans
...
39
Computer Architecture
(C)
Cache memory works on the principle of
(A) Locality of data
...
(B)
Which of the following is a Pseudo instruction?
(A)
SPHL
(B)
7
LXI
AC07/AT07
Computer Architecture
(C)
Ans
...
44
NOP
(D)
A demultiplexer can be used as
(A)Encoder
(C)Multiplexer
Ans
...
45
(C)
(C)
(B)
Which of the following expression is not equivalent to x?
(A) x NAND x
(B)
x NOR x
(C) x NAND 1
(D)
x NOR 1
Ans
...
50
(B)
Which of the following interrupt is maskable?
(A)INTR
(B)RST 7
...
Q
...
of NAND gate required to implement a Ex-OR function is
(A)2
(B)3
(C)4
(D)5
Ans
...
48
(B)Decoder
(D)None of the above
Which of the memory holds the information when the Power Supply is switched
off?
(A) Static RAM
(B) Dynamic RAM
(C) EEROM
(D) None of the above
Ans
...
47
END
Excess-3 equivalent representation of (1234)H is
(A) (1237)Ex-3
(B) (4567)Ex-3
(C) (7993)Ex-3
(D) (4663)Ex-3
Ans
...
46
(D)
(D)
Word 20 contains 40
Word 30 contains 50
Word 40 contains 60
Word 50 contains 70
Which of the following instructions does not, load 60 into the Accumulator
(A) Load immediate 60
(B) Load direct 30
(C) Load indirect 20
8
AC07/AT07
Computer Architecture
(D) both (A) & (C)
Ans
...
51
An interrupt for which hardware automatically transfers the program to a specific
memory location is known as
(A) Software interrupt
(B) Hardware interrupt
(C) Maskable interrupt
(D) Vector interrupt
Ans
...
52
Q
...
Q
...
Q
...
Q
...
Q
...
(C)
Which of the following architecture is/are not suitable for realizing SIMD
(A)Vector Processor
(B)
Array Processor
9
AC07/AT07
Computer Architecture
(C)Von Neumann
Ans
...
58
(A)
(D)
(C)
In a multiprogramming system, which of the following is used
(A)
Data parallelism
(B)
Paging concept
(C)
L1 cache
(D)
None of the above
Ans
...
Q
...
Q
...
(A)
NMOS
(B)
TTL shottky
(C)
PMOS
(D)
both NMOS & PMOS
Ans
...
62
(A'+B)(A'+C)
(A+B)C
A JK flip-flop can be implemented using D flip-flop connected such that
(B) D=JQ+KQ
(A) D=JQ+KQ
Ans
...
61
(B)
(D)
(A)
(C) D=JQ+KQ
Q
...
Q
...
Q
...
Q
...
Q
...
(A)
Large instruction set
(B)
One instruction per cycle
(C)
Simple addressing modes
(D)
Register-to-register operation
Ans
...
66
Computer Architecture
Cache memory
Content addressable memory
(D)
BCD equivalent of Two's complement is
(A)
nine's complement
(B)
(C)
one's complement+1
(D)
Ans
...
69
PAL circuit consists of
(A) Fixed OR & programmable AND logic
(B) Programmable OR & Fixed AND Logic
(C) Fixed OR & fixed AND logic
(D) Programmable OR & programmable AND logic
Ans
...
70
8085 microprocessor carryout the subtraction by
(A) BCD subtraction method
(B) Hexadecimal subtraction method
(C) 2’s complement method
(D) Floating Point subtraction method
Ans
...
71
CPU checks for an interrupt signal during
(A) Starting of last Machine cycle
(B) Last T-State of instruction cycle
(C) First T-State of interrupt cycle
(D) Fetch cycle
Ans
...
72
(B)
During DMA acknowledgement cycle, CPU relinquishes
11
AC07/AT07
Computer Architecture
(A)
Address bus only
(C) Control bus & data bus
Ans
...
73
(B) Address bus & control bus
(D) Data bus & address bus
(D)
If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz
...
8 KHz
(B) 12 KHz
(C) 2 KHz
(D) 8 KHz
Ans
...
74
If the stack pointer is initialised with (4FEB)H, then after execution of Push
operation in 8085 microprocessor, the Stack Pointer shall be
(A) 4FEA
(B) 4FEC
(C) 4FE9
(D) 4FED
Ans
...
75
A more efficient way to organise a Page Table is by means of an associative
memory having
(A) Number of words equal to number of pages
(B) Number of words more than the number of pages
(C) Number of words less than the number of pages
(D) Any of the above
Ans
...
76
(C)
A ⊕ B ⊕ C is equal to A
(A)
A=0, B=1, C=0
(C) A=1, B=1, C=1
Ans
...
78
(A)
If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address
range of Ist RAM is (Assume initial addresses correspond to ROMs)
(A) (8000)H to (9FFF)H
(B) (6000)H to (7FFF)H
(C) (8000)H to (8FFF)H
(D) (9000)H to (9FFF)H
Ans
...
77
(D)
B
C for
(B) A=1, B=0, C=1
(D) All of the above
(D)
Gray code equivalent of (1000)2 is
(A)
(1111)G
(C) (1000)G
Ans
...
1
Computer Architecture
Use K-maps to find the simplest Sum of Products (SOP) form of the function
F = f
...
2
Computer Architecture
Design a combinational circuit that generates 9's complement of a BCD digit
...
0
1
2
3
4
5
6
7
8
9
BCD input
A
0
0
0
0
0
0
0
0
1
1
B
0
0
0
0
1
1
1
1
0
0
C
0
0
1
1
0
0
1
1
0
0
output
D
0
1
0
1
0
1
0
1
0
1
W
1
1
0
0
0
0
0
0
0
0
X
0
0
1
1
1
1
0
0
0
0
Y
0
0
1
1
0
0
1
1
0
0
Z
1
0
1
0
1
0
1
0
1
0
w=m0+m1
x=m2+m3+m4+m5
y=m2+m3+m6+m7
z=m0+m2+m4+m6+m8
Q
...
4
Show that the dual of EX-OR is also its complement
...
A'+A
...
B'+B
...
Explain with the help of an example, the use of hamming code as error detection
and correction code
...
The bit positions are numbered from l to (n + k) from left to
right
...
The
remaining bits are data bits
...
For n = 8,
k = 4, therefore n+k =12
Bit position:
1
2
3
4
5
6
7
8
9
10
11
12
p1
p3
1
0
0
p4
0
1
0
0
p2
1
The 4 parity bits, p1, p2 p3 and p4 are in position 1, 2, 4 and 8 respectively
...
Each parity bit is calculated as follows:P1 = XOR of bits (3
...
the four check bits are so generated as follows Cl = XOR of bits {l, 3, 5, 7, 9, 11}
C2 = XOR of bits {2, 3, 6, 7, 10, 11}
C4 = XOR of bits {4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
If the result C = C8 C4 C2 C 1 = 0000, it indicates there is no error in received data
...
Consider the following three
cases for error detection:Received data
Bit
1 2 3 4 5 6 7 8 9 10 11 12
C8 C4 C2 C1
Remarks
Position
A
0011100101 0 0
0
0 0 0
No error
Error in bit position
B
1011100101 0 1
0
0 0 1
1
Error in bit position
C
0011000101 0 0
0
1 0 1
5
The error can be corrected by complementing the bit in the position as dictated by
C8 C4 C2 C1
...
15
AC07/AT07
Q
...
(6)
Ans:
A register that can shift the data in both directions and has the capacity of parallel
load is called Universal shift register
...
It can work as serial in parallel out, serial in serial out, parallel in
parallel out and parallel in serial out fashion
...
The two select in puts SO, Sl
select one of the multiplexer data input for the DFF’s
...
This condition forms a
path from the output of each FF into the input of the same FF
...
When S 1 SO = 01, this cases a shift right operation
...
If we want that the data stored in register should rotate right, then
the output A3 can be connected to the serial input (Shift Right)
...
Here also in order to rotate the
data in left direction by one bit with each clock pulse, the output AO can be
connected to serial input (Shift Left) terminal
...
Further, the output of the register can also be available at AO, Al, A2 and A3 lines
...
Q
...
How is it detected?
(3)
Ans:
Overflow may occur when two n-bits number of same sign are added or when two
n-bit I the time of the numbers of different sign are subtracted
...
For Example:+70-----01000110
+80----- 01010000
+150----- 10010110
Here the result of addition is in 8-bit only, but as +150 is out of the range that a
number can be represented by 8-bit signed 2's Compliment form
...
Now
-70 2's
-———-»
-80 2's
...
An overflow condition can be detected by observing the carry in to the sign bit
position and the carry out of sign bit position
...
If these two carries applied to an XOR gate, an overflow will
be detected when the output of the gate is equal to 1
...
7
Implement the following RTL code, using common bus and tri-state buffers
...
(6)
Ans:
The hardware realisation of R
...
All the FFs get the same clock pulse
...
Q
...
(3+4)
Ans:
Program control type instructions, when executed by the processor, may change the
address value of the Program Counter and cause type flow of control to be altered
...
This causes break in the sequence of instruction execution
...
Examples - Branch
...
Status bits are set or reset depending on the result of a logical or arithmetic
manipulation of accumulator data
...
These status bits constitute status register
...
if the end carry c8 is 1
...
It is set zero, if
thebitF7=0
(iii) Bit ‘z’(zero) is set to 1
...
Otherwise
it is set to zero
...
e
...
This is the condition for an
overflow when negative numbers are in 2's complement form
...
9
What are interrupts? Explain different types of interrupts
...
These are (i) External Interrupt: interrupt signal came from input-output devices
connected external to processor
...
The examples
that causes external Interrupt are - I/0 device requesting transfer of data, elapsed
time of an event, power failure
...
(ii) Internal Interrupt: Cause due to illegal or erroneous use of an instruction or
data
...
Internal interrupts are initiated due to
some exceptional condition caused by the program itself rather than by an external
event
...
Example of cause of internal interrupts are - attempt to divide by zero,
stack overflow, Invalid opcode, protection violation etc
...
These are
special call instructions that behaves like an interrupt rather than subroutine call
...
These interrupts arc usually used for switching to
supervisor made from user mode
...
10
How stack is implemented in a general microprocessor system
...
In some microprocessor,
register stack is provided
...
These two flags are known as EMPTY flag &
FULL flag
...
Full flag is
set only when all the stack locations are filled with data
...
Stacks operate in two principles
(1) LIFO i
...
Last in First Out
(2) FIFO i
...
first in first out
...
Most of general
purpose processor use LIFO principle for their stack
...
The memory stack grow down word i
...
with each Push
operations, stack pointer is decremented
...
Q
...
This binary format is very difficult to use and to –
troubleshoot
...
The assembler
converts these assembly language programs to binary form
...
It is easy to
troubleshoot, it is fast to execute than high level language program
...
Users must conform to all
format rules of the assembly language if it is to be translated correctly
...
The assembly language use
predefined rules that specify the symbols that can be used & how they may be
combined to form a line of code
...
(ii) The instruction field specify a machine instruction or a Pseudo instructions
...
(iv) The symbolic address consists of up to four alphanumeric characters
...
(vi) The comment field is preceded by a slash foe assembler to recognize the
beginning of a comment field
...
12
What is vertical micro code? State the design strategy of a vertical micro coded
control unit
...
Each microoperation is assigned a unique encoded value in this field
...
e
...
Vertical micro instructions require fewer bits
than their equivalent horizontal micro instructions, however the micro sequencer
incorporate a decoder for each microoperation field to generate the actual microoperation signals
...
(i)
Include NOP in each field if necessary
...
(iii)
Group together micro-operation that modify the same registers in the same
field
...
13
What is a microprogram sequencer? With block diagram, explain the working of
microprogram sequencer
...
When the control signals are generated by hardware using
conventional logic design techniques, the control unit is said to be hard wired
...
The control function that specifies
microoperation is a binary variable
...
A sequence of microinstructions
constitutes a microprogram
...
These microinstructions generates the
microoperations to fetch the instruction from main memory, to evaluate the effective
address, to execute the operation specified by the instruction and to return control to
the fetch phase, in order to repeat the cycle for new instruction
...
The micro instruction contains a control word that specifics one or more
micro operations for the data processes
...
The location of the next microinstruction
may be the one next in sequence or it may be located somewhere else in the control
memory
...
The
next address may also be a function of external input condition
...
The typical functions of
a micro program sequencer are
(i)
Incrementing the control address registers by one
...
The sequencer should also have a facility for subroutine call and return
...
14
Give the flow chart for add and subtract operation of two signed 2's complement
data
...
(4+6)
Ans:
22
AC07/AT07
Computer Architecture
In signed 2’s complement representation, the left most bit of a binary number
represents the sign bit
...
If the sign bit is 1, the entire
number is represented in 2’s complement form
...
A carry out of
the sign bit position is discarded
...
A carry out of the sign bit position is
discarded
...
-35-(+40) = 11011101
11011000
10110101
The overflow carry is neglected
...
Q
...
(6)
Ans:
To establish the priority of simultaneous interrupts can be done by software or
hardware
...
It is used for identifying the
highest-priority source by executing a program
...
The programme polls the interrupt sources in
sequence
...
Thus the initial service routine for all interrupts consist of a program that
tests the interrupts sources in sequence and to branch to one of many possible
service routines
...
These are
(i) Daisy- chaining priority and (ii) Parallel priority interrupts
...
The parallel priority interrupt method uses a register whose bits are set separately by
the interrupt signal from each device
...
In addition to the interrupt register, the circuit
may include a mask register whose purpose is to control the status of each interrupt
request
...
It can also provide a facility that
allows a high priority device to interrupt the CPU, while a lower priority device is
being serviced
...
24
AC07/AT07
Computer Architecture
in the interrupt register, individual bits are set by internal I/O device requesting the
service of CPU and is cleared by program instructions
...
For example magnetic disk may get higher priority than a printer
...
of bits as that of interrupt register
...
If it is 1, then the
associated interrupt is recognized, otherwise it is treated to be masked
...
In this way the interrupts are recognized by CPU
...
(ISR), which is to be loaded in
to PC for execution of ISR during interrupt cycle
...
When an interrupt is recognized, the
interrupt enable FF(IEN) can be set or cleared by the program to provide an overall
control over the interrupt system
...
If IST= 1 & IEN = 1, then the interrupt signal goes to CPU, in return
CPU sends interrupt acknowledgement signal, which enables the vector address
register to place the vector address of ISR into program computer
...
16
Give the hardware organization of associative memory
...
Deduce the logic equation used to find the match in the
associative memory
...
(3+2+5)
Ans:
The hardware organization of the cell of one word in associative memory including
the read and write logic is shown below:-
This consists of a memory array of logic for 'M' words with n-bits per word
...
The key register K, each has n-bits, one for each bit of a word
...
Each word in the
memory is compared in parallel with the content of the argument register
...
After the matching process, those bits in the match register that have been set indicate
25
AC07/AT07
Computer Architecture
the fact that their corresponding words have been matched
...
Let A1, A2
...
Kn are
n- bits of key register
...
The output of comparison of each bit in a particular row i is given by xj
...
As there is one bit in match register for
each word
...
(xn + kn')
n
Mi = Π ( Aj + Fij + Aj ' Fij '+ Kj ')
j =1
As xj = AjFij+Aj’Fij’
The circuit for match for one word of associative memory is given below-
Q
...
Explain different ways of
organizing a page table
...
e
...
So programs and data are transferred to and from auxiliary
memory and main memory based on demand imposed by the CPU
...
To obtain the actual main memory address of the data from its virtual
memory address
...
Further, each
word of page table also has ‘presence bit’ to donate whether this page is presently
available in main memory or not
...
But it is inefficient
w
...
t
...
(ii)
By using associative logic: It is more efficient way to organize the page
table, as it can be constructed with no
...
of blocks in main
memory
...
18
Design a sequential circuit with JK flip-flop to satisfy the following state
equations
...
Q
...
F (A,B, C, D) = m ( 1, 3, 7,11,15) + d(0,2,5)
Ans
...
20
Computer Architecture
Explain the Adder-Subtractor with the help of 2's complement
...
The addition of two numbers in signed 2's complement form consists of adding the
numbers with the sign bits treated the same as the other bits of the number
...
The subtraction consists of first
taking the 2's complement of the subtrahend and then adding it to the minuend
...
+ 1 digits then an overflow
occurred
...
When the two carries are applied to an exclusive OR gate, the overflow is
detected when, the output of the gate is equal to 1
...
The overflow bit V is set to 1 if the exclusive-OR of the last two carries is 1,
and it is cleared to 0 otherwise
...
Taking the 2's complement
of BR has the effect of changing a positive number to negative, and vice versa
...
The programmer must realized that if an overflow
occurs, there with be an erroneous result in the AC register
...
21
Design a combinational circuit using a ROM
...
28
AC07/AT07
Computer Architecture
Ans
...
For this type of circuit, we need six bits of output
...
22
Computer Architecture
Represent microinstructions for a microprogram of LD r1, (r2) instruction at
control memory addresses aj to aj+5
...
(ZDR = 1 if DR = 0 ; ZAC = 1 if AC = 0)
INR (PC) = R' T1 + RT2 + D6 T6 ZDR + PB9 (FGI) + PB8 (FGO)
+ rB4 (AC15) ' rB3 (AC15) + rB2 ZAC +RB1 E'
LD (PC) = D4 T4 + D5 T5
CLR (PC) = RT1
...
23
Evaluate the arithmetic statement X = (A+B)*(C+D) using a general register
computer with three address, two address and one address instruction format
Ans
...
The program in assembly
language that evaluates X = evaluates X = (A+B) * (C+D) is shown below, together
with comments that explain the register transfer operation of each instruction
...
It is assumed that the computer has two processor registers, R1and R2
...
Two-Address Instructions
30
AC07/AT07
Computer Architecture
Two-address instructions are the most common in commercial computers
...
The program to evaluate X = (A +B) * (C + D) is as follows:
MOV
R1, A
R1 <-M[A]
ADD
R1, B
R1 <-R1 + M[B]
MOV
R2, C
R2 <-M[C]
ADD
R2, D
R2<- R2 + M[D]
MUL
R1, R2
R1 <-R1 * R2
MOV
X, R1
M[X] <- R1
The MOV instruction moves or transfers the operands to and form memory and
processor registers
...
For multiplication and division there is a need for a second
register
...
The program to evaluate
X = (A + B) * (C + D) is
LOAD
A
AC <-M[A}
ADD
B
AC<-A[C] + M[B]
STORE
T
M[T] <-AC
LOAD
C
AC<-M[C]
ADD
D
AC<-AC+M[D]
MUL
T
AC<-AC * M[T]
STORE
X
M[X] <-AC
Q
...
Ans
...
Address for count
in H-L pair
...
Yes, next digit in
accumulator go to
AHEAD
Decrement Court
...
2003
21,0025
LXI
H12500H
2006
46
MOV
B 1M
2007
2008
21,0025
DA, 14,20
LOOP
INX
JC
H
AHEAD
2009
2010
00
12
AHEAD
DCR
STAX
C
D
Q
...
Give an example of
multiplicant and multiplier for which this algorithm takes the maximum time
...
The hardware implementation of Booth algorithm requires the register configuration
shown
...
Registers A, B,
and Q, as AC, BR, and QR, respectively
...
An extra flip-flop Qn+1 is appended to QR to
facilitate a double bit inspection of the multiplier
...
Hardware for Booth algorithm
BR register
Sequence counter (SC)
Complementer and
parallel adder
Qn
AC register
QR register
32
Qn+1
AC07/AT07
Computer Architecture
Example: Refer table 10-3 from page 348, Morris mano (3rd Edition)
Q
...
(i) - 35 + (-11)
(ii)
19 - (- 4)
Ans
...
27
Consider a cache (M1) and memory (M2) hierarchy with the following
characteristics:
M1 : 16 K words, 50 ns access time
M2 : 1 M words, 400 ns access time
Assume 8 words cache blocks and a set size of 256 words with set associative
mapping
...
(ii)Calculate the Effective Memory Access time with a cache
hit ratio of h =
...
Ans
...
= 220 words
...
220
main memory =
= 217 blocks
8
Cache memory = 16 k words
...
8
2
Set size = 265 words
...
(ii)
Given, tc = 50ns tm = 400 ns
h= 0
...
95 x 50 + ( 1-0
...
5 + 22
...
28
Write short notes on the following:
(i) Flip-Flops
...
Ans
...
A flip-flop is capable of
storing 1 bit of binary data
...
The output
stays low or high, to change it, the circuit must be drived by an input called trigger
...
Edge Triggered Flip-flops:- An edge triggered flip-flop responds only during the
brief instant the clock switches from one voltage level to another
...
Sometimes, triggering on the negative edge is better suited to the
application
...
This is called negative-edge triggering
...
To get some computers started, an operator has to push a reset button
...
Also, it is necessary in some digital
system to PRESET (synonymous with set) certain flip-flops
...
Types of Flip-flops
1)R-S
...
4)J-K Flip-Flop
5)Master-Slave Flip-Flop
6)T-Flip-Flop
(ii) Multiplexer
The multiplexer (MUX) is a combinational logic circuit that selects binary
information from one of the multiple input lines (Dn-1
...
S1 S0) and directs
it
...
it's truth table given
below
...
29
Implement the following by using 4:1 multiplexer
P = Π(M0, M1, M5, M7)
...
A
I0
1
I1
0
I2
I3
4x1
MUX
B
C
B and C are the selection lines
...
30
Computer Architecture
Explain with neat flow chart the addition and subtraction of floating point
numbers
...
The
sum or difference is formed in AC
...
Flow Chart
(1)
Check for zeros
...
The flowchart for adding or subtracting two floating point binary numbers is shown
in fig
...
If AC is equal to zero, we transfer the content of BR into AC and
also complement its sign if the numbers are to be subtracted
...
The magnitude comparator attached to exponents a and b provides three outputs that
indicate their relative magnitude
...
If the exponents are not equal, the mantissa having the smaller
exponent is shifted to the right and its exponent incremented
...
Q
...
table of the multiplication
...
Binary equivalent of 7 = 0111, -7 = 1001
Binary equivalent of 3 = 0011
...
32
AC
QR
Qn+1
0000
0011
0111
0111
ashr
0011
1001
ashr
0001
1100
Add BR
1001
1010
ashr
1101
0110
ashr
1110
1011
Final product = 11101011
0
SE
0
100
1
1
011
010
0
0
001
000
Design a hardware circuit by using common bus architecture to implement the
following Register Transfer Languages
...
33
Input
S1
0
0
1
1
0
X
X
X
X
S1
0
1
0
1
0
X
X
X
X
Output
P
Q
R
S1
]S
S2
X
X
X
X
Explain hardware polling method for data transfer
...
In a bus system that uses polling, the bus grant signal is replaced by a set of lines
called poll lines which are connected to all units
...
The bus
controller sequences through the addresses in a prescribed manner
...
After number of bus cycles, the polling process continues
by choosing a different processor
...
There are so many ways to boot alternative OSs to common PCs these days
...
Below we count the pros & cons of the three most popular methods: repartitioning, emulation and virtualization
...
Partitioning
With the re-partitioning method the user must manually re-partition his hard drive
and then install the OSs one after the other on the right partition and then use a
boot manager to boot between OSs
...
Virtualization
Virtualization is the new kid on the block and it’s gaining ground very fast
...
The virtualizer “shares” more hardware resources with the
host OS than an emulator does
...
Emulation
Emulators will completely emulate the target CPU and hardware (e
...
sound
cards, graphics cards, etc)
...
Emulation on PCs these days is only good for
non-OS usages (e
...
game consoles, embedded systems) or specific OS/CPU
development purposes
...
Tell us what’s your preferred method is below
Q
...
Ans
...
The first word of the instruction specifies the operation code and mode, and the
second word specifies the address part
...
The content of processor register R1 is 400, and the content of an index
register XR is 100
...
The
figure lists a few pertinent addresses and shows the memory content at each of these
addresses for each possible mode
...
In the direct address mode the effective
address is the address part of the instruction 500 and the operand to be loaded into
AC is 800
...
In the indirect mode the
effective address is stored in memory at address 500
...
In the Index mode the effective address is
XR + 500 = 100 + 500 = 600 and the operand is 900
...
The Autoincrement mode is the same as the register indirect mode except that R1 is
incremented to 401 after the execution of the instruction
...
In the relative mode
the effective address is 500+202=702 and the operand is 325
...
39
AC07/AT07
Q
...
Ans
...
Priority is established according to the
position of the bits in the register
...
The
mask register can be programmed to disable low priority interrupts while a higher
priority device is being carried
...
Each
interrupt bit and its corresponding mask bit are applied to an AND get to produce
the four inputs to a priority encoder
...
40
AC07/AT07
Computer Architecture
Interrupt Cycle:The interrupt enable flip-flop IEN shown it can be set or cleared by program
instructions
...
The program-controlled IEN bit allows the programmer to
choose whether to use the interrupt facility
...
An instruction to set IEN indicates that the interrupt facility will be
used while the current program is running
...
At the end of each instruction cycle the CPU checks IEN and the
interrupt signal from IST
...
If both IEN and IST are equal to 1, the CPU goes to an interrupt cycle
...
The CPU pushes the return address from PC into the stack
...
The priority interrupt unit
responds by placing a unique interrupt vector into the CPU data bus
...
The instruction read from memory during the next fetch phase will be the
one located at the vector address
...
36
Compare assembly language with high level language
...
If the given number is even then display '1' on its SOD line
...
Ans
...
37
Computer Architecture
Compare horizontal microcode with vertical microcode
...
(6)
Ans
...
(3) Lots of signals many bits in
micro-instruction
Vertical Micro-code
(1) Each action encoded density
...
(3) Takes less space but may be slower
...
There should be no need for further hardware or
wiring changes
...
Q
...
Compare them
...
Three types of mapping procedures used for cache memory:
(i)
Associative mapping
(ii)
Direct mapping
(iii)
Set-associative mapping
(i)
Associative mapping:The fastest and most flexible cache organization uses an associative memory
...
The associative memory stores both the address and
content (data) of the memory word
...
The diagram shows three words presently stored in the
cache
...
A CPU address of
15 bits is placed in the argument register and the associative memory is searched for
a matching address
...
If no match occurs, the main memory is accessed for the word
...
If the
cache is full, an address-data pair must be displaced to make room for a pair that is
needed and not presently in the cache
...
A simple procedure is to replace cells of the cache is round-robin order whenever a
43
AC07/AT07
Computer Architecture
new word is requested from main memory
...
Fig
...
The possibility of using a randomaccess memory for the cache is investigated
...
The nine least significant bits constitute the index field and the
remaining six bits form the tag field
...
The number of bits in the
index field is equal to the number of address bits required to access the cache
memory
...
The n bit memory address is divided into two fields: k bits for the
index field and the n-k bits for the tag field
...
The direct mapping cache organization uses the nbit address to access the main memory and the k-bit index to access the cache
...
Each word in
cache consists of the data word and its associated tag
...
When the CPU
generates a memory request, the index field is used for the address to access that
cache
...
If the two tags match, there is a hit and the desired data word is in
cache
...
It is then stored in the cache together with the new tag, replacing the
previous value
...
However, this possibility is minimized by the
fact that such words are relatively far apart in the address range
...
The word at address zero is presently stored in the cache (index = 000, tag =
00, data = 1220)
...
The index address is 000, so it is used to access the cache
...
The cache tag is 00 but the address tag is 02, which does not produce
a match
...
The cache word at index address 000 is then replaced with a
tag of 02 and data of 5670
...
The same
organization but using a block size of 8 words is shown
...
In a
512-word cache there are 64 blocks of 8 words cache, since 64 x 8 = 512
...
The tag field stored within the cache is common to all eight
words of the same block
...
Although this takes extra
45
AC07/AT07
Computer Architecture
time, the hit ratio will most likely improve with a larger block size because
sequential nature of computer programs
...
A third type of cache organization, called
set-associative mapping, is an improvement over the direct-mapping organization in
that each word of cache can stored two or more words of memory under the same
index address
...
An example of a setassociative cache organization for a set size of two is shown
...
Each tag requires six bits and
each data words has 12 bits, so the word length is 2(6+12) = 36 bits
...
Thus the size of cache memory is
512 x 36
...
In general, a set-associative cache of set size k will
accommodate k words of main memory in each word of cache
...
The words stored at addresses 01000 and 02000 of main memory are
stored in cache memory at index address 000
...
When the CPU generates
a memory request, the index value of the address is used to access the cache
...
The comparison logic is done by an associative search
of the tags in the set similar to an associative memory search: thus the name "setassociative
...
However, an increase in the set size
increases the number of bits in words of cache and requires more complex
comparison logic
...
The most
common replacement algorithms used are: random replacement, first-in, first-out
(FIFO), and least recently used (LRU)
...
The FIFO procedure
selects for replacement the item that has been in the set the longest
...
Both FIFO and LRU can be implemented by adding a few extra bits in each
word of cache
...
39
State how different policies of writing into cache are implemented
...
The simplest and most commonly used procedure is to update main memory with
every memory write operation, with cache memory being updated in parallel if it
contains the word at the specified address
...
This method has the advantage that main memory always contains the same data as
the cache
...
It ensures that the data residing in main memory are valid at all times so
that an I/O device communicating through DMA would receive the most recent
updated data
...
In this method
only the cache location is updated during a write operation
...
The reason for the write-back method is that during the time a
word resides to the cache, it may be updated several times; however, as long as the
word remains in the cache, it does not matter whether the copy in main memory is
out of date, since requests from the word are filled from the cache
...
47
AC07/AT07
Q
...
State your design specifications
...
In computer systems a number of storage registers connected to a common
operational unit called an arithmetic logic unit (ALU)
...
The
ALU performs an operation and the result of the operation is then transferred to a
destination register
...
The shift micro-operation
are often performed in a separate unit, but sometimes the shift unit is made part of
the overall ALU
...
One stage of an arithmetic logic and shift
unit is shown in fig
...
41
Input Ai and Bi are applied to both the arithmetic and logic units
...
A 4x1 MUX at the output chooses between an arithmetic output in Di and a
logic output in Ei
...
The other two data inputs to the MUX receive inputs Ai-1 for the shift right
operation and Ai+1 for the shift left operation
...
The circuit provides eight arithmetic operation, four logic operations and
two shift operations
...
The table lists the 14 operations of the ALU
...
The next four are logic operation
and are selected with S3 S2 = 01 and last two operation are shift operation
and are selected with
S3 S2 = 10 and 11
...
Ans
...
When the CPU fetches and decodes the operation code of an
input or output instruction, it places the address associated with the instruction into
the common address lines
...
When the CPU is fetching an instruction or an operand from memory,
it places the memory address on the address lines and enables the memory read or
memory write control line
...
Memory Mapped I/O :- In computers that employ only one set of read and write
signals and do not distinguish between memory and I/O addresses
...
In a memory-mapped I/O
organization there are no specific input or output instructions
...
The advantage is that the load and store
instructions used for reading and writing from memory can be used to input and
output data from I/O registers
...
42
Write short notes on:(i) Sequential circuit
...
(iii) Virtual memory
...
Ans
...
The gates by
themselves constitute a combinational circuit, but when included with the flip-flops,
the overall circuit is classified as a sequential circuit
...
It consists of a combinational
circuit and a number of clocked flip-flops
...
In the diagram, the combinational circuit block receives
binary signals from external inputs and from the outputs of flip-flops
...
The outputs of flip-flops, in turn, are applied to the
combinational circuit inputs and determine the circuit’s behavior
...
Thus a
sequential circuit is specified by a time sequence of external inputs, external outputs,
and internal flip-flop binary states
...
The logic of the priority encoder is such that if two or more inputs arrive
at the same time, the input having the highest priority will take precedence
...
The X’s in the
table designate don’t care conditions
...
I1 has the next priority level
...
The output for I2 is
generated only if higher-priority inputs are 0, and so on down the priority level
...
The interrupt
status IST is cleared to 0 and the other outputs of the encoder are not used, so they
are marked with don’t-care conditions
...
The output of the priority encoder is used to
form part of the vector address for each interrupt source
...
Inputs
I2 I3
X X
X X
I0
1
0
I1
X
1
0
0
1
0
0
0
0
Output
IST
1
1
Boolean function
X
0
0
Y
0
1
X
1
0
1
y=I'0 I1 +I'0 I'2
0
1
1
1
1
(IST)=I0 +I1 +I2 +I3
0
0
X
X
0
'
x=I'0 I1
(iii)
Virtual memory:- Virtual memory is a concept used in some large
computer that permit the user to construct programs as through a large memory
space were available, equal to the totality of auxiliary memory
...
A
virtual memory system provides a mechanism for translating program generated
addresses into correct main memory locations
...
The address field of the instruction code has a sufficient
number of bits to specify all virtual address
...
Thus CPU will reference instructions and data with a
20-bit address, but the information at this address must be taken from physical
memory because access to auxiliary storage for individual words will be
prohibitively long
...
51
AC07/AT07
Computer Architecture
(iv)
Program Control Instruction: – A program control type of instruction,
when executed, may change the address value in the program counter and cause the
flow of control to be altered
...
Some
typical program control instructions are list in table below
...
It is written in
assembly language as BR ADR, where ADR is a symbolic name for an address
...
An
unconditional branch instruction causes a branch to the specified address without
any condition
...
If the condition is meet, the program counter is
loaded with the branch address and the next instruction is taken from this address
...
A conditional skip instruction will skip the next instruction if the
condition is met
...
The call and return instruction are used in conjunction with
subroutines
...
The compare instruction performs a subtraction between two operands, the
result of the operation is not retained
...
Q
...
How does it work in
mapping the virtual address into Physical memory address?
(7)
Ans
...
A main memory address is called a
location or physical address and set of such locations are called memory space or
physical address space
...
Consider a computer of main – memory capacity of 32 K words
...
Suppose the computer has
available auxiliary memory for strong 220 words
...
Thus, N = 1024K and M=32K
...
Thus, the CPU will reference
instructions and data with 20- bit addresses, but the information at this address must
be taken from physical memory rather than auxiliary memory
...
For this a memory
mapping table is needed which is shown in the fig
...
This mapping is a
dynamic operation and every address is translated immediately as a word is
referenced by CPU
...
Address mapping can be further simplified if the information in address space and
memory space can be divided into groups of equal size
...
These blocks can range from 64 to 4096 words
...
Consider a computer with
an address space of 8K and memory space of 4K
...
This division of address space and memory space is
shown in figure
...
In a computer with 2p words per page, p bits are
used for line-address and remaining high- order bits of the virtual address specify
page number
...
Each page consists of 1K words i
...
210 words
...
The line address in address space and memory space is same and hence only
mapping required is from a page number to a block number
...
The memory page table
consists of eight words
...
Thus this shows that
pages 0, 2, 4 and 6 are stored in main memory in blocks 2, 3, 1 and 0, respectively
...
If presence bit is 1
the page is available in main memory and if it is 0 the page is not available in main
54
AC07/AT07
Computer Architecture
memory
...
Then the content of
the word at this address is read-out into the memory table buffer register along with the
presence bit
...
A read signal thus transfers the content
to the main memory buffer register, to be used by the CPU
...
Then a call
to operating system is generated to fetch the required page from auxiliary memory to
main memory before resuming computation
...
44
A Virtual memory has a Page Size of 1K words
...
The associative memory page table contains the following entries
...
Ans
...
45
How LRU technique is implemented
? (3)
Ans
...
The LRU algorithm can be implemented by associating a
counter with every page that is in the main memory
...
At fixed interval of time, the counters associated
with all pages presently in memory are incremented by 1
...
The counters are often called aging
registers, as their count indicates their age, that is how long ago their associated
pages have been referenced
...
46
What is cycle stealing DMA operation?
55
(3)
AC07/AT07
Computer Architecture
Ans
...
The CPU merely
delays its operation for one memory cycle to allow the direct memory input/output
transfer to ‘Steal’ one memory cycle
...
47
What do you understand by the term micro-operation
...
Show the hardware realization of decrement
micro-operation
...
e
...
A miocrooperation is an elementary operation performed with the data stored in
registers
...
A microoperation is an elementary operation performed on the
information stored in one or more registers
...
Examples are clear, shift, count, load etc
...
The microoperations must often encounter in digital computers are classified into
following categories:
Register transfer microoperations transfer binary information from one
(1)
register to another
...
(3)
Logic microoperations perform bit manipulation operations on non numeric
data stored in registers
...
(4)
The register transfer microoperation does not change the information content when
the binary information moves from source register to destination register
...
The basic arithmetic microoperations are addition,
subtraction, increment, decrement and shift
...
It states that add the content of register R1 and that
of register R2 and stored the result in register R3
...
Subtraction is basically implemented through complementation and addition and can
be specified by the statement
R A+B’+1
where B’ is the 1’s complement of B
...
The increment and decrement microoperations are implemented with the
help of combinational circuit or with a binary up-down counter
...
56
AC07/AT07
Computer Architecture
The multiplication operation and division are valid arithmetic operations
...
Hardware realization of decrement microoperation
T1: X
X -1
Q
...
Determine the operand ‘B’
and the logic micro-operation to be performed in order to change the value of ‘A’ to
(i) 01101101
(ii) 11111101
(4)
Ans
...
49
Give the flow chart of division of two signed magnitude data
...
Ans
...
The sign of the result is transferred
into Qs to be part of the quotient
...
Since an operand must be stored with its sign,
one bit of the word will be occupied by the sign and the magnitude will consist of n1 bits
...
If A ≥ B, the divide overflow flip flop DVF is
set and the operation is terminated prematurely
...
57
AC07/AT07
Computer Architecture
The division of the magnitudes starts by shifting the dividend in AQ to the left with
the high order bit shifted into E
...
In this case B
must be subtracted from EA and 1 inserted into Qn for the quotient bit
...
Adding to this value the 2’s complement of B results in
(EA-2n-1 )+(2n-1 -B)=EA-B
The carry from this addition is not transferred to E if we want E to remain a 1
...
If E = 1, it signifies that
A ≥ B ; therefore Qn is set to 1
...
This process is repeated again and again with register
A holding the partial remainder
...
The quotient sign is in QS and
the sign of the remainder in AS is the same as the original sign of the dividend
...
50
Convert the following arithmetic expression from reverse polish notation to infix
notation:
ABXYZ+*–/
Write a program using three address instruction to evaluate the same
...
The given expression is ABXYZ + * - /
ABXYZ + * - / = A / (BXYZ+*-)
= A / [B-(XYZ+*)]
59
AC07/AT07
Computer Architecture
= A / [B-{X*(YZ+)}]
= A / [B – {X* (Y+Z)}]
The arithmetic expression is
δ = A / { X *(Y + Z )}]
PROGRAM USING THREE ADDRESS INSTRUCTIONS
ADD R1, Y, Z R1 M[Y]+M[Z]
MUL R1, X, R1 R1 M[X] * R1
SUB R1, B, R1 R1 M[B]-R1
DIV δ , A, R1 M[ δ ] M[A] / R1
Q
...
(8)
Ans
...
The word interrupt is used from any exceptional event that causes the CPU to
temporarily transfer the control from its current program to another program, an
interrupt handler which will service the interrupt
...
Interrupts are the primary means by which input/
output devices obtain the services of the CPU
...
Input output interrupts are external requests to
the CPU to initiate or terminate an input output operation, such as data transfer with
a hard disk
...
An attempt by an
instruction to divide by 0 is an example of software generated interrupt
...
The interrupt is initiated by a signal generated by an external devices or a signal
generated externally by the CPU
...
The interrupt generated by special instructions are called software interrupts and
they are used to implement system services
...
Hardware interrupt is a type of interrupt generated either externally by the hardware
devices such as input output ports, key board, and disk drives etc or internally by the
microprocessor
...
Internal hardware interrupts are generated by the CPU to
control events
...
These instructions are inserted at
desired location in a program
...
While
running a program, if software interrupt instruction is encountered the CPU initiates
60
AC07/AT07
Computer Architecture
an interrupt
...
When interrupt signal is generated the CPU responds to the interrupt signal by
storing the return address from program counter into memory stack and then control
is transfer or branches to the service routine that processes the interrupt
...
One is called vectored interrupt and the other is called non-vectored interrupt
...
In vectored interrupt, the source that initiated the interrupt supplies the
branch information
...
In certain situations it may be desired that some of the several interrupts should not
occur while CPU is busy in performing some important task
...
The interrupt that can be masked off is called maskable interrupt
...
They remain pending
...
Certain interrupts have to be serviced without delay; else something serious damage
may be caused to program, data or results
...
Such interrupts are known as
non-maskable interrupts and CPU does not mask (ignore) them
...
Q
...
(4)
Ans
...
The most common fields found in the instruction are:(i)
An operation code field that specifies the operation to be performed
...
(ii)
An address field that designates the registers address and/or a memory
addresses
...
For example,
ADD R1, R0, ADD is the opcode and R1, R0 are the address field
...
Operands residing on memory are specified by register address
...
The number of address fields in the instruction format of a computer
system depends on the internal architecture/organization of registers
...
53
The 8-bit registers A, B, C & D are loaded with the value (F2) H, (FF) H,
(B9) H and (EA)H respectively
...
(i) A ← A + B, C ← C + Shl(D)
(ii) C ← C ^ D, B ← B + 1
...
(iv) A ← Shr(B) ⊕ Cir(D)
(8)
61
AC07/AT07
Computer Architecture
Ans
...
C C ^ D, B B+1
C ^ D = 10001101
^11010100
-------------10000100 = (84)H
B+1 = 11111111
+
1
---------------00000000 = (00)H
After these microoperations the content of A, B, C, and D are (F1)H, (00)H, (84)H
and (D4)H respectively
...
(iii)
(iv)
A shr(B) ⊕ Cir(D)
shr(B) = shr(00000000) = 00000000 = (00)H
Cir(D) = Cir (11010100) = (01101010) = (6A) H
shr(B) ⊕ Cir(D) = 00000000
⊕ 01101010
---------------01101010 = (6A)H
After this microoperation, the content of A, B, C, and D are (6A)H, (00)H, (84)H and
(6A)H respectively
...
54 Design a synchronous self starting counter using S-R flip flops for counter the
sequence 0, 2, 3, 5, 8, 7, 15, 12, 11, 10 & repeat
...
Excitation table for counter using S-R Flip Flop
A
0
0
0
0
1
0
1
1
1
1
B
0
0
0
1
0
1
1
1
0
0
C
0
1
1
0
0
1
1
0
1
1
D
0
0
1
1
0
1
1
0
1
0
SA
0
0
0
1
0
1
x
x
x
0
RA
x
x
x
0
1
0
0
0
0
1
SB
0
0
1
0
1
x
x
0
0
0
The K – maps are as follows:-
63
RB
x
x
0
1
0
0
0
1
x
x
SC
1
x
0
0
1
x
0
1
x
0
RC
0
0
1
x
0
0
1
0
0
1
SD
0
1
x
0
1
x
0
1
0
0
RD
X
0
0
1
0
0
1
0
1
x
AC07/AT07
Computer Architecture
64
AC07/AT07
Computer Architecture
Given, f ( b, a, c ) = Σm (1,3,5,6,7,11,13,14 ) and don’t care M4, M9, M10
65
AC07/AT07
Q
...
When x = 0, the state of the flip-flop does not change
...
01
...
Ans
...
56
Design a combinational circuit with three inputs x, y, z and three outputs A, B, C
...
When the binary input is 4, 5, 6 and 7, the binary output is one less
than the input
...
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
A
0
0
1
1
0
1
1
1
66
B
1
1
0
0
1
0
0
1
C
0
1
0
1
1
0
1
0
AC07/AT07
Computer Architecture
67
AC07/AT07
Q
...
Express the Boolean expression is product of sum form and also
show the k-map for that product of sum form
...
Q
...
How many pains are needed for
the integrated circuit package of Draw a block diagram and label all input and
outputs pins of the RAM
...
RAM chip is of 4096 x 8
...
2 for enable lines and 8 bits for
outputs
...
MAIN MEMORY:The main memory is the central storage unit in a computer system
...
The principal technology used for the main memory is based on
semiconductor integrated circuits
...
The static RAM consists essentially of internal flip-flop that store the binary
information
...
The dynamic RAM stores the binary information in the form of electric
charges that are applied to capacitors
...
The stored charge on the capacitors tend to discharge with
time and the capacitors must be periodically recharged by refreshing the dynamic
memory
...
The dynamic RAM offers reduced power
consumption and large storage capacity in a single memory chip
...
Most of the main memory in a general-purpose computer is made up of RAM
integrated circuit chips, but a portion of the memory may be constructed with ROM
chips
...
RAM is used for storing the bulk of the
programs and data that are subject to change
...
Q
...
It’s enable-1 input is active when A15 and A14
bits are 0 & 1 and enable-2 input is active when A13 , A12 bits are ‘X’ and ‘O’
...
Ans
...
Q
...
Ans
...
61
B
0
0
1
1
0
0
1
1
P
0
1
0
1
0
1
0
1
Difference
0
1
1
0
1
0
0
1
Borrow
0
1
1
1
0
0
0
1
Derive the circuit for a 3-bit parity generator and 4-bit parity checker using an
even parity bit
...
62
Computer Architecture
What is microoperation? Give suitable examples of some four types of
microoperations
...
A microoperation is an elementary operation performed with the data stored in
registers
...
2) Arithmetic microoperations perform arithmetic operation on
numeric data stored in registers
...
4) Shift microoperation performs shit operation on data stored in
registers
...
63
Give the hardware realization of 4-bit arithmetic circuit capable of doing addition,
subtraction, increment, decrement etc
...
70
AC07/AT07
Ans
...
64
Computer Architecture
Cin
0
1
0
1
X
A
A
A
A
Y
B
0
1
B
(A+B)
(A+1)
(A-1)
(A-B)
Give the comparison between & examples of hardwired control unit and micro
programmed control unit
...
Comparison between Hardwired and microprogrammed control unit
Characteristics
Hardwired Control
Microprogrammed
Control
(1)
Speed
Fast
Slow
(2)
Implementation
Hardware
Software
(3)
Ability to handle Somewhat difficult
large/complex instruction
sets
(4)
Design process
(5)
memory
Difficult
for
operation
No memory used
(6)
Flexibility
No flexibility
71
Easier
more Easy
Control memory used
...
65
Computer Architecture
What do you mean by Fetch cycle, instruction cycle, machine cycle,
acknowledgement cycle
...
The execution of an instruction may itself involve a number of steps
...
The instruction fetch is a common fraction instruction from location is memory
...
The instruction cycle is referred to as the fetch cycle and execute
cycle
...
The output for I2 is generated only if higher-priority
inputs are 01 and on down the priority level
...
If all
inputs are I0 IST is cleared to 0 and the other outputs of the encoder are not used, so
they are marked with don't care conditions
...
The output of the priority encoder is used to form part of the vector, address for
each interrupt source
...
Interrupt Cycle:The interrupt enable flip-flop IEN shown in Fig
...
When IEN is cleared, the interrupt request coming from IST
is neglected by the CPU
...
If an instruction to clear IEN has been
inserted in the program, it means that the user does not want his program to be
interrupted
...
Most computers include internal
hardware that clears IEN to 0 every time an interrupt is acknowledged by the
processor
...
If either is equal to 0, control continues with the next instruction
...
During the interrupt
cycle the CPU performs the following sequence of microoperations:
SP
SP – 1
Decrement stack pointer
M [SP]
PC
Push PC into stack
INTACK
1
Enable interrupt acknowledge
PC
VAD
Transfer Vector address to PC
IEN
0
Disable further interrupts
72
AC07/AT07
Computer Architecture
The CPU pushes the return address from PC into the stack
...
The priority interrupt unit responds by
placing a unique interrupt vector into the CPU data bus
...
The
instruction read from memory during the next fetch phase will be the one located at
the vector address
...
66
Explain in brief how a digital computer system works in a interrupt driven
input-output programming
...
A computer can serve no useful purpose unless it communicates with the external
environment
...
Computational results must be transmitted to the user through some output
device
...
To
demonstrate the most basic requirements for input and output communication, we
will use as an illustration a terminal unit with a keyboard and printer
...
Each quantity of information
has eight bits of an alphanumeric code
...
These two registers communicate with a
communication interface serially and with the AC in parallel
...
The transmitter interface receives serial information from
the keyboard and transmits it to INPR
...
The input register INPR consists of
eight bits and holds alphanumeric input information
...
The flag bit is set to 1 when new information is available in the
input device and is cleared to 0 when the information is accepted by the computer
...
Initially, the output flag FGO is set to 1
...
The output device accepts the coded information, prints the corresponding character,
and when the operation is completed, it sets FGO to 1
...
Input-Output Instructions
...
Input-output instructions have an operation code 1111 and are
recognized by the control when D7 = 1 and I = 1
...
The control functions and microoperations for the
input-output instructions are listed
...
Each control function needs a Boolean
relation D71T3, which we designate for convenience by the symbol p
...
By assigning the symbol Bi to
bit i of IR, all control functions can be denoted by pBi for i=6 through 11
...
67
pB9: If (FGI=1) then (PC
pB6: IEN
1
interrupt enable on
0
interrupt enable off
Design a CPU that meets the following specifications:
It can access 64 words of memory, each word being 8-bit long
...
0] and reading in the 8-bit
value from memory on inputs D [7
...
It has one 8-bit accumulator, 8-bit
address register, 6-bit program counter, 2-bit instruction register, 8-bit data register
...
Instruction
AND
JMP
ADD
INC
Label
AND
Instruction
code
00AAAAAA
01AAAAAA
10AAAAAA
11xxxxxx
Microoperation
ORG 16
operation
AC
AC+M(AAAAAA)
Go to AAAAAA
AC
AC + M(AAAAAA)
AC
74
AC+1
CD
BR
AD
AC07/AT07
ANDOP
ADD
STORE
COMPLEMENT
Q
...
Software and hardware interrupt:
The software interrupts are program instructions
...
A program generated interrupt also called trap, which
stops current processing in order to request a service provided by the CPU
...
For example a program might generate a software interrupt to read
input from keyboard
...
External hardware interrupts are used
by device to request attention from CPU
...
Q
...
There are three major difficulties that cause the instruction pipeline to deviate form
its normal operation
...
Most of these conflicts can be resolved by using separate instruction and data
memories
...
3)
Branch difficulties arise from branch and other instructions that change the
value of PC
...
The compiler for such computer is designed to detect a data conflict and re order the
instructions, to delay the loading of the conflicting data by inserting no-operation
instructions
...
75
AC07/AT07
Q
...
Ans
...
For example reading a
character form the keyboard or saving a block of data to disk
...
They may be called up macros and many of the
most useful routines are available as operating system calls
...
A set of common instructions
that can be used in a program in called a subroutine
...
71
With neat block diagram explain the working of a microprogram sequencer
for control memory
...
Block Diagram of Micro program sequencer
The input logic circuit has three inputs I0, I1, and T, and three outputs, S0, S1, and L
...
Variable L
enables the load input in SBR
...
For example, with S1 S0 = 0, multiplexer
input number 2 is selected and establishes a transfer path from SBR to CAR
...
The truth table for the input logic circuit is shown
...
The bit values for S1and S0 are determined from the
stated function and the path in the multiplexer that establishes the required transfer
...
S1 = I1
S0 = I1 I0 + I’1 T
L = I’1 I0 T
Input Logic Truth Table for Microprogram Sequence
BR
Field
0
0
0
0
1
1
Q
...
State their merits and demerits
...
The function of a computer is to execute program
...
When we are referring to here is the execution
time sequence of instructions
...
Micro-operation - The prefix micro refers to the fact that each step is very simple
and accomplish very little
...
The performance
Program
execution
Instruction
cycle
Fetch
Instruction
cycle
Indirect
Execute
Instruction
cycle
Interrupt
Fetch
Indirect
of each sub cycle involves one or more shorter operations, that is micro-operations
...
77
AC07/AT07
Computer Architecture
The fetch cycle - The fetch cycle, which occurs at the beginning of each instruction
cycle and causes an instruction to be fetched from memory
...
There is one sequence each for the fetch, indirect and
interrupt cycle and for execute cycle, there is one sequence of micro-operations for
each opcode
...
73
With neat flow chart, explain the procedure for division of floating point numbers
carried out in a computer
...
In the restoring division method,
the divisor is subtracted from the dividend or partial remainder as many times as
necessary until a negative reminder results
...
The digit in the quotient reflects the number of subtractions
up to but excluding the one that caused the negative difference
...
It is similar to the algorithm with binary data except
for the way the quotient bits are formed
...
The divisor is then
subtracted by adding its 10's complement value
...
The carry in E determines the relative magnitude
of A and B, If E=0, it signifies that A
If E=1, it
signifies that A>B
...
This process is repeated until the subtraction results in a negative
difference which is recognized by E being 0
...
In this
way, the quotient digit is made equal to the number of times that the partial
remainder "goes" into the divisor
...
The remainder is then found in register A and the quotient is to register Q
...
Q
...
Ans
...
75
What do you mean by initialization of DMA controller? How DMA controller
works? Explain with suitable block diagram
...
Figure below shows two control signals in the CPU that facilitate the DMA transfer
...
The CPU activates the bus grant (BG) output to
inform the external DMA that the buses are in the high-impedance state
...
When the DMA terminates the transfer, it
disables the bus request line
...
When the DMA takes control of the bus system, it communicates directly with the
memory
...
The unit
communicates with the CPU via the data bus and control lines
...
The RD (read) and WR (write) inputs are
bidirectional
...
When BG = 1, the CPU has relinquished the buses and the DMA can communicate
directly with the memory by specifying an address in the address bus and activating
the RD or WR control
...
For each word that is transferred, the DMA increments its
address registers and decrements its word count register
...
For a
high-speed device, the line will be active as soon as the previous transfer is
completed
...
If the peripheral speed is slower, the DMA request line
may come somewhat later
...
When the peripheral requests a
transfer, the DMA requests the buses again
...
76
The access time of a cache memory is 120 ns and that of main memory 900 ns
...
The hit ratio for read access only is 0
...
A write-through procedure is used
...
Ans
...
9 x 120 + 0
...
cache access
memory access
ii) 0
...
8 x 200 = 180 + 100 = 280 nsec
...
77
Hit ratio = 0
...
9 = 0
...
(i) DMA data transfer
...
(iv) RISC architecture
...
i)
DMA data transfer:The position of the DMA controller among the other components in a computer
system is shown in figure
...
The DMA has its own address,
which activates the DS and RS lines
...
Once the DMA receives the start control command, it can start the transfer
between the peripheral device and the memory
...
Thus the DMA controls the read or write operations
and supplies the address for the memory
...
For each word that is transferred,
the DMA increments its address registers and decrements its word count register
...
For a high-speed device, the line will be active as soon as the
previous transfer is completed
...
If the peripheral speed is slower, the
DMA request line may come somewhat later
...
When the
peripheral requests a transfer, the DMA can continue to execute its program
...
DMA transfer is very useful in many applications
...
It is also useful for updating the
display in an interactive terminal
...
The
contents of the memory can be transferred to the screen periodically by means of
DMA transfer
...
Similarly, a destination unit that initiates
the transfer has no way of knowing whether the source unit has actually placed the
data on the bus
...
The timing diagram shows the
exchange of signals between the two units
...
The source
unit initiates the transfer by placing the data on the bus and enabling its data valid
signal
...
The source unit then disables its data valid signal, which
invalidates the data on the bus
...
The source does not send the next
data item until after the destination unit shows its readiness to accept new data by
disabling its data accepted signal
...
The
rate of transfer is determined by the slowest unit
...
Notes that the
name of the signal generated by the destination unit
83
AC07/AT07
Computer Architecture
Destination-initiated transfer using handshaking
...
Enable ready for data
...
Enable data valid
...
Disable ready for data
...
Invalidate data on bus
(initial state)
...
The source unit in
this case does not place data on the bus until after it receives the ready for data
signal from the destination unit
...
Note that the sequence of events in
both cases would be identical if we consider the ready for data signal as the
complement of data accepted
...
iii)
Isolated vs memory mapped I/O:In the isolated I/O configuration, the CPU has distinct input and output instructions,
and each of these instructions is associated with the address of an interface register
...
The isolated I/O method isolates memory and I/O addresses so that
memory address values are not affected by interface address assignment since each
has its own address space
...
This configuration is referred to as memory-mapped I/O
...
The CPU can manipulate I/O data residing in interface registers with the same
instructions that are used to manipulate memory words
...
The advantage is
that the load and store instructions used for reading and writing from memory can be
used to input and output data from I/O registers
...
With memory-mapped
I/O all instructions that refer to memory are also available for I/O
...
The major characteristics of a RISC
processor are:
1
...
2
...
3
...
4
...
5
...
6
...
7
...
8
...
Other characteristics attributed to RISC architecture are:
1
...
2
...
3
...
4
...
A large number of registers is useful for storing intermediate results and for
optimizing operand references
...
Thus register-tomemory operations can be minimized by keeping the most frequent accessed
operands in registers
...
Q
...
Ans
...
The possibility of using a randomaccess memory for the cache is investigated
...
The nine least significant bits constitute the index field and the
remaining six bits form the tag field
...
The number of bits in the
index field is equal to the number of address bits required to access the cache
memory
...
The n bit memory address is divided into two fields: k bits for the
index field and the n-k bits for the tag field
...
The internal organization of the words in the cache memory is as shown
...
When a new
word is first brought into the cache the tag bits are stored alongside the data bits
...
The tag field of the CPU address is compared with the tag in the
word read from the cache
...
If there is no match, there is a miss and the required word is read
from main memory
...
The disadvantage of direct mapping is that the hit ratio
can drop considerably if two or more words whose addresses have the same index
but different tags are accessed repeatedly
...
To see how the direct-mapping
organization operates, consider the numerical example shown
...
Suppose
that the CPU now wants to access the word at address 02000
...
The two tags are then compared
...
Therefore, the
main memory is accessed and the ata word 5670 is transferred to the CPU
...
Q
...
The references to memory at any given internal of time tend to be confined within a
few localized areas in memory
...
The locality of reference property, that over a short internal of
time, the addresses generated by a typical program refer to a few localized area of
memory repeatedly, while the remainder of memory is accessed relatively
infrequently
...
80
A virtual memory system has an address space of 8k words, memory space of 4k
words and Page & Block size of 1k words
...
4, 2, 0, 1, 2, 6, 1, 4, 0, 1, 0, 2, 3, 5, 7
Determine the four pages that are resident in main memory after each Page
reference change if the replacement algorithm used is (i)FIFO (ii) LRU
...
An address space of 8K and a memory of 4K words and page Block size of 1K
words
...
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Block 0
Block 1
Block 2
Block 3
Address Space
N = 8K = 213
Memory Space
M = 4K = 212
(1)
FIFO
String 4, 2, 0, 1, 2, 6, 1, 4, 0, 1, 0, 2, 3, 5, 7
4
4
2
4
2
0
4
2
0
1
4
2
0
1
2
6
6
2
0
1
1
4
6
4
0
1
0
87
1
0
2
6
4
2
1
3
6
4
2
3
5
5
4
2
3
7
5
7
2
3
AC07/AT07
Computer Architecture
Page fault by FIFO = 10
LRU
(2)
4
4
Q
...
Ans
...
The CPU communicates with the DMA through the
address and data buses as with any interface unit
...
The CPU initializes the DMA through the data
bus
...
When the peripheral device sends a
DMA request, the DMA controller activates the BR line, informing the CPU to
relinquish the buses
...
The DMA then puts the current value of its address register
into the address bus, initiates the RD or WR signal, and sends a DMA acknowledge
to the peripheral device
...
The direction of transfer depends on the status of the BG line
...
When the peripheral device receives a DMA acknowledge, it
puts a word in the data bus (for write) or receives a word from the data bus (for
read)
...
The peripheral unit can then communicate with memory through
the data bus for direct transfer between the two units while the CPU is momentarily
disabled
...
82
How data is transmitted in synchronous serial communication system?
Ans
...
In synchronous transmission, where an entire block
of character is transmitted, each character has a parity bit for the receiver to check
...
This character is called a
longitudinal redundancy check (LRC) and is the accumulation of the exclusive OR
of all transmitted character
...
The calculated and received
LRC should be equal for error-free messages
...
Q
...
Ans
...
Total no
...
84
A Computer uses a memory unit with 256K words of 32 bits each
...
The instruction has four parts: an
indirect bit, an operation code, a register code part to specify one of 64 registers and
an address part
...
(iii) How many bits are there in the data and address inputs of the memory?
Ans
...
Operation Code = 7 bits
32-25 = 7 bits for opcode
Register Code = 6 bits
> 26 = 64
(ii)
Instruction Word Format
1
7
6
18 = 32 bits
I
Opcode
Register Code
Address
(iii)
Q
...
15
14
1
OP Code
Instruction format fig
...
a
...
A 12
bit address, and an indirect address mode bit designated by I
...
A direct address instruction is shown
in fig
...
It is placed in address 22 in memory
...
The operation code specifies an ADD
instruction, and the address part is the binary equivalent of 457
...
Indirect address:The instruction in address 35 shown in fig
...
Therefore, it is
recognized as an indirect address instruction
...
The control goes to address 300 to find the address of the
operand
...
The operand found in
address 1350 is then added to the content of AC
...
The first reference is needed
to read the address of the operand the second is for the operand itself
...
(1)
ADD to AC
(2)
ADD to AC
(3)
LDA: Load to AC
(4)
STA: Store AC
91
AC07/AT07
(5)
(6)
(7)
Q
...
Explain with the help of an example
...
The multiplication of two floating-point numbers requires that we multiply
the mantissas and add the exponents
...
Check for zeros
...
Add the exponents
...
Multiply the mantissas
...
Normalize the product
...
The flowchart for floating-point multiplication is shown in Fig
...
If either operand is equal to zero,
the product in the AC is set to zero and the operation is terminated
...
The exponent of the multiplier is in q and the adder is between exponents a and b
...
Since both exponents are biased by the addition of a
constant, the exponent sum will have double this bias
...
The mantissas are then multiplied as in the fixed – point case with the
product residing in A and Q
...
If it
is a 1, the product is already normalized
...
Q
...
Use AND gates and binary address
...
93
AC07/AT07
Q
...
P=
(X-Y+Z)*(M*n-o)
Q+R*S
By using
(i)
Two address instructions
(ii)
One address instructions
(iii)
Zero address instructions
Ans
...
89
TOS ← X-Y
TOS ← Z
TOS ← (X-Y+Z)
TOS ← M
TOS ← N
TOS ← M*N
TOS ← O
TOS ← (M*N-O)
TOS ← (X-Y+Z) x (M*N-O)
TOS ← R
TOS ← S
TOS ← R*S
TOS ← Q
TOS ← Q-R*S
Z
M
N
O
R
S
Q
O
P
M [P] ← TOS
Convert the following arithmetic expression from infix notation to RPN
...
B*D+C*E
In RPN
BD*CE*+
Infix
A*B+B*(BxD+CxE)
RPN
AB*BBD*CE*+*+
Q
...
Subroutines:Frequently, the same piece of code must written over again in many different parts
of a program
...
A set of
common instructions that can be used in a program many times is called a
subroutine
...
After the subroutine has been
executed, a branch it is made back to the main program
...
The
subroutine shifted the number and left it there to be accepted by the main program
...
The accumulator can be used for a single input
parameter and a single output parameter
...
Two operands must be
transferred to the subroutine and the subroutine must return the result of the
operation
...
The other operand is inserted in the location following the BSA instruction
...
Moreover, the calling program
can reserve one or more locations for the subroutine to return results that are
computed
...
If there is a large amount of data to be
transferred , the data can be placed in a block of storage and the address of the first
item in the block is then used as the linking parameter
...
The length of the
block is 16 words
...
The items
are retrieved from their blocks by the use of two pointers
...
When the subroutine completes its operation, the data
required is in the block starting address
...
Q
...
Ans
...
92
Show the hardware implementation of following statement:
xyT0 +T1 +y'T2:AR ← AR+1
Where x, y are control functions and T0, T1, T2 are T - State
96
AC07/AT07
Computer Architecture
Ans
...
93
Represent the given conditional control statement by two register transfer
Statements with Control functions
...
(2)
Ans: The two resistor transfer statements are :
P: R1 R2
P' Q: R1 R3
Q
...
Ans
...
95 If P = ∑ (m 0 , m 3 , m 4 , m8 , m12 , m13 , m15 ) and Q = Π (M1 , M 4 , M 5 , M12 , M14 ) ,
Then find the expression for X = P ⊕ Q in SOP & POS
...
P = ∑ (m 0 , m 3 , m 4 , m8 , m12 , m13 , m15 )
Q = π (M1, M4, M5, M12, M14)
Mo = 0000, M3 = 0011, M4 = 0100
M8 = 1000, M12 = 1100, M13 = 1101, M15 = 1111
M1 = 0001, M4 = 0100, M5 = 0101,
M12 = 1100, M14 = 1110
98
(8)
AC07/AT07
Q
...
Ans
...
During the design of sequential circuits, the required transition form present state to
next state and to find the FF input conditions that will cause the required transition
...
Such a table is called a flip-flop excitation table
...
97
SR Flip-flop
Q(t+1)
S
0
0
1
1
0
0
1
X
JK flip-flop
Q(t+1)
J
0
0
1
1
0
x
1
x
D Flip-flop
Q(t+1)
DR
0
0
1
1
0
0
1
1
R
X
0
1
0
Q(t)
0
0
1
1
K
x
x
1
0
T flip-flop
Q(t)
Q(t+1)
0
0
0
1
1
0
1
1
DR
0
1
1
0
Simplify the Boolean function F together with don't care condition D in
(i) Sum of Product
(ii) Product of sums
F(w, x, y, z) = Σ (0, 1, 2,3, 7, 8, 10)
D(w, x, y, z) = Σ (5, 6, 11, 15)
Ans
...
(ii)
Q
...
Ans
...
99
Design a binary Incrementer and binary Decrementer
...
Incrementer circuit
A – 1 = A + 2’s complement of 1 = A + 1111
Q
...
Also, give the register transfer statements
...
The interrupt is handled by the computer can be explained by means of the
flowchart
...
When R = 0, the
computer goes through an instruction cycle
...
If it is 0, it indicates that the
programmer does not want to use the interrupt, so control continues with the next
instruction cycle
...
If both flags are 0, it
indicates that neither the input nor the output registers are ready for transfer of
information
...
At the end
of the execute phase, control checks the value of R, and if it is equal to 1, it goes to
an interrupt cycle instead of an instruction cycle
...
that an interrupt
occurs and R is set to 1 while the control is executing the instruction at address 255
...
The programmer has previously placed an inputoutput service program in memory starting from address 1120 and a BUN 1120
instruction at address 1
...
This flip-flop is set to 1 if IEN = 1 and either FG1 or FG0 are equal to 1
...
This can be expressed with the
following register transfer statements
...
101
Explain all the phases of instruction cycle
...
Instruction Cycle:A program residing in the memory unit of the computer consists of a sequence of
instructions
...
Each instruction cycle in turn is subdivided into a sequence of sub
cycles or phases
...
Fetch an instruction from memory
...
Decode the instruction
3
...
4
...
Fetch and Decode:The program counter PC is loaded with the address of the first instruction in the
program
...
After each clock pulse, SC is incremented by one, so that the timing
103
AC07/AT07
Computer Architecture
signals go through a sequence T0, T1, and so on
...
T0 : AR
PC
T1 : IR
M[AR], PC
PC + 1
T2 : D0
...
Place the content of PC onto the bus by making the bus selection inputs S2 S1 S0
equal to 010
...
Transfer the content of the bus to AR by enabling the LD input of AR
...
In order
to implement the second statement T1: IR M[R], PC PC +1
It is necessary to use timing signal T1, to provide the following connections in the
bus system
...
Enable the read input of memory
...
Place the content of memory onto the bus by making
S2 S1 S0 = 111
...
Transfer the content of the bus to IR by enabling the LD input of IR
...
Increment PC by enabling the INR input of PC
...
The selected
operation is activated with the clock transition associated with timing signal T3
...
However, the sequence
counter SC must be incremented with D7'I'T3 = 1, so that the execution of the
memory-reference instruction can be continued with timing variable T4
...
After the instruction is executed, SC is cleared to 0 and control
returns to the fetch phase with To = 1
...
We will adopt the convention that if SC is incremented,
we will not write the statement SC
SC + 1, but it will be implied that the control
goes to the next timing signal is sequence
...
104
AC07/AT07
Q
...
(Explain both pass 1 and pass 2 with flow
chart)
...
LC is initially set to 0
...
Labels are
neglected during the second pass, so the assembler goes immediately to the
instruction field and proceeds to check the first symbol encountered
...
A match with ORG sends the assembler to a
subroutine that sets LC to an initial value
...
An operand pseudo instruction causes a conversion of the
operand into binary
...
The location counter is then incremented by 1 and the
assembler continues to analyze the next line of code
...
103
Computer Architecture
Write an assembly language program to multiply two positive numbers by a
repeated addition method
...
Ans
...
ORG 100
LOP CLE
/Clear
LDA Y
/Load multiplier
CIR
/Transfer multiplier bit to E
STAY
/Store shifted multiplier
SZE
/Check if bit is zero
BUN ONE
/Bit is one; go to ONE
BUN ZRO
/Bit is one; go to ZRO
ONE, LDAX
/Load multiplicand
ADD P
/Add to partial product
STA P
/Store partial product
CLE
/Clear E
ZRO, LDA X
/Load multiplicand
CIL
/Shift left
STA X
/Store shifted multiplicand
ISZ CTR
/Increment counter
BUN LOP
/Counter not zero; repeat loop
HLT
/Counter is zero; halt
CTR, DEC – 8
/This location serves as a counter
X,
HEX 000F
/Multiplicand stored here
Y,
HEX 000B
/Multiplier stored here
P,
HEX 0
/Product formed here
Q
...
(ii)
Program interrupt and subroutine call & return
...
Autoincrement and Autodecrement mode :The register is incremented or decremented after (or before) its value is used to
access memory
...
This is achieved by using the increment or decrement instruction
...
During the execution of program, a subroutine may be called to
perform its function many times at various points in the main program
...
The indirect BUN instruction at the end of the subroutine performs the function
referred to as a subroutine return
...
When a subroutine is called, the main program must transfer
the data
...
It is necessary for the subroutine to have access to data from the
calling program and to return results to that program
...
Two operands must be transferred to the
subroutine and the subroutine must return the result of the operation
...
105
What is a microinstruction? Write a micro instruction code format and explain all
the fields in it
...
Each word in control memory contains within it a microinstruction
...
A sequence
of microinstruction constitutes a microprogram
...
OP code
Computer
Instruction
Mapping Bits
Microinstruction
address
0
0
0
1
1
1
x
1
x
0
x
1
address
x
1
0
0
0
0
Instruction code to microinstruction address
A special type of branch exist when a microinstruction specifies a branch to the first
word in control memory where a microprogram routine for an instruction is located
...
Micro instruction format is 20 bits in length
...
The three fields F1, F2 and F3 specify micro operations for the
computer
...
* the AD field contains a branch address
...
F1, F2, F3 : Micro operation fields
3
3
F1
F2
3
F3
2
CD
2
BR
CD : Condition for branching
BR : Branch field
AD : Address field
* Micro operations are sub-divided into three fields of three bits each
...
This gives 21
micro operations
...
Symbols and Binary Code for Micro Instruction Fields
108
7
AD
AC07/AT07
Computer Architecture
F1
000
001
010
011
100
101
110
111
Micro operation
None NOP
AC AC + DR
AC 0
AC AC + 1
AC DR
AR DR (0-10)
AR PC
M [AR] DR
Symbol
F2
000
001
010
011
100
101
110
111
Micro Operation
None NOP
AC AC-DR
AC AC ∨ DR
AC AC ∧ DR
DR M[AR]
DR AC
DR DR+1
DR(0-10) PC
Symbol
F3
000
001
010
011
100
101
110
111
Micro Operation
None NOP
AC AC ⊕ DR
AC AC COM
AC shl AC
AC shr AC
PC PC+1
PC AR
Reserved
Symbol
ADD
CLRAC
INCAC
DRTAC
DRTAR
DCTAR
WRITE
SUB
OR
AND
READ
ACTDR
INCDR
PCTDR
XOR
SHL
SHR
INCPC
ARTPC
CD
Condition Symbol
00 Always=1
U
01 DR(15) 1 Indirect address bit
10 AC(15) S Sign bit of AC
11 AC=0
Z Zero value in AC
BR
00
01
10
11
Q
...
Ans
...
The use of a micro
program involves placing all control variables in words of ROM for use by the
control unit through successive record operation
...
107
000
000
001
000
000
000
000
000
000
000
111
000
000
001
100
111
110
000
101
000
101
AD
000
100
000
000
000
000
000
000
000
101
000
000
000
000
101
000
000
100
000
000
000
000
000
000
000
000
110
000
000
000
000
000
000
000
000
000
101
000
01
00
00
00
10
00
01
00
01
00
00
01
01
00
00
00
00
00
00
01
00
00
00
00
00
01
00
01
00
00
01
01
00
00
00
00
00
11
1000011
0000010
1000000
1000000
0000110
1000000
1000011
1000000
1000011
0001010
1000000
1000011
1000011
0001110
0001111
1000000
1000000
1000010
0000000
010
000
000
000
00
00
00
10
1000100
0000000
Formulate a four segment instruction pipeline for a computer
...
Ans
...
This
causes the instruction fetch and execute phases to overlap and perform simultaneous
operations
...
This is a type of unit that forms a queue rather than a stack
...
An
instruction stream can be placed in a queue, waiting for decoding and processing by
the execution segment
...
The computer needs to process each instruction with the following
sequence of steps
...
Fetch the instruction from memory
...
Decode the instruction
...
Calculate the effective address
...
Fetch the operands from memory
...
Execute the instruction
...
Store the result in the proper place
...
Different segments may take different times to operate on the
incoming information
...
For
example, a register mode instruction does not need an effective address calculation
...
The design of an instruction pipeline will be most efficient if the instruction cycle is
divided into segments of equal duration
...
Q
...
How many address lines are required to access
memory
...
Memory organization:-
Address lines:-
111
AC07/AT07
Computer Architecture
128 = 128 = 27
512 = 29
Address lines = 16
Q
...
Ans
...
The two signs As, and Bs are
compared by an exclusive-OR gate
...
For an add operation, identical signs
dictate that the
magnitudes are added
...
The magnitudes are added with a microoperation EA A + B,
where EA is a register that combines E and A
...
The value of E is transferred into the addoverflow flip-flop AVF
...
110
Computer Architecture
Ram wants to purchase a bicycle
...
The bicycle
which has either a hand brake or foot brake, No bicycle has both type of brakes
...
Ans
...
111
Write short notes on followings
(i) Daisy chaining priority
...
(iii) Handshaking method for data transfer
...
(i)
Daisy chaining priority:The daisy-chaining method of establishing priority consists of a serial connection of
all devices that request an interrupt
...
This method of connection between three devices and the CPU is shown
...
If
any device has its interrupt signal in the low-level state, the interrupt line goes to the
low-level state and enables the interrupt input in the CPU
...
This is equivalent to a negative logic OR operation
...
(ii) Direct Memory Access:The transfer of data between a fast storage device such as magnetic disk and memory is
often limited by the speed of the CPU
...
This transfer technique is called direct memory access (DMA)
...
CPU bus signals for DMA transfer
The figure shows two control signals in the CPU that facilitate the DMA transfer
...
The CPU activates the bus grant (BG) output to inform the
external DMA that the buses are in the high-impedance state
...
When the DMA
terminates the transfer, it disables the bus request line
...
When the DMA takes control of the bus system, it communicates directly
with the memory
...
Similarly, a
destination unit
Input output organization
Data bus
Data valid
Data accepted
Source
unit
Destination
unit
(a) Block diagram
Data bus
Valid data
Data valid
Data accepted
(b) Timing diagram
Source unit
Destination unit
Place data on bus
...
Accept data from bus
...
Disable data valid
...
Disable data accepted
...
(Initial state)
...
The two handshaking lines are data valid, which is
generated by the source unit, and data accepted, generated by the destination unit
...
The
sequence of events listed in part (c) shows the four possible states that the system
can be at any given time
...
The data accepted signal is activated
by the destination unit after it accepts the data from the bus
...
The destination
unit then disables its data accepted signal and the system goes into its initial state
...
This scheme
allows arbitrary delays from one state to the next and permits each unit to respond at
its own data transfer rate
...
Destination initiated data transfer:The destination-initiated transfer using handshaking lines
...
The source unit in this case does not place data on the bus until
after it receives the ready for data signal from the destination unit
...
Note that the sequence of events in both cases would be identical if we consider the
ready for data signal as the complement of data accepted
...
This disadvantage of the strobe method is that the source unit that initiates the
transfer has no way of knowing whether the destination unit has actually received
the data item that was placed in the bus
...
116
AC07/AT07
Computer Architecture
(iv)
Associative Memory:The time required to find an item stored in memory can be reduced considerably if
stored data can be identified for access by the content of the data itself rather than by
an address
...
A memory unit accessed by content is called an associative memory or
content addressable memory (CAM)
...
Q
...
i)
ii)
Show the Truth Table's for the Following functions:f(w, x, y, z) = w + x + y + z
f(w, x, y, z) = wx + xz + y
Ans
...
113
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Construct a T flip flop using a
i)
D - FF
0
1
0
1
1
1
1
1
Output= wx + xz + y
1
1
0
0
1
1
0
1
1
1
0
0
1
1
1
1
ii)
J-K FF
Ans
...
114
Computer Architecture
Explain Ven Neumann architector and stored program concept
...
In 1946, John Von Neumann and his colleagues began the design of a new stored –
program computer referred to as IAS computer
...
(b)
An arithmetic and logic unit (ALU) capable of operating on binary data
...
(d)
Input and output (I/O) equipment operated by the control unit
...
Both data and instructions are stored there
...
120
AC07/AT07
Computer Architecture
Each number is represented by a sign bit and a 39- bit value
...
John Von Neumann gave the idea of storing
‘Programme’ and ‘Data’ in the same memory
...
It makes the operation of computer
automatic
...
115
Show the hardware to implement the following micro-operations
...
L : α shl (x)
Ans
...
116
(i)
α : cir (x)
Discuss the properties of an ideal instruction set computer
...
(i)
(ii)
(iii)
Q
...
Input and output instructions are needed for communication between the
computer and the user
...
Explain instruction cycle
...
Ans
...
The program is executed in the computer by going
through a
cycle for each instruction
...
The sequence counter SC is cleared to 0, providing a decoded tining
signal To
...
To : AR ← PC
T1 : IR ← M[AR], PC ← PC+1
Q
...
Ans
...
119
S0
0
1
0
1
Output
E=A^B
E=A ∨ B
E=A
Shl
Operation
AND
ADD
Complement
Discuss the different addressing modes of an instruction
...
In this mode the operands are specified implicitly in the definition of the instruction
...
In
other words, an immediate-mode instruction has an operand field rather than an
address field
...
Register mode:- In this mode the operands are in registers that reside within in
CPU
...
A kbit field can specify any one of 2k registers
...
Before using a register
indirect mode instruction, the programmer must ensure that the memory address of
the operand is placed in the processor register with a previous instruction
...
When the address stored in the register refers to a
table of data is memory
...
Direct Address Mode:- In this mode the effective address is equal to the address
part of the instruction
...
Control fetches the
instruction from memory and uses its address part to access memory again to read
the effective address
...
When
this number is added to the content of the program counter, the result produces an
123
AC07/AT07
Computer Architecture
effective address whose position in memory is relative to the address of the next
instruction
...
Base Register Addressing Mode:- In this mode the content of a base register is
added to the address part of the instruction to obtain the effective address
...
120
What is the significance of program status word
...
The collection of all status bit condition in the CPU is called a program status
word or PSW
...
The CPU does not
respond to an interrupt until the end of an instruction execution
...
If an interrupt is pending, control goes to hardware interrupt cycle
...
The PSW is
transferred to the status register and the return address to the program counts
...
Q
...
Ans
...
Software interrupt is a
special call instruction that behaves like an interrupt rather than a subjective call
...
This instruction provides means for switching from a CPU user mode
to the supervision mode
...
Q
...
2’s
Ans
...
If one of these numbers is
positive then the other number will be negative with the some magnitude and viceversa
...
For example, 2's complement of 0101
is 1011
...
For an n bit number the maximum positive
number is (2n-1-1) and the maximum negative number is -2n-1
Q
...
124
AC07/AT07
Computer Architecture
Ans
...
124
BR=01110
BR +1=10010
Initial
ashr
AC
QR
00000
10010
00000
01001
10010
Subtract BR
10010
ashr
11001
00100
01110
Add BR
00111
ashr
00011
10010
ashr
00001
11001
10010
Subtract BR
10011
ashr
11001
11100
Final Product = 1100111100
Qn+1
SC
0
0
101
100
1
011
0
0
010
001
1
000
Explain the use of time out mechanism in handshaking data transfer scheme
...
The handshaking scheme provides a hight degree of flexibility and reliability
because the successful completion of a data transfer relies on active participation by
both units
...
An error
can be detected by means of a timeout mechanism, which produces an alarm if the
data transfer is not completed within a predetermined time
...
Q
...
Ans
...
Virtual memory is used to give programmers the
illusion that they have a very large memory at their disposal, even though the
computer actually has a relatively small main memory
...
In a virtual memory system, programmers are told that they
have the total address space at their disposal
...
In
our example, the address field of an instruction code will consist of 20 bits but
physical memory addresses must be specified with only 15 bits
...
at this
address must be taken from physical memory because access to auxiliary storage for
individual words will be prohibitively long
...
The mapping is a
dynamic operation, which means that every address is translated immediately as a
word is reference by CPU an address space of 8k and a memory space of 4k
...
A virtual address has 13 bits
...
A system with
n pages and m blocks will be marked with block numbers and all others will be
empty
...
In this way the
size of the memory is reduced and each location is fully utilized
...
1 0 1
Line number
1 1 1
0
0
0 0 1
1
1
0 1 0
0
0
1 0 1
0
1
1 1 0
1
Argument register
0
Page no
...
containing a page number together with its corresponding block number
...
If a
match occurs, the word is read from memory and its corresponding block
...
If a
match occurs, the word is read from memory and its corresponding block number is
127
AC07/AT07
Computer Architecture
extracted
...
The
first three bits specify a field for storing the page number
...
The virtual address is placed in the
argument register
...
If the page number is
found, the 5-bit word is read out from memory
...
If no
match occurs, a call to the operating system is generated to bring the required page
from auxiliary memory
...
126
State the advantages of cache memory
...
Advantages –
(1)
The average memory access time of a computer system can be improved
by use of a cache
...
(3)
Very little or no time wasted when searching for words in the cache
...
(5)
Program segment and data frequently needed by CPU are stored in cache
memory and hence fast processing
...
127
Compare memory mapped I/O vs I/o mapped I/O
...
1)
Memory mapped I/O use memory type instructions to access I/O data
...
2) The load and store instructions are for reading and writing from
memory can be used to input and output data from I/O registers
...
4) In I/O mapped I/O configuration, the CPU has distinct input and output
instructions, and each of these instructions is associated with the address of an
interface register
...
Q
...
Ans
...
The multiplication algorithm can be subdivided
into four parts
...
Check for zeros
...
Add the exponents
...
Multiply the mantissas
...
Normalize the product
Title: computer architecture
Description: Most important questions with solution which generally asked in exams ...
Description: Most important questions with solution which generally asked in exams ...